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[/] [minsoc/] [branches/] [rc-1.0/] [syn/] [altera/] [Makefile] - Rev 93
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MINSOC = ..MINSOC_DEFINES = ${MINSOC}/backendMINSOC_RTL = ${MINSOC}/rtl/verilogMINSOC_STARTUP_RTL = ${MINSOC_RTL}/minsoc_startupUART_RTL = ${MINSOC_RTL}/uart16550/rtl/verilogADV_DEBUG_ROOT = ${MINSOC_RTL}/adv_debug_sys/HardwareDEBUG_RTL = ${ADV_DEBUG_ROOT}/adv_dbg_if/rtl/verilogOR1200_RTL = ${MINSOC_RTL}/or1200/rtl/verilogETH_RTL = ${MINSOC_RTL}/ethmac/rtl/verilogBUILD_SUPPORT = $(MINSOC)/syn/buildSupportPROJECT_DIR = $(MINSOC)/prj/alterahelp:@echo " all: Synthesize and implement the SoC, then generate a bit stream"@echo ""@echo " bitgen: Generate a programming file for the target FPGA"@echo " map: Express the SoC netlist in the target hardware"@echo " fit: Place the target hardware, then route the wires"@echo " sta: Perfom a timming analysis"@echo " eda: Generate a netlist of the hardware"@echo ""@echo " clean: Delete all superfluous files generated by Altera tools"@echo " distclean: Delete all generated files"all: bitgen eda stamap: minsoc_top.map.summaryfit: minsoc_top.fit.summarybitgen: minsoc_top.sofeda: minsoc_top.eda.summarysta: minsoc_top.sta.summary#minsoc_top.map.summary: ${MINSOC_RTL}/*.v $(UART_RTL)/*.v $(ADV_DEBUG_ROOT)/*.v $(DEBUG_RTL)/*.v $(OR1200_RTL)/*.v $(ETH_RTL)/*.v ${MINSOC_DEFINES}/minsoc_defines.v minsoc_top.qsfminsoc_top.map.summary: ${MINSOC_DEFINES}/minsoc_defines.v minsoc_top.qsfquartus_map minsoc_top --write_settings_files=offminsoc_top.fit.summary: minsoc_top.map.summaryquartus_fit minsoc_top --write_Settings_files=off --pack_register=minimize_areaminsoc_top.sof: minsoc_top.fit.summaryquartus_asm minsoc_topminsoc_top.sta.summary: minsoc_top.fit.summaryquartus_sta minsoc_topminsoc_top.eda.summary: minsoc_top.fit.summaryquartus_eda minsoc_top --write_settings_files=offdistclean:$(RM) *.sofmake cleanclean:$(RM) *.rpt *.summary *.jdi *.smsg *.pin *.qpfrm -fr db incremental_db
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