URL
https://opencores.org/ocsvn/minsoc/minsoc/trunk
Subversion Repositories minsoc
[/] [minsoc/] [branches/] [verilator/] [syn/] [altera/] [Makefile] - Rev 93
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MINSOC = ..
MINSOC_DEFINES = ${MINSOC}/backend
MINSOC_RTL = ${MINSOC}/rtl/verilog
MINSOC_STARTUP_RTL = ${MINSOC_RTL}/minsoc_startup
UART_RTL = ${MINSOC_RTL}/uart16550/rtl/verilog
ADV_DEBUG_ROOT = ${MINSOC_RTL}/adv_debug_sys/Hardware
DEBUG_RTL = ${ADV_DEBUG_ROOT}/adv_dbg_if/rtl/verilog
OR1200_RTL = ${MINSOC_RTL}/or1200/rtl/verilog
ETH_RTL = ${MINSOC_RTL}/ethmac/rtl/verilog
BUILD_SUPPORT = $(MINSOC)/syn/buildSupport
PROJECT_DIR = $(MINSOC)/prj/altera
help:
@echo " all: Synthesize and implement the SoC, then generate a bit stream"
@echo ""
@echo " bitgen: Generate a programming file for the target FPGA"
@echo " map: Express the SoC netlist in the target hardware"
@echo " fit: Place the target hardware, then route the wires"
@echo " sta: Perfom a timming analysis"
@echo " eda: Generate a netlist of the hardware"
@echo ""
@echo " clean: Delete all superfluous files generated by Altera tools"
@echo " distclean: Delete all generated files"
all: bitgen eda sta
map: minsoc_top.map.summary
fit: minsoc_top.fit.summary
bitgen: minsoc_top.sof
eda: minsoc_top.eda.summary
sta: minsoc_top.sta.summary
#minsoc_top.map.summary: ${MINSOC_RTL}/*.v $(UART_RTL)/*.v $(ADV_DEBUG_ROOT)/*.v $(DEBUG_RTL)/*.v $(OR1200_RTL)/*.v $(ETH_RTL)/*.v ${MINSOC_DEFINES}/minsoc_defines.v minsoc_top.qsf
minsoc_top.map.summary: ${MINSOC_DEFINES}/minsoc_defines.v minsoc_top.qsf
quartus_map minsoc_top --write_settings_files=off
minsoc_top.fit.summary: minsoc_top.map.summary
quartus_fit minsoc_top --write_Settings_files=off --pack_register=minimize_area
minsoc_top.sof: minsoc_top.fit.summary
quartus_asm minsoc_top
minsoc_top.sta.summary: minsoc_top.fit.summary
quartus_sta minsoc_top
minsoc_top.eda.summary: minsoc_top.fit.summary
quartus_eda minsoc_top --write_settings_files=off
distclean:
$(RM) *.sof
make clean
clean:
$(RM) *.rpt *.summary *.jdi *.smsg *.pin *.qpf
rm -fr db incremental_db
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