Subversion Repositories minsoc

PROJECT_DIR=(backend rtl/verilog rtl/verilog/minsoc_startup rtl/verilog/or1200/rtl/verilog rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog rtl/verilog/ethmac/rtl/verilog rtl/verilog/uart16550/rtl/verilog)
PROJECT_SRC=(minsoc_defines.v
timescale.v
interconnect_defines.v
minsoc_top.v
minsoc_tc_top.v
minsoc_onchip_ram.v
minsoc_onchip_ram_top.v
minsoc_clock_manager.v
altera_pll.v
xilinx_dcm.v
minsoc_xilinx_internal_jtag.v
spi_top.v
spi_defines.v
spi_shift.v
spi_clgen.v
OR1K_startup_generic.v)