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https://opencores.org/ocsvn/minsoc/minsoc/trunk
Subversion Repositories minsoc
[/] [minsoc/] [trunk/] [prj/] [src/] [or1200_top.prj] - Rev 85
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PROJECT_DIR=rtl/verilog/or1200/rtl/verilogPROJECT_SRC=(or1200_spram_512x20.vor1200_spram_64x24.vor1200_du.vor1200_spram_2048x32_bw.vor1200_rf.vor1200_alu.vor1200_dmmu_top.vor1200_lsu.vor1200_spram_1024x32.vor1200_dc_top.vor1200_cpu.vor1200_gmultp2_32x32.vor1200_immu_top.vor1200_dpram_256x32.vor1200_tt.vor1200_iwb_biu.vor1200_rfram_generic.vor1200_dc_tag.vor1200_spram_2048x8.vor1200_immu_tlb.vor1200_ic_tag.vor1200_spram_64x14.vor1200_spram_32x24.vor1200_dpram_32x32.vor1200_xcv_ram32x8d.vor1200_spram_1024x8.vor1200_mem2reg.vor1200_pm.vor1200_spram_256x21.vor1200_operandmuxes.vor1200_pic.vor1200_cfgr.vor1200_if.vor1200_qmem_top.vor1200_genpc.vor1200_defines.vor1200_wbmux.vor1200_ic_ram.vor1200_dmmu_tlb.vor1200_sb_fifo.vor1200_sprs.vor1200_tpram_32x32.vor1200_ctrl.vor1200_sb.vor1200_mult_mac.vor1200_ic_fsm.vor1200_amultp2_32x32.vor1200_reg2mem.vor1200_spram_2048x32.vor1200_except.vor1200_top.vor1200_ic_top.vor1200_dc_ram.vor1200_spram_1024x32_bw.vor1200_freeze.vor1200_spram_128x32.vor1200_dc_fsm.vor1200_wb_biu.vor1200_spram_64x22.vor1200_fpu.vor1200_spram.vor1200_spram_32_bw.vor1200_dpram.v)
