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https://opencores.org/ocsvn/minsoc/minsoc/trunk
Subversion Repositories minsoc
[/] [minsoc/] [trunk/] [sim/] [run/] [generate_bench] - Rev 167
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#!/bin/sh
iverilog -Wimplicit -Wportbind -Wselect-range -Wsensitivity-entire-array -c ../../prj/sim/minsoc_verilog.src -o minsoc_bench
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