OpenCores
URL https://opencores.org/ocsvn/mips32/mips32/trunk

Subversion Repositories mips32

[/] [mips32/] [trunk/] [Classic-MIPS/] [TestBenchs/] [fibonacci/] [assembler_output.txt] - Rev 2

Compare with Previous | Blame | View Log

[0x000000]      00110100000010000000000000000000        # ori $t0, $zero, 0 ($t0 = $zero | 0)
[0x000004]      00110100000010010000000000000001        # ori $t1, $zero, 1 ($t1 = $zero | 1)
[0x000008]      00110100000010100000000000000000        # ori $t2, $zero, 0 ($t2 = $zero | 0)
[0x00000C]      00110100000010110000000000010100        # ori $t3, $zero, 20 ($t3 = $zero | 20)
[0x000010]      00000001000010011000000000100000        # add $s0, $t0, $t1 ($s0 = $t0 + $t1)
[0x000014]      00100001001010000000000000000000        # addi $t0, $t1, 0 ($t0 = $t1)
[0x000018]      00100010000010010000000000000000        # addi $t1, $s0, 0 ($t1 = $s0)
[0x00001C]      10101101010100000000000000000000        # sw $s0, 0($t2) (mem[$t2 + 0] = $s0)
[0x000020]      00100001010010100000000000000001        # addi $t2, $t2, 1 ($t2 = $t2 + 1)
[0x000024]      00010101010010111111111111111010        # bne $t3, $t2, -6 (if ($t3 != $t2) goto -6)
[0x000028]      00110100000010010000000000000000        # ori $t1, $zero, 0 ($t1 = $zero | 0)
[0x00002C]      00110100000010100000000000000000        # ori $t2, $zero, 0 ($t2 = $zero | 0)
[0x000030]      00110100000100000000000000000000        # ori $s0, $zero, 0 ($s0 = $zero | 0)
[0x000034]      10001101010010010000000000000000        # lw $t1, 0($t2) ($t1 = mem[$t2 + 0])
[0x000038]      00000001001100001000000000100000        # add $s0, $t1, $s0 ($s0 = $t1 + $s0)
[0x00003C]      00100001010010100000000000000001        # addi $t2, $t2, 1 ($t2 = $t2 + 1)
[0x000040]      00010101010010111111111111111100        # bne $t3, $t2, -4 (if ($t3 != $t2) goto -4)
[0x000044]      10101100000100000000000000011000        # sw $s0, 24($zero) (mem[$zero + 24] = $s0)
[0x000048]      00110100000010010000000000000001        # ori $t1, $zero, 1 ($t1 = $zero | 1)
[0x00004C]      00000010000010011000100000000100        # sllv $s1, $s0, $t1 ($s1 = $s0 << $t1)
[0x000050]      10101100000100010000000000011100        # sw $s1, 28($zero) (mem[$zero + 28] = $s1)
[0x000054]      00110100000010010000000000000010        # ori $t1, $zero, 2 ($t1 = $zero | 2)
[0x000058]      00000010000010011001000000000110        # srlv $s2, $s0, $t1 ($s2 = $s0 >> $t1)
[0x00005C]      10101100000100100000000000100000        # sw $s2, 32($zero) (mem[$zero + 32] = $s2)

Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.