Subversion Repositories mips32r1

MIPS32-R1 Standalone
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The files in this directory create a complete MIPS32 processor. The top-level
module is "Processor.v". The interface includes 5 general-purpose hardware
interrupts, a non-maskable hardware interrupt, the 8 pending ISA interrupts
(for diagnostics--this can be removed), and a memory interface for both
instructions and data.

The memory interface is implemented as a four-way handshake:

    1. Read/Write request goes high.
    2. Ack goes high when data is available.
    3. Read/Write request goes low.
    4. Ack signal goes low.
            ____
    R/W: __|    |____
               ____
    Ack: _____|    |____

This interface is simple and robust but can limit the performance of the
system. In the SoC design this is currently the case, since the instruction
memory fetches only once per handshake. This greatly increases the maximum
theoretical IPC from 1 to between 3 and 4.

If your application requires maximum performance out of this processor,
you should modify the memory handshake accordingly.