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MIPS32-R1 SoC HOWTO
-------------------

This document is a step-by-step procedure for building the MIPS32 hardware
and software and running it on the XUPV5-LX110T FPGA development board. With
minimal changes, other hardware platforms may be used as well (see FAQ).

Procedure
---------

    1. Build the software toolchain. Instructions for doing this are located
       in the "Software/toolchain" directory.

    2. Open the project file "MIPS32-Pipelined-Hw.xise" located in the
       "Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw" directory. This is
       a Xilinx ISE 14.1 project file.
    
    3. Build the Block RAM core by using the Block Memory Generator in
       the Core Generator. See details below.

    4. Build the hardware project and generate the programming .bit file.
       Send the programming file to the board through Impact (you may need
       to create a new Impact project file for your system, but no options
       are needed other than the configuration .bit file targeted for the
       Virtex-5 device). A default program built into the BRAM will print
       a hello message to the LCD screen.

       Alternatively, a pre-built .bit file is located in the
       "Hardware/XUPV5-LX110T_SoC" directory. It is timed conservatively
       at 33 MHz (66 MHz bus).

    5. Compile any of the software demos located in "Software/demos" using
       the Makefile included with the demo. One of the output files from
       the compilation will have a .xum extension. This is a binary file that
       contains the code and data for the program. Use the XUM Bootloader
       software (Windows) to send the .xum file over a serial port to the
       FPGA. When the program is sent, the CPU will reset and run it.

Rebuilding the Block RAM
------------------------
    The following settings will allow you to build the Block RAM module
    and add a default program to it assuming Xilinx Block Memory Generator
    version 7.1): True Dual Port RAM, Common Clock, Byte Write Enable of 8
    bits, Write/Read width of 32 bits, Write depth of 151552 (for full
    592 KB), Always Enabled, same options for port B, Register Port A Output
    of Memory Primitives AND Memory Core (for 2R version, this can be
    customized), same settings for Port B, fill remaining locations with
    0x00000000, optionally load a .coe file with initial memory contents,
    use RSTA and RSTB. The file 'Boot.coe' provides the simple hello message
    program.

FAQ
---

    Q: What if I don't have the XUPV5-LX110T board?
    A: If you have the same Virtex 5 FPGA but a different board, all you need
       to do is update the pin locations in the User Constraints File (.ucf)
       and either make sure your clock input is 100 MHz or adjust the PLL
       in the clocking module of the design accordingly. Note that some
       hardware such as the LCD screen or piezo speaker may not be present
       on your board, in which case you should remove them from the design.

    Q: What if I don't have a Virtex 5 FPGA?
    A: Any FPGA can implement this design if it has enough logic resources.
       There are only two Xilinx-specific modules in the MIPS32 SoC design;
       the clocking module and BRAM module. Replace these with whatever suits
       your hardware. Note however that the MIPS32 memory interface uses
       byte-width write enables to memory (4 bits per 32-bit word), so if you
       use Block Memory or equivalents they must either support this or
       you must fake it somehow. You must also update the UCF.

    Q: What if I don't have or use the Xilinx development tools?
    A: If you only care about the MIPS32 processor and not the full SoC, start
       with the "Hardware/MIPS32_Standalone" directory which contains only
       Verilog files. The top-most module is "Processor.v". For the full SoC,
       copy the "Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src" directory
       to whatever development environment you use. This directory contains
       all of the Verilog files with "Top.v" as the head. The "Clocks" and
       "BRAM" directories will need to be customized for your environment,
       as well as the pin constraints.

    Q: Is there a non-Windows version of the bootloader?
    A: No, but the boot protocol is simple and can be implemented for any OS.
       See "Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/UART/
       uart_bootloader_v2.v" for a description of the protocol. If you
       implement another version of the bootloader, please contribute it back
       to the project.