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Fitter report for mips_topMon Oct 13 12:02:00 2008Version 4.2 Build 157 12/07/2004 SJ Full Version---------------------; Table of Contents ;---------------------1. Legal Notice2. Fitter Summary3. Fitter Settings4. Fitter Device Options5. Fitter Equations6. Pin-Out File7. Fitter Resource Usage Summary8. Input Pins9. Output Pins10. I/O Bank Usage11. All Package Pins12. PLL Summary13. PLL Usage14. Output Pin Default Load For Reported TCO15. Fitter Resource Utilization by Entity16. Delay Chain Summary17. Pad To Core Delay Chain Fanout18. Control Signals19. Global & Other Fast Signals20. Non-Global High Fan-Out Signals21. Fitter RAM Summary22. Interconnect Usage Summary23. LAB Logic Elements24. LAB-wide Signals25. LAB Signals Sourced26. LAB Signals Sourced Out27. LAB Distinct Inputs28. Fitter Messages----------------; Legal Notice ;----------------Copyright (C) 1991-2004 Altera CorporationAny megafunction design, and related netlist (encrypted or decrypted),support information, device programming or simulation file, and any otherassociated documentation or information provided by Altera or a partnerunder Altera's Megafunction Partnership Program may be used onlyto program PLD devices (but not masked PLD devices) from Altera. Anyother use of such megafunction design, netlist, support information,device programming or simulation file, or any other related documentationor information is prohibited for any other purpose, including, but notlimited to modification, reverse engineering, de-compiling, or use withany other silicon devices, unless such use is explicitly licensed undera separate agreement with Altera or a megafunction partner. Title to theintellectual property, including patents, copyrights, trademarks, tradesecrets, or maskworks, embodied in any such megafunction design, netlist,support information, device programming or simulation file, or any otherrelated documentation or information provided by Altera or a megafunctionpartner, remains with Altera, the megafunction partner, or their respectivelicensors. No other licenses, including any licenses needed under any thirdparty's intellectual property, are provided herein.+------------------------------------------------------------------+; Fitter Summary ;+-----------------------+------------------------------------------+; Fitter Status ; Successful - Mon Oct 13 12:02:00 2008 ;; Quartus II Version ; 4.2 Build 157 12/07/2004 SJ Full Version ;; Revision Name ; mips_top ;; Top-level Entity Name ; mips_top ;; Family ; Cyclone ;; Device ; EP1C6Q240C6 ;; Timing Models ; Final ;; Total logic elements ; 3,468 / 5,980 ( 57 % ) ;; Total pins ; 33 / 185 ( 17 % ) ;; Total virtual pins ; 0 ;; Total memory bits ; 71,680 / 92,160 ( 77 % ) ;; Total PLLs ; 1 / 2 ( 50 % ) ;+-----------------------+------------------------------------------++----------------------------------------------------------------------------------------------------------------------+; Fitter Settings ;+----------------------------------------------------+--------------------------------+--------------------------------+; Option ; Setting ; Default Value ;+----------------------------------------------------+--------------------------------+--------------------------------+; Device ; EP1C6Q240C6 ; ;; Use smart compilation ; Normal ; Normal ;; Placement Effort Multiplier ; 1.0 ; 1.0 ;; Router Effort Multiplier ; 1.0 ; 1.0 ;; Optimize Hold Timing ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;; Optimize Fast-Corner Timing ; Off ; Off ;; Optimize Timing ; Normal compilation ; Normal compilation ;; Optimize IOC Register Placement for Timing ; On ; On ;; Limit to One Fitting Attempt ; Off ; Off ;; Final Placement Optimizations ; Automatically ; Automatically ;; Fitter Initial Placement Seed ; 1 ; 1 ;; Slow Slew Rate ; Off ; Off ;; PCI I/O ; Off ; Off ;; Weak Pull-Up Resistor ; Off ; Off ;; Enable Bus-Hold Circuitry ; Off ; Off ;; Auto Global Memory Control Signals ; Off ; Off ;; Auto Packed Registers -- Cyclone ; Auto ; Auto ;; Auto Delay Chains ; On ; On ;; Auto Merge PLLs ; On ; On ;; Perform Physical Synthesis for Combinational Logic ; Off ; Off ;; Perform Register Duplication ; Off ; Off ;; Perform Register Retiming ; Off ; Off ;; Fitter Effort ; Auto Fit ; Auto Fit ;; Physical Synthesis Effort Level ; Normal ; Normal ;; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ;; Auto Register Duplication ; Off ; Off ;; Auto Global Clock ; On ; On ;; Auto Global Register Control Signals ; On ; On ;+----------------------------------------------------+--------------------------------+--------------------------------++--------------------------------------------------------------------+; Fitter Device Options ;+----------------------------------------------+---------------------+; Option ; Setting ;+----------------------------------------------+---------------------+; Enable user-supplied start-up clock (CLKUSR) ; Off ;; Enable device-wide reset (DEV_CLRn) ; Off ;; Enable device-wide output enable (DEV_OE) ; Off ;; Enable INIT_DONE output ; Off ;; Configuration scheme ; Active Serial ;; Error detection CRC ; Off ;; Reserve all unused pins ; As input tri-stated ;; Base pin-out file on sameframe device ; Off ;+----------------------------------------------+---------------------++------------------+; Fitter Equations ;+------------------+The equations can be found in E:/mips789/mips789/quartus2/mips_top.fit.eqn.+--------------+; Pin-Out File ;+--------------+The pin-out file can be found in E:/mips789/mips789/quartus2/mips_top.pin.+------------------------------------------------------------------------------------+; Fitter Resource Usage Summary ;+-----------------------------------------+------------------------------------------+; Resource ; Usage ;+-----------------------------------------+------------------------------------------+; Total logic elements ; 3,468 / 5,980 ( 57 % ) ;; -- Combinational with no register ; 2605 ;; -- Register only ; 104 ;; -- Combinational with a register ; 759 ;; ; ;; Logic element usage by number of inputs ; ;; -- 4 input functions ; 1701 ;; -- 3 input functions ; 1277 ;; -- 2 input functions ; 377 ;; -- 1 input functions ; 103 ;; -- 0 input functions ; 1 ;; ; ;; Logic elements by mode ; ;; -- arithmetic mode ; 437 ;; -- qfbk mode ; 158 ;; -- register cascade mode ; 0 ;; -- synchronous clear/load mode ; 414 ;; -- asynchronous clear/load mode ; 1 ;; ; ;; Total LABs ; 451 / 598 ( 75 % ) ;; Logic elements in carry chains ; 460 ;; User inserted logic elements ; 0 ;; Virtual pins ; 0 ;; I/O pins ; 33 / 185 ( 17 % ) ;; -- Clock pins ; 1 / 2 ( 50 % ) ;; Global signals ; 1 ;; M4Ks ; 19 / 20 ( 95 % ) ;; Total memory bits ; 71,680 / 92,160 ( 77 % ) ;; Total RAM block bits ; 87,552 / 92,160 ( 95 % ) ;; Global clocks ; 1 / 8 ( 12 % ) ;; Maximum fan-out node ; pll50:Ipll|altpll:altpll_component|_clk0 ;; Maximum fan-out ; 882 ;; Total fan-out ; 13803 ;; Average fan-out ; 3.92 ;+-----------------------------------------+------------------------------------------++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Input Pins ;+---------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ;+---------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+; clk ; 28 ; 1 ; 0 ; 12 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; LVTTL ; Off ; User ;; key1 ; 156 ; 3 ; 35 ; 13 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; LVTTL ; Off ; User ;; key2 ; 158 ; 3 ; 35 ; 13 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; LVTTL ; Off ; User ;; rst ; 159 ; 3 ; 35 ; 13 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; LVTTL ; Off ; User ;; ser_rxd ; 177 ; 3 ; 35 ; 19 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; LVTTL ; Off ; User ;+---------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Output Pins ;+-------------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Output Enable Register ; Power Up High ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Location assigned by ;+-------------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+; lcd_data[0] ; 136 ; 3 ; 35 ; 6 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; LVTTL ; 24mA ; Off ; User ;; lcd_data[1] ; 137 ; 3 ; 35 ; 6 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; LVTTL ; 24mA ; Off ; User ;; lcd_data[2] ; 138 ; 3 ; 35 ; 7 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; LVTTL ; 24mA ; Off ; User ;; lcd_data[3] ; 139 ; 3 ; 35 ; 7 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; LVTTL ; 24mA ; Off ; User ;; lcd_data[4] ; 140 ; 3 ; 35 ; 8 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; LVTTL ; 24mA ; Off ; User ;; lcd_data[5] ; 141 ; 3 ; 35 ; 8 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; LVTTL ; 24mA ; Off ; User ;; lcd_data[6] ; 143 ; 3 ; 35 ; 9 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; LVTTL ; 24mA ; Off ; User ;; lcd_data[7] ; 144 ; 3 ; 35 ; 9 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; LVTTL ; 24mA ; Off ; User ;; lcd_en ; 135 ; 3 ; 35 ; 5 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; LVTTL ; 24mA ; Off ; User ;; lcd_rs ; 133 ; 3 ; 35 ; 4 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; LVTTL ; 24mA ; Off ; User ;; lcd_rw ; 134 ; 3 ; 35 ; 5 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; LVTTL ; 24mA ; Off ; User ;; led1 ; 1 ; 1 ; 0 ; 20 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; LVTTL ; 24mA ; Off ; User ;; led2 ; 2 ; 1 ; 0 ; 20 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; LVTTL ; 24mA ; Off ; User ;; seg7led1[0] ; 169 ; 3 ; 35 ; 17 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; LVTTL ; 24mA ; Off ; User ;; seg7led1[1] ; 166 ; 3 ; 35 ; 16 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; LVTTL ; 24mA ; Off ; User ;; seg7led1[2] ; 161 ; 3 ; 35 ; 14 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; LVTTL ; 24mA ; Off ; User ;; seg7led1[3] ; 160 ; 3 ; 35 ; 14 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; LVTTL ; 24mA ; Off ; User ;; seg7led1[4] ; 164 ; 3 ; 35 ; 15 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; LVTTL ; 24mA ; Off ; User ;; seg7led1[5] ; 168 ; 3 ; 35 ; 17 ; 2 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; LVTTL ; 24mA ; Off ; User ;; seg7led1[6] ; 167 ; 3 ; 35 ; 16 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; LVTTL ; 24mA ; Off ; User ;; seg7led2[0] ; 175 ; 3 ; 35 ; 18 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; LVTTL ; 24mA ; Off ; User ;; seg7led2[1] ; 170 ; 3 ; 35 ; 17 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; LVTTL ; 24mA ; Off ; User ;; seg7led2[2] ; 163 ; 3 ; 35 ; 15 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; LVTTL ; 24mA ; Off ; User ;; seg7led2[3] ; 165 ; 3 ; 35 ; 16 ; 2 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; LVTTL ; 24mA ; Off ; User ;; seg7led2[4] ; 162 ; 3 ; 35 ; 15 ; 2 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; LVTTL ; 24mA ; Off ; User ;; seg7led2[5] ; 174 ; 3 ; 35 ; 18 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; LVTTL ; 24mA ; Off ; User ;; seg7led2[6] ; 173 ; 3 ; 35 ; 18 ; 2 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; LVTTL ; 24mA ; Off ; User ;; ser_txd ; 176 ; 3 ; 35 ; 19 ; 2 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; LVTTL ; 24mA ; Off ; User ;+-------------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------++------------------------------------------------------------+; I/O Bank Usage ;+----------+------------------+---------------+--------------+; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ;+----------+------------------+---------------+--------------+; 1 ; 5 / 44 ( 11 % ) ; 3.3V ; -- ;; 2 ; 0 / 48 ( 0 % ) ; 3.3V ; -- ;; 3 ; 30 / 45 ( 66 % ) ; 3.3V ; -- ;; 4 ; 0 / 48 ( 0 % ) ; 3.3V ; -- ;+----------+------------------+---------------+--------------++--------------------------------------------------------------------------------------------------------------------+; All Package Pins ;+----------+------------+----------+----------------+--------+--------------+---------+------------+-----------------+; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ;+----------+------------+----------+----------------+--------+--------------+---------+------------+-----------------+; 1 ; 0 ; 1 ; led1 ; output ; LVTTL ; ; Row I/O ; Y ;; 2 ; 1 ; 1 ; led2 ; output ; LVTTL ; ; Row I/O ; Y ;; 3 ; 2 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ;; 4 ; 3 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ;; 5 ; 4 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ;; 6 ; 5 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ;; 7 ; 6 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ;; 8 ; 7 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ;; 9 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ;; 10 ; ; ; GND ; gnd ; ; ; -- ; ;; 11 ; 8 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ;; 12 ; 9 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ;; 13 ; 10 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ;; 14 ; 11 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ;; 15 ; 12 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ;; 16 ; 13 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ;; 17 ; 14 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ;; 18 ; 15 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ;; 19 ; 16 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ;; 20 ; 17 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ;; 21 ; 18 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ;; 22 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ;; 23 ; 19 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ;; 24 ; 20 ; 1 ; *~nCSO~ / GND* ; output ; LVTTL ; ; Row I/O ; N ;; 25 ; 21 ; 1 ; ^DATA0 ; input ; ; ; -- ; ;; 26 ; 22 ; 1 ; ^nCONFIG ; ; ; ; -- ; ;; 27 ; ; ; VCCA_PLL1 ; power ; ; 1.5V ; -- ; ;; 28 ; 23 ; 1 ; clk ; input ; LVTTL ; ; Row I/O ; Y ;; 29 ; 24 ; 1 ; GND+ ; ; ; ; Row I/O ; ;; 30 ; ; ; GNDA_PLL1 ; gnd ; ; ; -- ; ;; 31 ; ; ; GNDG_PLL1 ; gnd ; ; ; -- ; ;; 32 ; 25 ; 1 ; ^nCEO ; ; ; ; -- ; ;; 33 ; 26 ; 1 ; ^nCE ; ; ; ; -- ; ;; 34 ; 27 ; 1 ; ^MSEL0 ; ; ; ; -- ; ;; 35 ; 28 ; 1 ; ^MSEL1 ; ; ; ; -- ; ;; 36 ; 29 ; 1 ; ^DCLK ; bidir ; ; ; -- ; ;; 37 ; 30 ; 1 ; *~ASDO~ / GND* ; output ; LVTTL ; ; Row I/O ; N ;; 38 ; 31 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ;; 39 ; 32 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ;; 40 ; ; ; GND ; gnd ; ; ; -- ; ;; 41 ; 33 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ;; 42 ; 34 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ;; 43 ; 35 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ;; 44 ; 36 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ;; 45 ; 37 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ;; 46 ; 38 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ;; 47 ; 39 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ;; 48 ; 40 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ;; 49 ; 41 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ;; 50 ; 42 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ;; 51 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ;; 52 ; ; ; GND ; gnd ; ; ; -- ; ;; 53 ; 43 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ;; 54 ; 44 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ;; 55 ; 45 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ;; 56 ; 46 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ;; 57 ; 47 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ;; 58 ; 48 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ;; 59 ; 49 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ;; 60 ; 50 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ;; 61 ; 51 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;; 62 ; 52 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;; 63 ; 53 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;; 64 ; 54 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;; 65 ; 55 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;; 66 ; 56 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;; 67 ; 57 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;; 68 ; 58 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;; 69 ; ; ; GND ; gnd ; ; ; -- ; ;; 70 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ;; 71 ; ; ; GND ; gnd ; ; ; -- ; ;; 72 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; ;; 73 ; 59 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;; 74 ; 60 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;; 75 ; 61 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;; 76 ; 62 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;; 77 ; 63 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;; 78 ; 64 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;; 79 ; 65 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;; 80 ; 66 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;; 81 ; 67 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;; 82 ; 68 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;; 83 ; 69 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;; 84 ; 70 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;; 85 ; 71 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;; 86 ; 72 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;; 87 ; 73 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;; 88 ; 74 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;; 89 ; ; ; GND ; gnd ; ; ; -- ; ;; 90 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; ;; 91 ; ; ; GND ; gnd ; ; ; -- ; ;; 92 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ;; 93 ; 75 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;; 94 ; 76 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;; 95 ; 77 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;; 96 ; 78 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;; 97 ; 79 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;; 98 ; 80 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;; 99 ; 81 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;; 100 ; 82 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;; 101 ; 83 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;; 102 ; 84 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;; 103 ; 85 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;; 104 ; 86 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;; 105 ; 87 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;; 106 ; 88 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;; 107 ; 89 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;; 108 ; 90 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;; 109 ; ; ; GND ; gnd ; ; ; -- ; ;; 110 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; ;; 111 ; ; ; GND ; gnd ; ; ; -- ; ;; 112 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ;; 113 ; 91 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;; 114 ; 92 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;; 115 ; 93 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;; 116 ; 94 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;; 117 ; 95 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;; 118 ; 96 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;; 119 ; 97 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;; 120 ; 98 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;; 121 ; 99 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ;; 122 ; 100 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ;; 123 ; 101 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ;; 124 ; 102 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ;; 125 ; 103 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ;; 126 ; 104 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ;; 127 ; 105 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ;; 128 ; 106 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ;; 129 ; ; ; GND ; gnd ; ; ; -- ; ;; 130 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ;; 131 ; 107 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ;; 132 ; 108 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ;; 133 ; 109 ; 3 ; lcd_rs ; output ; LVTTL ; ; Row I/O ; Y ;; 134 ; 110 ; 3 ; lcd_rw ; output ; LVTTL ; ; Row I/O ; Y ;; 135 ; 111 ; 3 ; lcd_en ; output ; LVTTL ; ; Row I/O ; Y ;; 136 ; 112 ; 3 ; lcd_data[0] ; output ; LVTTL ; ; Row I/O ; Y ;; 137 ; 113 ; 3 ; lcd_data[1] ; output ; LVTTL ; ; Row I/O ; Y ;; 138 ; 114 ; 3 ; lcd_data[2] ; output ; LVTTL ; ; Row I/O ; Y ;; 139 ; 115 ; 3 ; lcd_data[3] ; output ; LVTTL ; ; Row I/O ; Y ;; 140 ; 116 ; 3 ; lcd_data[4] ; output ; LVTTL ; ; Row I/O ; Y ;; 141 ; 117 ; 3 ; lcd_data[5] ; output ; LVTTL ; ; Row I/O ; Y ;; 142 ; ; ; GND ; gnd ; ; ; -- ; ;; 143 ; 118 ; 3 ; lcd_data[6] ; output ; LVTTL ; ; Row I/O ; Y ;; 144 ; 119 ; 3 ; lcd_data[7] ; output ; LVTTL ; ; Row I/O ; Y ;; 145 ; 120 ; 3 ; ^CONF_DONE ; ; ; ; -- ; ;; 146 ; 121 ; 3 ; ^nSTATUS ; ; ; ; -- ; ;; 147 ; 122 ; 3 ; #TCK ; input ; ; ; -- ; ;; 148 ; 123 ; 3 ; #TMS ; input ; ; ; -- ; ;; 149 ; 124 ; 3 ; #TDO ; output ; ; ; -- ; ;; 150 ; ; ; GNDG_PLL2 ; gnd ; ; ; -- ; ;; 151 ; ; ; GNDA_PLL2 ; gnd ; ; ; -- ; ;; 152 ; 125 ; 3 ; GND+ ; ; ; ; Row I/O ; ;; 153 ; 126 ; 3 ; GND+ ; ; ; ; Row I/O ; ;; 154 ; ; ; VCCA_PLL2 ; power ; ; 1.5V ; -- ; ;; 155 ; 127 ; 3 ; #TDI ; input ; ; ; -- ; ;; 156 ; 128 ; 3 ; key1 ; input ; LVTTL ; ; Row I/O ; Y ;; 157 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ;; 158 ; 129 ; 3 ; key2 ; input ; LVTTL ; ; Row I/O ; Y ;; 159 ; 130 ; 3 ; rst ; input ; LVTTL ; ; Row I/O ; Y ;; 160 ; 131 ; 3 ; seg7led1[3] ; output ; LVTTL ; ; Row I/O ; Y ;; 161 ; 132 ; 3 ; seg7led1[2] ; output ; LVTTL ; ; Row I/O ; Y ;; 162 ; 133 ; 3 ; seg7led2[4] ; output ; LVTTL ; ; Row I/O ; Y ;; 163 ; 134 ; 3 ; seg7led2[2] ; output ; LVTTL ; ; Row I/O ; Y ;; 164 ; 135 ; 3 ; seg7led1[4] ; output ; LVTTL ; ; Row I/O ; Y ;; 165 ; 136 ; 3 ; seg7led2[3] ; output ; LVTTL ; ; Row I/O ; Y ;; 166 ; 137 ; 3 ; seg7led1[1] ; output ; LVTTL ; ; Row I/O ; Y ;; 167 ; 138 ; 3 ; seg7led1[6] ; output ; LVTTL ; ; Row I/O ; Y ;; 168 ; 139 ; 3 ; seg7led1[5] ; output ; LVTTL ; ; Row I/O ; Y ;; 169 ; 140 ; 3 ; seg7led1[0] ; output ; LVTTL ; ; Row I/O ; Y ;; 170 ; 141 ; 3 ; seg7led2[1] ; output ; LVTTL ; ; Row I/O ; Y ;; 171 ; ; ; GND ; gnd ; ; ; -- ; ;; 172 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ;; 173 ; 142 ; 3 ; seg7led2[6] ; output ; LVTTL ; ; Row I/O ; Y ;; 174 ; 143 ; 3 ; seg7led2[5] ; output ; LVTTL ; ; Row I/O ; Y ;; 175 ; 144 ; 3 ; seg7led2[0] ; output ; LVTTL ; ; Row I/O ; Y ;; 176 ; 145 ; 3 ; ser_txd ; output ; LVTTL ; ; Row I/O ; Y ;; 177 ; 146 ; 3 ; ser_rxd ; input ; LVTTL ; ; Row I/O ; Y ;; 178 ; 147 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ;; 179 ; 148 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ;; 180 ; 149 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ;; 181 ; 150 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;; 182 ; 151 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;; 183 ; 152 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;; 184 ; 153 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;; 185 ; 154 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;; 186 ; 155 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;; 187 ; 156 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;; 188 ; 157 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;; 189 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ;; 190 ; ; ; GND ; gnd ; ; ; -- ; ;; 191 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; ;; 192 ; ; ; GND ; gnd ; ; ; -- ; ;; 193 ; 158 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;; 194 ; 159 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;; 195 ; 160 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;; 196 ; 161 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;; 197 ; 162 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;; 198 ; 163 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;; 199 ; 164 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;; 200 ; 165 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;; 201 ; 166 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;; 202 ; 167 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;; 203 ; 168 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;; 204 ; 169 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;; 205 ; 170 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;; 206 ; 171 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;; 207 ; 172 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;; 208 ; 173 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;; 209 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ;; 210 ; ; ; GND ; gnd ; ; ; -- ; ;; 211 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; ;; 212 ; ; ; GND ; gnd ; ; ; -- ; ;; 213 ; 174 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;; 214 ; 175 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;; 215 ; 176 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;; 216 ; 177 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;; 217 ; 178 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;; 218 ; 179 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;; 219 ; 180 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;; 220 ; 181 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;; 221 ; 182 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;; 222 ; 183 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;; 223 ; 184 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;; 224 ; 185 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;; 225 ; 186 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;; 226 ; 187 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;; 227 ; 188 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;; 228 ; 189 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;; 229 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; ;; 230 ; ; ; GND ; gnd ; ; ; -- ; ;; 231 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ;; 232 ; ; ; GND ; gnd ; ; ; -- ; ;; 233 ; 190 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;; 234 ; 191 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;; 235 ; 192 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;; 236 ; 193 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;; 237 ; 194 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;; 238 ; 195 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;; 239 ; 196 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;; 240 ; 197 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;+----------+------------+----------+----------------+--------+--------------+---------+------------+-----------------++----------------------------------------------------------------------+; PLL Summary ;+-----------------------------+----------------------------------------+; Name ; pll50:Ipll|altpll:altpll_component|pll ;+-----------------------------+----------------------------------------+; PLL type ; - ;; Scan chain ; None ;; PLL mode ; Normal ;; Feedback source ; -- ;; Compensate clock ; clock0 ;; Switchover on loss of clock ; -- ;; Switchover counter ; -- ;; Primary clock ; -- ;; Input frequency 0 ; 25.0 MHz ;; Input frequency 1 ; -- ;; Nominal VCO frequency ; 800.0 MHz ;; Freq min lock ; 15.34 MHz ;; Freq max lock ; 31.25 MHz ;; Clock Offset ; 0 ps ;; M VCO Tap ; 0 ;; M Initial ; 1 ;; M value ; 32 ;; N value ; 1 ;; M counter delay ; -- ;; N counter delay ; -- ;; M2 value ; -- ;; N2 value ; -- ;; SS counter ; -- ;; Downspread ; -- ;; Spread frequency ; -- ;; Charge pump current ; -- ;; Loop filter resistance ; -- ;; Loop filter capacitance ; -- ;; Freq zero ; -- ;; Bandwidth ; -- ;; Freq pole ; -- ;; enable0 counter ; -- ;; enable1 counter ; -- ;; Real time reconfigurable ; -- ;; Scan chain MIF file ; -- ;; Preserve counter order ; Off ;; PLL location ; PLL_1 ;; Inclk0 signal ; clk ;; Inclk1 signal ; -- ;+-----------------------------+----------------------------------------++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; PLL Usage ;+------------------------------------------+--------------+------+-----+------------------+-------------+-------+------------+---------+---------------+---------------+------------+---------+---------+; Name ; Output Clock ; Mult ; Div ; Output Frequency ; Phase Shift ; Delay ; Duty Cycle ; Counter ; Counter Delay ; Counter Value ; High / Low ; Initial ; VCO Tap ;+------------------------------------------+--------------+------+-----+------------------+-------------+-------+------------+---------+---------------+---------------+------------+---------+---------+; pll50:Ipll|altpll:altpll_component|_clk0 ; clock0 ; 2 ; 1 ; 50.0 MHz ; 0 (0 ps) ; 0 ps ; 50/50 ; G1 ; -- ; 16 ; 8/8 Even ; 1 ; 0 ;+------------------------------------------+--------------+------+-----+------------------+-------------+-------+------------+---------+---------------+---------------+------------+---------+---------++------------------------------------------------------------------+; Output Pin Default Load For Reported TCO ;+---------------------+-------+------------------------------------+; I/O Standard ; Load ; Termination Resistance ;+---------------------+-------+------------------------------------+; LVTTL ; 10 pF ; Not Available ;; LVCMOS ; 10 pF ; Not Available ;; 2.5 V ; 10 pF ; Not Available ;; 1.8 V ; 10 pF ; Not Available ;; 1.5 V ; 10 pF ; Not Available ;; SSTL-3 Class I ; 30 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ;; SSTL-3 Class II ; 30 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ;; SSTL-2 Class I ; 30 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ;; SSTL-2 Class II ; 30 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ;; Differential SSTL-2 ; 30 pF ; (See SSTL-2) ;; 3.3-V PCI ; 10 pF ; 25 Ohm (Parallel) ;; LVDS ; 4 pF ; 100 Ohm (Differential) ;; RSDS ; 0 pF ; 100 Ohm (Differential) ;+---------------------+-------+------------------------------------++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Fitter Resource Utilization by Entity ;+----------------------------------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name ;+----------------------------------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; |mips_top ; 3468 (3) ; 863 ; 71680 ; 33 ; 0 ; 2605 (1) ; 107 (1) ; 756 (1) ; 460 (0) ; |mips_top ;; |mem_array:ram_8k| ; 0 (0) ; 0 ; 65536 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mem_array:ram_8k ;; |ram2048x8_0:ram0| ; 0 (0) ; 0 ; 16384 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mem_array:ram_8k|ram2048x8_0:ram0 ;; |altsyncram:altsyncram_component| ; 0 (0) ; 0 ; 16384 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mem_array:ram_8k|ram2048x8_0:ram0|altsyncram:altsyncram_component ;; |altsyncram_eht1:auto_generated| ; 0 (0) ; 0 ; 16384 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mem_array:ram_8k|ram2048x8_0:ram0|altsyncram:altsyncram_component|altsyncram_eht1:auto_generated ;; |ram2048x8_1:ram1| ; 0 (0) ; 0 ; 16384 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mem_array:ram_8k|ram2048x8_1:ram1 ;; |altsyncram:altsyncram_component| ; 0 (0) ; 0 ; 16384 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mem_array:ram_8k|ram2048x8_1:ram1|altsyncram:altsyncram_component ;; |altsyncram_fht1:auto_generated| ; 0 (0) ; 0 ; 16384 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mem_array:ram_8k|ram2048x8_1:ram1|altsyncram:altsyncram_component|altsyncram_fht1:auto_generated ;; |ram2048x8_2:ram2| ; 0 (0) ; 0 ; 16384 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mem_array:ram_8k|ram2048x8_2:ram2 ;; |altsyncram:altsyncram_component| ; 0 (0) ; 0 ; 16384 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mem_array:ram_8k|ram2048x8_2:ram2|altsyncram:altsyncram_component ;; |altsyncram_ght1:auto_generated| ; 0 (0) ; 0 ; 16384 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mem_array:ram_8k|ram2048x8_2:ram2|altsyncram:altsyncram_component|altsyncram_ght1:auto_generated ;; |ram2048x8_3:ram3| ; 0 (0) ; 0 ; 16384 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mem_array:ram_8k|ram2048x8_3:ram3 ;; |altsyncram:altsyncram_component| ; 0 (0) ; 0 ; 16384 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mem_array:ram_8k|ram2048x8_3:ram3|altsyncram:altsyncram_component ;; |altsyncram_hht1:auto_generated| ; 0 (0) ; 0 ; 16384 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mem_array:ram_8k|ram2048x8_3:ram3|altsyncram:altsyncram_component|altsyncram_hht1:auto_generated ;; |mips_sys:isys| ; 3465 (44) ; 861 ; 6144 ; 31 ; 0 ; 2604 (44) ; 106 (0) ; 755 (0) ; 460 (0) ; |mips_top|mips_sys:isys ;; |mips_core:mips_core| ; 3085 (31) ; 604 ; 2048 ; 0 ; 0 ; 2481 (31) ; 55 (0) ; 549 (0) ; 363 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core ;; |decode_pipe:decoder_pipe| ; 251 (0) ; 52 ; 0 ; 0 ; 0 ; 199 (0) ; 6 (0) ; 46 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe ;; |decoder:idecoder| ; 199 (184) ; 0 ; 0 ; 0 ; 0 ; 199 (184) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder ;; |SYNLPM_LATR1:cmp_ctl_1_0_| ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:cmp_ctl_1_0_ ;; |lpm_latch:U1| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:cmp_ctl_1_0_|lpm_latch:U1 ;; |SYNLPM_LATR1:fsm_dly_1_0_| ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:fsm_dly_1_0_ ;; |lpm_latch:U1| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:fsm_dly_1_0_|lpm_latch:U1 ;; |SYNLPM_LATR1:fsm_dly_1_1__Z| ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:fsm_dly_1_1__Z ;; |lpm_latch:U1| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:fsm_dly_1_1__Z|lpm_latch:U1 ;; |SYNLPM_LATR1:fsm_dly_1_2__Z| ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:fsm_dly_1_2__Z ;; |lpm_latch:U1| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:fsm_dly_1_2__Z|lpm_latch:U1 ;; |SYNLPM_LATRS1:alu_func_1_2_| ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:alu_func_1_2_ ;; |lpm_latch:U1| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:alu_func_1_2_|lpm_latch:U1 ;; |SYNLPM_LATRS1:alu_func_1_3_| ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:alu_func_1_3_ ;; |lpm_latch:U1| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:alu_func_1_3_|lpm_latch:U1 ;; |SYNLPM_LATRS1:dmem_ctl_1_0_| ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:dmem_ctl_1_0_ ;; |lpm_latch:U1| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:dmem_ctl_1_0_|lpm_latch:U1 ;; |SYNLPM_LATRS1:dmem_ctl_1_1_| ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:dmem_ctl_1_1_ ;; |lpm_latch:U1| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:dmem_ctl_1_1_|lpm_latch:U1 ;; |SYNLPM_LATRS1:dmem_ctl_1_2_| ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:dmem_ctl_1_2_ ;; |lpm_latch:U1| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:dmem_ctl_1_2_|lpm_latch:U1 ;; |SYNLPM_LATRS1:ext_ctl_1_0_| ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:ext_ctl_1_0_ ;; |lpm_latch:U1| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:ext_ctl_1_0_|lpm_latch:U1 ;; |SYNLPM_LATRS1:muxa_ctl_1_1_| ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:muxa_ctl_1_1_ ;; |lpm_latch:U1| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:muxa_ctl_1_1_|lpm_latch:U1 ;; |SYNLPM_LATRS1:muxb_ctl_1_1_| ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:muxb_ctl_1_1_ ;; |lpm_latch:U1| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:muxb_ctl_1_1_|lpm_latch:U1 ;; |SYNLPM_LATRS1:pc_gen_ctl_1_0_| ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:pc_gen_ctl_1_0_ ;; |lpm_latch:U1| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:pc_gen_ctl_1_0_|lpm_latch:U1 ;; |SYNLPM_LATRS1:pc_gen_ctl_1_2_| ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:pc_gen_ctl_1_2_ ;; |lpm_latch:U1| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:pc_gen_ctl_1_2_|lpm_latch:U1 ;; |SYNLPM_LATRS1:rd_sel_1_1_| ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:rd_sel_1_1_ ;; |lpm_latch:U1| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:rd_sel_1_1_|lpm_latch:U1 ;; |pipelinedregs:pipereg| ; 52 (0) ; 52 ; 0 ; 0 ; 0 ; 0 (0) ; 6 (0) ; 46 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg ;; |alu_func_reg_clr:U16| ; 5 (5) ; 5 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 5 (5) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|alu_func_reg_clr:U16 ;; |alu_func_reg_clr_cls:U26| ; 5 (5) ; 5 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 5 (5) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|alu_func_reg_clr_cls:U26 ;; |alu_we_reg_clr:U24| ; 1 (1) ; 1 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (1) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|alu_we_reg_clr:U24 ;; |alu_we_reg_clr_cls:U6| ; 1 (1) ; 1 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 1 (1) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|alu_we_reg_clr_cls:U6 ;; |cmp_ctl_reg_clr_cls:U2| ; 3 (3) ; 3 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 3 (3) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|cmp_ctl_reg_clr_cls:U2 ;; |dmem_ctl_reg:U9| ; 4 (4) ; 4 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 4 (4) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|dmem_ctl_reg:U9 ;; |dmem_ctl_reg_clr:U15| ; 4 (4) ; 4 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 4 (4) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|dmem_ctl_reg_clr:U15 ;; |dmem_ctl_reg_clr_cls:U3| ; 4 (4) ; 4 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 4 (4) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|dmem_ctl_reg_clr_cls:U3 ;; |ext_ctl_reg_clr_cls:U4| ; 3 (3) ; 3 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 3 (3) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|ext_ctl_reg_clr_cls:U4 ;; |muxa_ctl_reg_clr:U17| ; 2 (2) ; 2 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 2 (2) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|muxa_ctl_reg_clr:U17 ;; |muxa_ctl_reg_clr_cls:U7| ; 2 (2) ; 2 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 2 (2) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|muxa_ctl_reg_clr_cls:U7 ;; |muxb_ctl_reg_clr:U14| ; 2 (2) ; 2 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 2 (2) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|muxb_ctl_reg_clr:U14 ;; |muxb_ctl_reg_clr_cls:U1| ; 2 (2) ; 2 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 2 (2) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|muxb_ctl_reg_clr_cls:U1 ;; |pc_gen_ctl_reg_clr_cls:U8| ; 3 (3) ; 3 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 3 (3) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|pc_gen_ctl_reg_clr_cls:U8 ;; |rd_sel_reg_clr_cls:U5| ; 2 (2) ; 2 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 2 (2) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|rd_sel_reg_clr_cls:U5 ;; |wb_mux_ctl_reg:U18| ; 1 (1) ; 1 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (1) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|wb_mux_ctl_reg:U18 ;; |wb_mux_ctl_reg_1:U21| ; 1 (1) ; 1 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (1) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|wb_mux_ctl_reg_1:U21 ;; |wb_mux_ctl_reg_clr:U13| ; 1 (1) ; 1 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (1) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|wb_mux_ctl_reg_clr:U13 ;; |wb_mux_ctl_reg_clr_cls:U10| ; 1 (1) ; 1 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 1 (1) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|wb_mux_ctl_reg_clr_cls:U10 ;; |wb_we_reg:U12| ; 1 (1) ; 1 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 1 (1) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|wb_we_reg:U12 ;; |wb_we_reg_1:U20| ; 1 (1) ; 1 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (1) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|wb_we_reg_1:U20 ;; |wb_we_reg_2:U22| ; 1 (1) ; 1 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 1 (1) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|wb_we_reg_2:U22 ;; |wb_we_reg_clr:U19| ; 1 (1) ; 1 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (1) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|wb_we_reg_clr:U19 ;; |wb_we_reg_clr_cls:U11| ; 1 (1) ; 1 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 1 (1) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|wb_we_reg_clr_cls:U11 ;; |exec_stage:iexec_stage| ; 1941 (1) ; 179 ; 0 ; 0 ; 0 ; 1762 (1) ; 2 (0) ; 177 (0) ; 331 (1) ; |mips_top|mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage ;; |alu_muxa:i_alu_muxa| ; 128 (128) ; 0 ; 0 ; 0 ; 0 ; 128 (128) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa ;; |alu_muxb:i_alu_muxb| ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 4 (4) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxb:i_alu_muxb ;; |big_alu:MIPS_alu| ; 1711 (95) ; 115 ; 0 ; 0 ; 0 ; 1596 (95) ; 1 (0) ; 114 (0) ; 301 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu ;; |alu:mips_alu| ; 240 (240) ; 0 ; 0 ; 0 ; 0 ; 240 (240) ; 0 (0) ; 0 (0) ; 98 (98) ; |mips_top|mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu ;; |muldiv_ff:muldiv_ff| ; 769 (769) ; 115 ; 0 ; 0 ; 0 ; 654 (654) ; 1 (1) ; 114 (114) ; 203 (203) ; |mips_top|mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff ;; |shifter_tak:mips_shifter| ; 607 (607) ; 0 ; 0 ; 0 ; 0 ; 607 (607) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter ;; |fwd_mux_2:dmem_fw_mux| ; 33 (33) ; 0 ; 0 ; 0 ; 0 ; 33 (33) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|fwd_mux_2:dmem_fw_mux ;; |r32_reg:pc_nxt| ; 32 (32) ; 32 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (1) ; 31 (31) ; 29 (29) ; |mips_top|mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt ;; |r32_reg_cls:spc| ; 32 (32) ; 32 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 32 (32) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg_cls:spc ;; |forward:iforward| ; 16 (0) ; 10 ; 0 ; 0 ; 0 ; 6 (0) ; 1 (0) ; 9 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|forward:iforward ;; |forward_node_fw_alu_rs:fw_alu_rs| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|forward:iforward|forward_node_fw_alu_rs:fw_alu_rs ;; |forward_node_fw_alu_rs_1:fw_alu_rt| ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|forward:iforward|forward_node_fw_alu_rs_1:fw_alu_rt ;; |forward_node_fw_alu_rs_3:fw_cmp_rt| ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|forward:iforward|forward_node_fw_alu_rs_3:fw_cmp_rt ;; |fw_latch5:fw_reg_rns| ; 5 (5) ; 5 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 5 (5) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|forward:iforward|fw_latch5:fw_reg_rns ;; |fw_latch5_1:fw_reg_rnt| ; 5 (5) ; 5 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (1) ; 4 (4) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|forward:iforward|fw_latch5_1:fw_reg_rnt ;; |mem_module:MEM_CTL| ; 140 (0) ; 6 ; 0 ; 0 ; 0 ; 134 (0) ; 0 (0) ; 6 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL ;; |infile_dmem_ctl_reg:dmem_ctl_post| ; 6 (6) ; 6 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 6 (6) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|infile_dmem_ctl_reg:dmem_ctl_post ;; |mem_addr_ctl:i_mem_addr_ctl| ; 11 (3) ; 0 ; 0 ; 0 ; 0 ; 11 (3) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_addr_ctl:i_mem_addr_ctl ;; |SYNLPM_LATRS1:wr_en_1_0_| ; 2 (0) ; 0 ; 0 ; 0 ; 0 ; 2 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_addr_ctl:i_mem_addr_ctl|SYNLPM_LATRS1:wr_en_1_0_ ;; |lpm_latch:U1| ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_addr_ctl:i_mem_addr_ctl|SYNLPM_LATRS1:wr_en_1_0_|lpm_latch:U1 ;; |SYNLPM_LATRS1:wr_en_1_1_| ; 2 (0) ; 0 ; 0 ; 0 ; 0 ; 2 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_addr_ctl:i_mem_addr_ctl|SYNLPM_LATRS1:wr_en_1_1_ ;; |lpm_latch:U1| ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_addr_ctl:i_mem_addr_ctl|SYNLPM_LATRS1:wr_en_1_1_|lpm_latch:U1 ;; |SYNLPM_LATRS1:wr_en_1_2_| ; 2 (0) ; 0 ; 0 ; 0 ; 0 ; 2 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_addr_ctl:i_mem_addr_ctl|SYNLPM_LATRS1:wr_en_1_2_ ;; |lpm_latch:U1| ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_addr_ctl:i_mem_addr_ctl|SYNLPM_LATRS1:wr_en_1_2_|lpm_latch:U1 ;; |SYNLPM_LATRS1:wr_en_1_3_| ; 2 (0) ; 0 ; 0 ; 0 ; 0 ; 2 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_addr_ctl:i_mem_addr_ctl|SYNLPM_LATRS1:wr_en_1_3_ ;; |lpm_latch:U1| ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_addr_ctl:i_mem_addr_ctl|SYNLPM_LATRS1:wr_en_1_3_|lpm_latch:U1 ;; |mem_din_ctl:i_mem_din_ctl| ; 33 (33) ; 0 ; 0 ; 0 ; 0 ; 33 (33) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_din_ctl:i_mem_din_ctl ;; |mem_dout_ctl:i_mem_dout_ctl| ; 90 (90) ; 0 ; 0 ; 0 ; 0 ; 90 (90) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl ;; |r32_reg_1:alu_pass0| ; 30 (30) ; 30 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 30 (30) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|r32_reg_1:alu_pass0 ;; |r32_reg_2:alu_pass1| ; 32 (32) ; 32 ; 0 ; 0 ; 0 ; 0 (0) ; 32 (32) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|r32_reg_2:alu_pass1 ;; |r32_reg_3:cop_data_reg| ; 32 (32) ; 32 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 32 (32) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg ;; |r32_reg_4:cop_dout_reg| ; 32 (32) ; 32 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 32 (32) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|r32_reg_4:cop_dout_reg ;; |r32_reg_5:ext_reg| ; 32 (32) ; 32 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 32 (32) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg ;; |r32_reg_6:pc| ; 32 (32) ; 32 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 32 (32) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|r32_reg_6:pc ;; |r32_reg_7:rs_reg| ; 32 (32) ; 32 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 32 (32) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg ;; |r32_reg_8:rt_reg| ; 32 (32) ; 32 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 32 (32) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg ;; |r5_reg:rnd_pass0| ; 5 (5) ; 5 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 5 (5) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|r5_reg:rnd_pass0 ;; |r5_reg_1:rnd_pass1| ; 5 (5) ; 5 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 5 (5) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|r5_reg_1:rnd_pass1 ;; |r5_reg_2:rnd_pass2| ; 5 (5) ; 5 ; 0 ; 0 ; 0 ; 0 (0) ; 2 (2) ; 3 (3) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|r5_reg_2:rnd_pass2 ;; |rf_stage:iRF_stage| ; 437 (0) ; 88 ; 2048 ; 0 ; 0 ; 349 (0) ; 12 (0) ; 76 (0) ; 32 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage ;; |compare:i_cmp| ; 36 (36) ; 0 ; 0 ; 0 ; 0 ; 36 (36) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|compare:i_cmp ;; |ctl_FSM:MIAN_FSM| ; 35 (33) ; 14 ; 0 ; 0 ; 0 ; 21 (19) ; 1 (1) ; 13 (13) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM ;; |SYNLPM_LATR1:next_delay_counter_Sreg0_3__Z| ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|SYNLPM_LATR1:next_delay_counter_Sreg0_3__Z ;; |lpm_latch:U1| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|SYNLPM_LATR1:next_delay_counter_Sreg0_3__Z|lpm_latch:U1 ;; |SYNLPM_LATS1:next_delay_counter_Sreg0_5_| ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|SYNLPM_LATS1:next_delay_counter_Sreg0_5_ ;; |lpm_latch:U1| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|SYNLPM_LATS1:next_delay_counter_Sreg0_5_|lpm_latch:U1 ;; |ext:i_ext| ; 16 (16) ; 0 ; 0 ; 0 ; 0 ; 16 (16) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ext:i_ext ;; |fwd_mux:rf_fwd_rt| ; 65 (65) ; 0 ; 0 ; 0 ; 0 ; 65 (65) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt ;; |fwd_mux_1:rs_fwd_rs| ; 64 (64) ; 0 ; 0 ; 0 ; 0 ; 64 (64) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs ;; |pc_gen:i_pc_gen| ; 133 (133) ; 0 ; 0 ; 0 ; 0 ; 133 (133) ; 0 (0) ; 0 (0) ; 32 (32) ; |mips_top|mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen ;; |r32_reg_clr_cls:ins_reg| ; 26 (26) ; 26 ; 0 ; 0 ; 0 ; 0 (0) ; 8 (8) ; 18 (18) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|r32_reg_clr_cls:ins_reg ;; |reg_array:reg_bank_cZ| ; 62 (62) ; 48 ; 2048 ; 0 ; 0 ; 14 (14) ; 3 (3) ; 45 (45) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ ;; |altsyncram:reg_bank_1_I_1_Z| ; 0 (0) ; 0 ; 1024 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_1_I_1_Z ;; |altsyncram_3mc1:auto_generated| ; 0 (0) ; 0 ; 1024 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_1_I_1_Z|altsyncram_3mc1:auto_generated ;; |altsyncram:reg_bank_I_1_Z| ; 0 (0) ; 0 ; 1024 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_I_1_Z ;; |altsyncram_3mc1:auto_generated| ; 0 (0) ; 0 ; 1024 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_I_1_Z|altsyncram_3mc1:auto_generated ;; |mips_dvc:imips_dvc| ; 336 (108) ; 257 ; 4096 ; 0 ; 0 ; 79 (24) ; 51 (36) ; 206 (48) ; 97 (0) ; |mips_top|mips_sys:isys|mips_dvc:imips_dvc ;; |seg7led_cv:iseg7_cv| ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; 6 (6) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_dvc:imips_dvc|seg7led_cv:iseg7_cv ;; |tmr0:mips_tmr0| ; 75 (75) ; 64 ; 0 ; 0 ; 0 ; 11 (11) ; 0 (0) ; 64 (64) ; 32 (32) ; |mips_top|mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0 ;; |uart0:iuart0| ; 147 (0) ; 109 ; 4096 ; 0 ; 0 ; 38 (0) ; 15 (0) ; 94 (0) ; 65 (0) ; |mips_top|mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0 ;; |rxd_d:rxd_rdy_hold_lw| ; 1 (1) ; 1 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 1 (1) ; 0 (0) ; |mips_top|mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|rxd_d:rxd_rdy_hold_lw ;; |uart_read:uart_rd_tak| ; 55 (55) ; 42 ; 0 ; 0 ; 0 ; 13 (13) ; 14 (14) ; 28 (28) ; 19 (19) ; |mips_top|mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak ;; |uart_write:uart_txd| ; 91 (53) ; 66 ; 4096 ; 0 ; 0 ; 25 (16) ; 1 (1) ; 65 (36) ; 46 (19) ; |mips_top|mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd ;; |fifo512_cyclone:fifo| ; 38 (0) ; 29 ; 4096 ; 0 ; 0 ; 9 (0) ; 0 (0) ; 29 (0) ; 27 (0) ; |mips_top|mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo ;; |scfifo_Z1:scfifo_component| ; 38 (0) ; 29 ; 4096 ; 0 ; 0 ; 9 (0) ; 0 (0) ; 29 (0) ; 27 (0) ; |mips_top|mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component ;; |scfifo:U1| ; 38 (0) ; 29 ; 4096 ; 0 ; 0 ; 9 (0) ; 0 (0) ; 29 (0) ; 27 (0) ; |mips_top|mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1 ;; |scfifo_e4u:auto_generated| ; 38 (0) ; 29 ; 4096 ; 0 ; 0 ; 9 (0) ; 0 (0) ; 29 (0) ; 27 (0) ; |mips_top|mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated ;; |a_dpfifo_lqr:dpfifo| ; 38 (2) ; 29 ; 4096 ; 0 ; 0 ; 9 (2) ; 0 (0) ; 29 (0) ; 27 (0) ; |mips_top|mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo ;; |a_fefifo_s7f:fifo_state| ; 18 (9) ; 11 ; 0 ; 0 ; 0 ; 7 (7) ; 0 (0) ; 11 (2) ; 9 (0) ; |mips_top|mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|a_fefifo_s7f:fifo_state ;; |cntr_cc7:count_usedw| ; 9 (9) ; 9 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 9 (9) ; 9 (9) ; |mips_top|mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|a_fefifo_s7f:fifo_state|cntr_cc7:count_usedw ;; |cntr_ud8:rd_ptr_count| ; 9 (9) ; 9 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 9 (9) ; 9 (9) ; |mips_top|mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|cntr_ud8:rd_ptr_count ;; |cntr_ud8:wr_ptr| ; 9 (9) ; 9 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 9 (9) ; 9 (9) ; |mips_top|mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|cntr_ud8:wr_ptr ;; |dpram_4cm:FIFOram| ; 0 (0) ; 0 ; 4096 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|dpram_4cm:FIFOram ;; |altsyncram_ihc1:altsyncram1| ; 0 (0) ; 0 ; 4096 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|dpram_4cm:FIFOram|altsyncram_ihc1:altsyncram1 ;; |pll50:Ipll| ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|pll50:Ipll ;; |altpll:altpll_component| ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|pll50:Ipll|altpll:altpll_component ;+----------------------------------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------++--------------------------------------------------------------------------------------+; Delay Chain Summary ;+-------------+----------+---------------+---------------+-----------------------+-----+; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ;+-------------+----------+---------------+---------------+-----------------------+-----+; clk ; Input ; -- ; -- ; -- ; -- ;; rst ; Input ; ON ; ON ; -- ; -- ;; ser_txd ; Output ; -- ; -- ; -- ; -- ;; seg7led1[6] ; Output ; -- ; -- ; -- ; -- ;; seg7led1[5] ; Output ; -- ; -- ; -- ; -- ;; seg7led1[4] ; Output ; -- ; -- ; -- ; -- ;; seg7led1[3] ; Output ; -- ; -- ; -- ; -- ;; seg7led1[2] ; Output ; -- ; -- ; -- ; -- ;; seg7led1[1] ; Output ; -- ; -- ; -- ; -- ;; seg7led1[0] ; Output ; -- ; -- ; -- ; -- ;; seg7led2[6] ; Output ; -- ; -- ; -- ; -- ;; seg7led2[5] ; Output ; -- ; -- ; -- ; -- ;; seg7led2[4] ; Output ; -- ; -- ; -- ; -- ;; seg7led2[3] ; Output ; -- ; -- ; -- ; -- ;; seg7led2[2] ; Output ; -- ; -- ; -- ; -- ;; seg7led2[1] ; Output ; -- ; -- ; -- ; -- ;; seg7led2[0] ; Output ; -- ; -- ; -- ; -- ;; lcd_data[7] ; Output ; -- ; -- ; -- ; -- ;; lcd_data[6] ; Output ; -- ; -- ; -- ; -- ;; lcd_data[5] ; Output ; -- ; -- ; -- ; -- ;; lcd_data[4] ; Output ; -- ; -- ; -- ; -- ;; lcd_data[3] ; Output ; -- ; -- ; -- ; -- ;; lcd_data[2] ; Output ; -- ; -- ; -- ; -- ;; lcd_data[1] ; Output ; -- ; -- ; -- ; -- ;; lcd_data[0] ; Output ; -- ; -- ; -- ; -- ;; lcd_rs ; Output ; -- ; -- ; -- ; -- ;; lcd_rw ; Output ; -- ; -- ; -- ; -- ;; lcd_en ; Output ; -- ; -- ; -- ; -- ;; led1 ; Output ; -- ; -- ; -- ; -- ;; led2 ; Output ; -- ; -- ; -- ; -- ;; key1 ; Input ; ON ; ON ; -- ; -- ;; key2 ; Input ; ON ; ON ; -- ; -- ;; ser_rxd ; Input ; OFF ; ON ; -- ; -- ;+-------------+----------+---------------+---------------+-----------------------+-----++-----------------------------------------------------------------------------------------------------------------+; Pad To Core Delay Chain Fanout ;+-----------------------------------------------------------------------------------+-------------------+---------+; Source Pin / Fanout ; Pad To Core Index ; Setting ;+-----------------------------------------------------------------------------------+-------------------+---------+; clk ; ; ;; rst ; ; ;; - r_rst ; 0 ; ON ;; mips_sys:isys|key1_in ; ; ;; - mips_sys:isys|mips_dvc:imips_dvc|r_key1_Z ; 0 ; ON ;; mips_sys:isys|key2_in ; ; ;; - mips_sys:isys|mips_dvc:imips_dvc|r_key2_Z ; 0 ; ON ;; mips_sys:isys|ser_rxd_in ; ; ;; - mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|rxq1_Z ; 1 ; ON ;+-----------------------------------------------------------------------------------+-------------------+---------++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Control Signals ;+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------+---------+---------------------------+--------+----------------------+------------------+; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ;+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------+---------+---------------------------+--------+----------------------+------------------+; clk ; PIN_28 ; 1 ; Clock ; no ; -- ; -- ;; mips_sys:isys|G_451_x ; LC_X14_Y3_N5 ; 3 ; Clock enable ; no ; -- ; -- ;; mips_sys:isys|G_504 ; LC_X29_Y17_N4 ; 53 ; Clock enable ; no ; -- ; -- ;; mips_sys:isys|G_505 ; LC_X3_Y14_N5 ; 65 ; Clock enable ; no ; -- ; -- ;; mips_sys:isys|G_570_x ; LC_X33_Y5_N9 ; 8 ; Clock enable ; no ; -- ; -- ;; mips_sys:isys|G_578 ; LC_X33_Y16_N7 ; 8 ; Clock enable ; no ; -- ; -- ;; mips_sys:isys|G_586 ; LC_X16_Y2_N7 ; 8 ; Clock enable ; no ; -- ; -- ;; mips_sys:isys|G_594 ; LC_X33_Y9_N5 ; 8 ; Clock enable ; no ; -- ; -- ;; mips_sys:isys|G_602 ; LC_X33_Y9_N4 ; 32 ; Clock enable ; no ; -- ; -- ;; mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|wb_we_reg:U12|wb_we_o_0 ; LC_X27_Y12_N8 ; 10 ; Write enable ; no ; -- ; -- ;; mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|addop2_0_sqmuxa_1_i ; LC_X2_Y15_N9 ; 3 ; Clock enable ; no ; -- ; -- ;; mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|finish_0_sqmuxa_i ; LC_X2_Y15_N7 ; 1 ; Clock enable ; no ; -- ; -- ;; mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_1_sqmuxa_i ; LC_X32_Y9_N0 ; 6 ; Sync. clear ; no ; -- ; -- ;; mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|mul_0_sqmuxa_i ; LC_X9_Y14_N8 ; 3 ; Clock enable ; no ; -- ; -- ;; mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|op1_sign_reged_0_sqmuxa_i ; LC_X8_Y13_N4 ; 34 ; Clock enable ; no ; -- ; -- ;; mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|sub_or_yn_0_sqmuxa_1_i ; LC_X3_Y14_N2 ; 1 ; Clock enable ; no ; -- ; -- ;; mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_addr_ctl:i_mem_addr_ctl|SYNLPM_LATRS1:wr_en_1_0_|lpm_latch:U1|q[0]~95 ; LC_X13_Y9_N4 ; 5 ; Write enable ; no ; -- ; -- ;; mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_addr_ctl:i_mem_addr_ctl|SYNLPM_LATRS1:wr_en_1_1_|lpm_latch:U1|q[0]~95 ; LC_X13_Y9_N5 ; 5 ; Write enable ; no ; -- ; -- ;; mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_addr_ctl:i_mem_addr_ctl|SYNLPM_LATRS1:wr_en_1_2_|lpm_latch:U1|q[0]~85 ; LC_X13_Y9_N9 ; 5 ; Write enable ; no ; -- ; -- ;; mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_addr_ctl:i_mem_addr_ctl|SYNLPM_LATRS1:wr_en_1_3_|lpm_latch:U1|q[0]~85 ; LC_X14_Y9_N1 ; 5 ; Write enable ; no ; -- ; -- ;; mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|CurrState_Sreg0_2 ; LC_X30_Y16_N7 ; 55 ; Clock enable ; no ; -- ; -- ;; mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|NET1640_i ; LC_X27_Y14_N9 ; 16 ; Sync. clear ; no ; -- ; -- ;; mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|id2ra_ins_clr_1_0_i_a2_0_a2 ; LC_X27_Y14_N6 ; 54 ; Sync. clear ; no ; -- ; -- ;; mips_sys:isys|mips_dvc:imips_dvc|cmd[1] ; LC_X34_Y13_N7 ; 1 ; Async. clear ; no ; -- ; -- ;; mips_sys:isys|mips_dvc:imips_dvc|lcd_data_0_sqmuxa_0_a2 ; LC_X33_Y9_N0 ; 8 ; Clock enable ; no ; -- ; -- ;; mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntrlde ; LC_X32_Y6_N0 ; 32 ; Clock enable ; no ; -- ; -- ;; mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|un1_ld_1 ; LC_X31_Y3_N8 ; 33 ; Sync. load ; no ; -- ; -- ;; mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|bit_ctr23_i_i ; LC_X33_Y15_N7 ; 3 ; Sync. clear ; no ; -- ; -- ;; mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|clk_ctr27_i_i ; LC_X33_Y15_N4 ; 16 ; Sync. clear ; no ; -- ; -- ;; mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|int_req ; LC_X33_Y15_N9 ; 1 ; Clock enable ; no ; -- ; -- ;; mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|bit_ctr23_i_i ; LC_X16_Y3_N7 ; 3 ; Sync. clear ; no ; -- ; -- ;; mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|clk_ctr26_i_i ; LC_X15_Y3_N8 ; 16 ; Sync. clear ; no ; -- ; -- ;; mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|a_fefifo_s7f:fifo_state|_~14 ; LC_X22_Y2_N6 ; 9 ; Clock enable ; no ; -- ; -- ;; mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|valid_rreq ; LC_X22_Y2_N9 ; 10 ; Clock enable ; no ; -- ; -- ;; mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|valid_wreq ; LC_X22_Y2_N8 ; 18 ; Write enable ; no ; -- ; -- ;; mips_sys:isys|mips_dvc:imips_dvc|wr_tmr_data_0_a2 ; LC_X33_Y9_N1 ; 33 ; Clock enable ; no ; -- ; -- ;; pll50:Ipll|altpll:altpll_component|_clk0 ; PLL_1 ; 882 ; Clock ; yes ; Global clock ; GCLK3 ;; sys_rst ; LC_X33_Y13_N2 ; 185 ; Clock enable, Sync. clear ; no ; -- ; -- ;+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------+---------+---------------------------+--------+----------------------+------------------++---------------------------------------------------------------------------------------------------------+; Global & Other Fast Signals ;+------------------------------------------+----------+---------+----------------------+------------------+; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ;+------------------------------------------+----------+---------+----------------------+------------------+; pll50:Ipll|altpll:altpll_component|_clk0 ; PLL_1 ; 882 ; Global clock ; GCLK3 ;+------------------------------------------+----------+---------+----------------------+------------------++-----------------------------------------------------------------------------------------------------------------------------------+; Non-Global High Fan-Out Signals ;+-------------------------------------------------------------------------------------------------------------------------+---------+; Name ; Fan-Out ;+-------------------------------------------------------------------------------------------------------------------------+---------+; mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_2 ; 242 ;; mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_1 ; 225 ;; sys_rst ; 186 ;; mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_0 ; 159 ;; mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_2_sqmuxa ; 65 ;; mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_sn_m2 ; 65 ;; mips_sys:isys|G_505 ; 65 ;; mips_sys:isys|mips_dvc:imips_dvc|wr_tmr_data_0_a2 ; 65 ;; mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3 ; 62 ;; mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|b_o_iv_31 ; 58 ;; mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|CurrState_Sreg0_2 ; 58 ;; mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out586 ; 58 ;; mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_1_sqmuxa_1 ; 54 ;; mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|id2ra_ins_clr_1_0_i_a2_0_a2 ; 54 ;; mips_sys:isys|G_504 ; 53 ;; mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|alu_func_reg_clr:U16|alu_func_o_0 ; 51 ;; mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out587 ; 48 ;; mem_array:ram_8k|ram2048x8_3:ram3|altsyncram:altsyncram_component|altsyncram_hht1:auto_generated|q_a[4] ; 47 ;; mem_array:ram_8k|ram2048x8_3:ram3|altsyncram:altsyncram_component|altsyncram_hht1:auto_generated|q_a[3] ; 45 ;; mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_sn_m25_0 ; 45 ;; mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|alu_func_reg_clr:U16|alu_func_o_4 ; 45 ;; mem_array:ram_8k|ram2048x8_3:ram3|altsyncram:altsyncram_component|altsyncram_hht1:auto_generated|q_a[2] ; 41 ;; mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_4 ; 38 ;; mips_sys:isys|mips_core:mips_core|forward:iforward|forward_node_fw_alu_rs_2:fw_cmp_rs|mux_fw_1 ; 35 ;; mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|sign ; 35 ;; mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|alu_out_sn_m14_0_0 ; 35 ;; mips_sys:isys|mips_core:mips_core|forward:iforward|forward_node_fw_alu_rs_1:fw_alu_rt|mux_fw_1 ; 35 ;; mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout7_0_a2 ; 34 ;; mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqop2_2_32 ; 34 ;; mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_3_sqmuxa ; 34 ;; mem_array:ram_8k|ram2048x8_3:ram3|altsyncram:altsyncram_component|altsyncram_hht1:auto_generated|q_a[7] ; 34 ;; mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|op1_sign_reged_0_sqmuxa_i ; 34 ;; mips_sys:isys|mips_core:mips_core|forward:iforward|forward_node_fw_alu_rs_3:fw_cmp_rt|mux_fw_1 ; 34 ;; mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_sn_m31_i ; 34 ;; mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_0_sqmuxa ; 33 ;; mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|muxa_ctl_reg_clr:U17|muxa_ctl_o_1 ; 33 ;; mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxb:i_alu_muxb|b_o18 ; 33 ;; mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|sum13_0_a2 ; 33 ;; mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|un1_ld_1 ; 33 ;; mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|fwd_mux_2:dmem_fw_mux|dout7 ; 33 ;; ~GND ; 32 ;; mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|N_14_i_0_s2 ; 32 ;; mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|N_18_i_0_s3 ; 32 ;; mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_sqmuxa_0_a4 ; 32 ;; mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_1_sqmuxa_0_a4 ; 32 ;; mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_2_sqmuxa_0_a4 ; 32 ;; mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_next46_0 ; 32 ;; mem_array:ram_8k|ram2048x8_3:ram3|altsyncram:altsyncram_component|altsyncram_hht1:auto_generated|q_a[5] ; 32 ;; mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|un6_a_o ; 32 ;; mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxb:i_alu_muxb|b_o_1_sqmuxa ; 32 ;+-------------------------------------------------------------------------------------------------------------------------+---------++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Fitter RAM Summary ;+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+---------------------+------+--------------+---------------------------------------------------+; Name ; Type ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Port A Input Registers ; Port A Output Registers ; Port B Input Registers ; Port B Output Registers ; Size ; Implementation Bits ; M4Ks ; MIF ; Location ;+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+---------------------+------+--------------+---------------------------------------------------+; mem_array:ram_8k|ram2048x8_0:ram0|altsyncram:altsyncram_component|altsyncram_eht1:auto_generated|ALTSYNCRAM ; AUTO ; True Dual Port ; 2048 ; 8 ; 2048 ; 8 ; yes ; no ; yes ; no ; 16384 ; 16384 ; 4 ; qu2_ram0.mif ; M4K_X17_Y5, M4K_X17_Y13, M4K_X17_Y14, M4K_X17_Y10 ;; mem_array:ram_8k|ram2048x8_1:ram1|altsyncram:altsyncram_component|altsyncram_fht1:auto_generated|ALTSYNCRAM ; AUTO ; True Dual Port ; 2048 ; 8 ; 2048 ; 8 ; yes ; no ; yes ; no ; 16384 ; 16384 ; 4 ; qu2_ram1.mif ; M4K_X17_Y18, M4K_X17_Y11, M4K_X17_Y20, M4K_X17_Y7 ;; mem_array:ram_8k|ram2048x8_2:ram2|altsyncram:altsyncram_component|altsyncram_ght1:auto_generated|ALTSYNCRAM ; AUTO ; True Dual Port ; 2048 ; 8 ; 2048 ; 8 ; yes ; no ; yes ; no ; 16384 ; 16384 ; 4 ; qu2_ram2.mif ; M4K_X17_Y17, M4K_X17_Y4, M4K_X17_Y15, M4K_X17_Y8 ;; mem_array:ram_8k|ram2048x8_3:ram3|altsyncram:altsyncram_component|altsyncram_hht1:auto_generated|ALTSYNCRAM ; AUTO ; True Dual Port ; 2048 ; 8 ; 2048 ; 8 ; yes ; no ; yes ; no ; 16384 ; 16384 ; 4 ; qu2_ram3.mif ; M4K_X17_Y6, M4K_X17_Y16, M4K_X17_Y19, M4K_X17_Y12 ;; mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_1_I_1_Z|altsyncram_3mc1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 32 ; 32 ; 32 ; 32 ; yes ; no ; yes ; no ; 1024 ; 1024 ; 1 ; None ; M4K_X17_Y3 ;; mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_I_1_Z|altsyncram_3mc1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 32 ; 32 ; 32 ; 32 ; yes ; no ; yes ; no ; 1024 ; 1024 ; 1 ; None ; M4K_X17_Y9 ;; mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|dpram_4cm:FIFOram|altsyncram_ihc1:altsyncram1|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 512 ; 8 ; 512 ; 8 ; yes ; no ; yes ; no ; 4096 ; 4096 ; 1 ; None ; M4K_X17_Y2 ;+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+---------------------+------+--------------+---------------------------------------------------++------------------------------------------------------+; Interconnect Usage Summary ;+----------------------------+-------------------------+; Interconnect Resource Type ; Usage ;+----------------------------+-------------------------+; C4s ; 5,731 / 16,320 ( 35 % ) ;; Direct links ; 234 / 21,944 ( 1 % ) ;; Global clocks ; 1 / 8 ( 12 % ) ;; LAB clocks ; 37 / 240 ( 15 % ) ;; LUT chains ; 562 / 5,382 ( 10 % ) ;; Local interconnects ; 7,130 / 21,944 ( 32 % ) ;; M4K buffers ; 136 / 720 ( 18 % ) ;; R4s ; 5,627 / 14,640 ( 38 % ) ;+----------------------------+-------------------------++----------------------------------------------------------------------------+; LAB Logic Elements ;+--------------------------------------------+-------------------------------+; Number of Logic Elements (Average = 7.69) ; Number of LABs (Total = 451) ;+--------------------------------------------+-------------------------------+; 1 ; 8 ;; 2 ; 13 ;; 3 ; 45 ;; 4 ; 17 ;; 5 ; 21 ;; 6 ; 25 ;; 7 ; 32 ;; 8 ; 36 ;; 9 ; 76 ;; 10 ; 178 ;+--------------------------------------------+-------------------------------++--------------------------------------------------------------------+; LAB-wide Signals ;+------------------------------------+-------------------------------+; LAB-wide Signals (Average = 1.14) ; Number of LABs (Total = 451) ;+------------------------------------+-------------------------------+; 1 Async. clear ; 1 ;; 1 Clock ; 267 ;; 1 Clock enable ; 142 ;; 1 Sync. clear ; 99 ;; 1 Sync. load ; 3 ;; 2 Clock enables ; 4 ;+------------------------------------+-------------------------------++-----------------------------------------------------------------------------+; LAB Signals Sourced ;+---------------------------------------------+-------------------------------+; Number of Signals Sourced (Average = 8.33) ; Number of LABs (Total = 451) ;+---------------------------------------------+-------------------------------+; 0 ; 7 ;; 1 ; 7 ;; 2 ; 13 ;; 3 ; 37 ;; 4 ; 20 ;; 5 ; 23 ;; 6 ; 23 ;; 7 ; 29 ;; 8 ; 22 ;; 9 ; 50 ;; 10 ; 116 ;; 11 ; 30 ;; 12 ; 34 ;; 13 ; 24 ;; 14 ; 8 ;; 15 ; 3 ;; 16 ; 1 ;; 17 ; 3 ;; 18 ; 0 ;; 19 ; 1 ;+---------------------------------------------+-------------------------------++---------------------------------------------------------------------------------+; LAB Signals Sourced Out ;+-------------------------------------------------+-------------------------------+; Number of Signals Sourced Out (Average = 4.17) ; Number of LABs (Total = 451) ;+-------------------------------------------------+-------------------------------+; 0 ; 7 ;; 1 ; 45 ;; 2 ; 75 ;; 3 ; 121 ;; 4 ; 43 ;; 5 ; 50 ;; 6 ; 28 ;; 7 ; 24 ;; 8 ; 18 ;; 9 ; 8 ;; 10 ; 23 ;; 11 ; 1 ;; 12 ; 2 ;; 13 ; 3 ;; 14 ; 1 ;; 15 ; 1 ;; 16 ; 0 ;; 17 ; 1 ;+-------------------------------------------------+-------------------------------++------------------------------------------------------------------------------+; LAB Distinct Inputs ;+----------------------------------------------+-------------------------------+; Number of Distinct Inputs (Average = 14.32) ; Number of LABs (Total = 451) ;+----------------------------------------------+-------------------------------+; 0 ; 0 ;; 1 ; 0 ;; 2 ; 4 ;; 3 ; 3 ;; 4 ; 15 ;; 5 ; 8 ;; 6 ; 16 ;; 7 ; 16 ;; 8 ; 6 ;; 9 ; 19 ;; 10 ; 26 ;; 11 ; 19 ;; 12 ; 31 ;; 13 ; 18 ;; 14 ; 25 ;; 15 ; 26 ;; 16 ; 25 ;; 17 ; 31 ;; 18 ; 30 ;; 19 ; 50 ;; 20 ; 40 ;; 21 ; 41 ;; 22 ; 1 ;+----------------------------------------------+-------------------------------++-----------------+; Fitter Messages ;+-----------------+Info: *******************************************************************Info: Running Quartus II FitterInfo: Version 4.2 Build 157 12/07/2004 SJ Full VersionInfo: Processing started: Mon Oct 13 11:59:20 2008Info: Command: quartus_fit --import_settings_files=off --export_settings_files=off mips_top -c mips_topInfo: Selected device EP1C6Q240C6 for design "mips_top"Info: Implementing parameter values for PLL "pll50:Ipll|altpll:altpll_component|pll"Info: Implementing clock multiplication of 2, clock division of 1, and phase shift of 0 degrees (0 ps) for pll50:Ipll|altpll:altpll_component|_clk0 portInfo: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation timeInfo: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices.Info: Device EP1C12Q240C6 is compatibleInfo: Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirementsInfo: Performing register packing on registers with non-logic cell location assignmentsInfo: Completed register packing on registers with non-logic cell location assignmentsInfo: Completed User Assigned Global Signals Promotion OperationInfo: Promoted PLL clock signalsInfo: Promoted signal "pll50:Ipll|altpll:altpll_component|_clk0" to use global clockInfo: Completed PLL Placement OperationInfo: Completed Auto Global Promotion OperationInfo: Starting register packingInfo: Started Fast Input/Output/OE register processingInfo: Finished Fast Input/Output/OE register processingInfo: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic optionInfo: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and densityInfo: Finished moving registers into I/O cells, LUTs, and RAM blocksInfo: Finished register packingWarning: Following nodes are assigned to locations or regions, but do not exist in designWarning: Node "FLASH_ADDR[0]" is assigned to location or region, but does not exist in designWarning: Node "FLASH_ADDR[10]" is assigned to location or region, but does not exist in designWarning: Node "FLASH_ADDR[11]" is assigned to location or region, but does not exist in designWarning: Node "FLASH_ADDR[12]" is assigned to location or region, but does not exist in designWarning: Node "FLASH_ADDR[13]" is assigned to location or region, but does not exist in designWarning: Node "FLASH_ADDR[14]" is assigned to location or region, but does not exist in designWarning: Node "FLASH_ADDR[15]" is assigned to location or region, but does not exist in designWarning: Node "FLASH_ADDR[16]" is assigned to location or region, but does not exist in designWarning: Node "FLASH_ADDR[17]" is assigned to location or region, but does not exist in designWarning: Node "FLASH_ADDR[18]" is assigned to location or region, but does not exist in designWarning: Node "FLASH_ADDR[19]" is assigned to location or region, but does not exist in designWarning: Node "FLASH_ADDR[1]" is assigned to location or region, but does not exist in designWarning: Node "FLASH_ADDR[2]" is assigned to location or region, but does not exist in designWarning: Node "FLASH_ADDR[3]" is assigned to location or region, but does not exist in designWarning: Node "FLASH_ADDR[4]" is assigned to location or region, but does not exist in designWarning: Node "FLASH_ADDR[5]" is assigned to location or region, but does not exist in designWarning: Node "FLASH_ADDR[6]" is assigned to location or region, but does not exist in designWarning: Node "FLASH_ADDR[7]" is assigned to location or region, but does not exist in designWarning: Node "FLASH_ADDR[8]" is assigned to location or region, but does not exist in designWarning: Node "FLASH_ADDR[9]" is assigned to location or region, but does not exist in designWarning: Node "FLASH_BYTE" is assigned to location or region, but does not exist in designWarning: Node "FLASH_CE" is assigned to location or region, but does not exist in designWarning: Node "FLASH_DQ[0]" is assigned to location or region, but does not exist in designWarning: Node "FLASH_DQ[10]" is assigned to location or region, but does not exist in designWarning: Node "FLASH_DQ[11]" is assigned to location or region, but does not exist in designWarning: Node "FLASH_DQ[12]" is assigned to location or region, but does not exist in designWarning: Node "FLASH_DQ[13]" is assigned to location or region, but does not exist in designWarning: Node "FLASH_DQ[14]" is assigned to location or region, but does not exist in designWarning: Node "FLASH_DQ[15]" is assigned to location or region, but does not exist in designWarning: Node "FLASH_DQ[1]" is assigned to location or region, but does not exist in designWarning: Node "FLASH_DQ[2]" is assigned to location or region, but does not exist in designWarning: Node "FLASH_DQ[3]" is assigned to location or region, but does not exist in designWarning: Node "FLASH_DQ[4]" is assigned to location or region, but does not exist in designWarning: Node "FLASH_DQ[5]" is assigned to location or region, but does not exist in designWarning: Node "FLASH_DQ[6]" is assigned to location or region, but does not exist in designWarning: Node "FLASH_DQ[7]" is assigned to location or region, but does not exist in designWarning: Node "FLASH_DQ[8]" is assigned to location or region, but does not exist in designWarning: Node "FLASH_DQ[9]" is assigned to location or region, but does not exist in designWarning: Node "FLASH_OE" is assigned to location or region, but does not exist in designWarning: Node "FLASH_RESET" is assigned to location or region, but does not exist in designWarning: Node "FLASH_WE" is assigned to location or region, but does not exist in designWarning: Node "sd_addr[0]" is assigned to location or region, but does not exist in designWarning: Node "sd_addr[10]" is assigned to location or region, but does not exist in designWarning: Node "sd_addr[11]" is assigned to location or region, but does not exist in designWarning: Node "sd_addr[1]" is assigned to location or region, but does not exist in designWarning: Node "sd_addr[2]" is assigned to location or region, but does not exist in designWarning: Node "sd_addr[3]" is assigned to location or region, but does not exist in designWarning: Node "sd_addr[4]" is assigned to location or region, but does not exist in designWarning: Node "sd_addr[5]" is assigned to location or region, but does not exist in designWarning: Node "sd_addr[6]" is assigned to location or region, but does not exist in designWarning: Node "sd_addr[7]" is assigned to location or region, but does not exist in designWarning: Node "sd_addr[8]" is assigned to location or region, but does not exist in designWarning: Node "sd_addr[9]" is assigned to location or region, but does not exist in designWarning: Node "sd_ba[0]" is assigned to location or region, but does not exist in designWarning: Node "sd_ba[1]" is assigned to location or region, but does not exist in designWarning: Node "sd_cas" is assigned to location or region, but does not exist in designWarning: Node "sd_cke" is assigned to location or region, but does not exist in designWarning: Node "sd_clk" is assigned to location or region, but does not exist in designWarning: Node "sd_cs" is assigned to location or region, but does not exist in designWarning: Node "sd_data[0]" is assigned to location or region, but does not exist in designWarning: Node "sd_data[10]" is assigned to location or region, but does not exist in designWarning: Node "sd_data[11]" is assigned to location or region, but does not exist in designWarning: Node "sd_data[12]" is assigned to location or region, but does not exist in designWarning: Node "sd_data[13]" is assigned to location or region, but does not exist in designWarning: Node "sd_data[14]" is assigned to location or region, but does not exist in designWarning: Node "sd_data[15]" is assigned to location or region, but does not exist in designWarning: Node "sd_data[1]" is assigned to location or region, but does not exist in designWarning: Node "sd_data[2]" is assigned to location or region, but does not exist in designWarning: Node "sd_data[3]" is assigned to location or region, but does not exist in designWarning: Node "sd_data[4]" is assigned to location or region, but does not exist in designWarning: Node "sd_data[5]" is assigned to location or region, but does not exist in designWarning: Node "sd_data[6]" is assigned to location or region, but does not exist in designWarning: Node "sd_data[7]" is assigned to location or region, but does not exist in designWarning: Node "sd_data[8]" is assigned to location or region, but does not exist in designWarning: Node "sd_data[9]" is assigned to location or region, but does not exist in designWarning: Node "sd_dqm[0]" is assigned to location or region, but does not exist in designWarning: Node "sd_dqm[1]" is assigned to location or region, but does not exist in designWarning: Node "sd_ras" is assigned to location or region, but does not exist in designWarning: Node "sd_we" is assigned to location or region, but does not exist in designWarning: Node "uart_rxd_usb" is assigned to location or region, but does not exist in designWarning: Node "uart_txd_usb" is assigned to location or region, but does not exist in designInfo: Fitter placement preparation operations beginningInfo: Fitter placement preparation operations ending: elapsed time = 26 secondsInfo: Fitter placement operations beginningInfo: Fitter placement was successfulInfo: Estimated most critical path is register to memory delay of 16.886 nsInfo: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X25_Y8; Fanout = 6; REG Node = 'mips_sys:isys|mips_core:mips_core|r5_reg_1:rnd_pass1|r5_o_4'Info: 2: + IC(0.787 ns) + CELL(0.340 ns) = 1.127 ns; Loc. = LAB_X26_Y10; Fanout = 1; COMB Node = 'mips_sys:isys|mips_core:mips_core|forward:iforward|forward_node_fw_alu_rs:fw_alu_rs|un14_mux_fw_a'Info: 3: + IC(0.463 ns) + CELL(0.088 ns) = 1.678 ns; Loc. = LAB_X26_Y10; Fanout = 5; COMB Node = 'mips_sys:isys|mips_core:mips_core|forward:iforward|forward_node_fw_alu_rs:fw_alu_rs|un14_mux_fw'Info: 4: + IC(1.202 ns) + CELL(0.088 ns) = 2.968 ns; Loc. = LAB_X21_Y12; Fanout = 35; COMB Node = 'mips_sys:isys|mips_core:mips_core|forward:iforward|forward_node_fw_alu_rs_1:fw_alu_rt|mux_fw_1'Info: 5: + IC(0.422 ns) + CELL(0.088 ns) = 3.478 ns; Loc. = LAB_X21_Y12; Fanout = 65; COMB Node = 'mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|fwd_mux_2:dmem_fw_mux|dout7'Info: 6: + IC(0.211 ns) + CELL(0.340 ns) = 4.029 ns; Loc. = LAB_X21_Y12; Fanout = 32; COMB Node = 'mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxb:i_alu_muxb|b_o_1_sqmuxa'Info: 7: + IC(1.037 ns) + CELL(0.340 ns) = 5.406 ns; Loc. = LAB_X21_Y5; Fanout = 2; COMB Node = 'mips_sys:isys|mips_core:mips_core|BUS15471_i_m[16]'Info: 8: + IC(0.422 ns) + CELL(0.088 ns) = 5.916 ns; Loc. = LAB_X21_Y5; Fanout = 27; COMB Node = 'mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|b_o_iv_16'Info: 9: + IC(1.040 ns) + CELL(0.340 ns) = 7.296 ns; Loc. = LAB_X21_Y13; Fanout = 1; COMB Node = 'mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_79_a[8]'Info: 10: + IC(0.422 ns) + CELL(0.088 ns) = 7.806 ns; Loc. = LAB_X21_Y13; Fanout = 4; COMB Node = 'mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_79[8]'Info: 11: + IC(0.285 ns) + CELL(0.225 ns) = 8.316 ns; Loc. = LAB_X21_Y13; Fanout = 1; COMB Node = 'mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_74_a[0]'Info: 12: + IC(0.882 ns) + CELL(0.088 ns) = 9.286 ns; Loc. = LAB_X19_Y13; Fanout = 1; COMB Node = 'mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_74[0]'Info: 13: + IC(0.285 ns) + CELL(0.225 ns) = 9.796 ns; Loc. = LAB_X19_Y13; Fanout = 1; COMB Node = 'mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_86[0]'Info: 14: + IC(1.084 ns) + CELL(0.225 ns) = 11.105 ns; Loc. = LAB_X14_Y9; Fanout = 1; COMB Node = 'mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_a[0]'Info: 15: + IC(0.422 ns) + CELL(0.088 ns) = 11.615 ns; Loc. = LAB_X14_Y9; Fanout = 2; COMB Node = 'mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_0'Info: 16: + IC(0.285 ns) + CELL(0.225 ns) = 12.125 ns; Loc. = LAB_X14_Y9; Fanout = 7; COMB Node = 'mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|infile_dmem_ctl_reg:dmem_ctl_post|c_0_d0'Info: 17: + IC(0.422 ns) + CELL(0.088 ns) = 12.635 ns; Loc. = LAB_X14_Y9; Fanout = 4; COMB Node = 'mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_addr_ctl:i_mem_addr_ctl|un1_wr_en46_3_combout'Info: 18: + IC(0.000 ns) + CELL(2.508 ns) = 15.143 ns; Loc. = LAB_X13_Y9; Fanout = 9; COMB LOOP Node = 'mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_addr_ctl:i_mem_addr_ctl|SYNLPM_LATRS1:wr_en_1_1_|lpm_latch:U1|q[0]~95'Info: Loc. = LAB_X13_Y9; Node "mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_addr_ctl:i_mem_addr_ctl|SYNLPM_LATRS1:wr_en_1_1_|lpm_latch:U1|q[0]~95"Info: Loc. = LAB_X13_Y9; Node "mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_addr_ctl:i_mem_addr_ctl|SYNLPM_LATRS1:wr_en_1_1_|lpm_latch:U1|q[0]~94"Info: 19: + IC(1.432 ns) + CELL(0.311 ns) = 16.886 ns; Loc. = M4K_X17_Y20; Fanout = 0; MEM Node = 'mem_array:ram_8k|ram2048x8_1:ram1|altsyncram:altsyncram_component|altsyncram_fht1:auto_generated|ram_block1a3~portb_we_reg'Info: Total cell delay = 5.783 ns ( 34.25 % )Info: Total interconnect delay = 11.103 ns ( 65.75 % )Info: Estimated interconnect usage is 39% of the available device resourcesInfo: Fitter placement operations ending: elapsed time = 36 secondsInfo: Fitter routing operations beginningInfo: Fitter routing operations ending: elapsed time = 46 secondsInfo: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.Info: Completed Fixed Delay Chain OperationInfo: Started post-fitting delay annotationInfo: Delay annotation completed successfullyInfo: Completed Auto Delay Chain OperationInfo: Quartus II Fitter was successful. 0 errors, 82 warningsInfo: Processing ended: Mon Oct 13 12:02:00 2008Info: Elapsed time: 00:02:40
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