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Analysis & Synthesis report for mips_top
Mon Oct 13 11:59:16 2008
Version 4.2 Build 157 12/07/2004 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Hierarchy
  5. Cut Buffers Inserted to Break Combinational Loops
  6. General Register Statistics
  7. WYSIWYG Cells
  8. Analysis & Synthesis Resource Utilization by Entity
  9. Analysis & Synthesis Equations
 10. Analysis & Synthesis Source Files Read
 11. Analysis & Synthesis Resource Usage Summary
 12. Analysis & Synthesis RAM Summary
 13. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2004 Altera Corporation
Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
support information,  device programming or simulation file,  and any other
associated  documentation or information  provided by  Altera  or a partner
under  Altera's   Megafunction   Partnership   Program  may  be  used  only
to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
other  use  of such  megafunction  design,  netlist,  support  information,
device programming or simulation file,  or any other  related documentation
or information  is prohibited  for  any  other purpose,  including, but not
limited to  modification,  reverse engineering,  de-compiling, or use  with
any other  silicon devices,  unless such use is  explicitly  licensed under
a separate agreement with  Altera  or a megafunction partner.  Title to the
intellectual property,  including patents,  copyrights,  trademarks,  trade
secrets,  or maskworks,  embodied in any such megafunction design, netlist,
support  information,  device programming or simulation file,  or any other
related documentation or information provided by  Altera  or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.



+------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                           ;
+-----------------------------+------------------------------------------+
; Analysis & Synthesis Status ; Successful - Mon Oct 13 11:59:16 2008    ;
; Quartus II Version          ; 4.2 Build 157 12/07/2004 SJ Full Version ;
; Revision Name               ; mips_top                                 ;
; Top-level Entity Name       ; mips_top                                 ;
; Family                      ; Cyclone                                  ;
; Total logic elements        ; 3,649                                    ;
; Total pins                  ; 33                                       ;
; Total virtual pins          ; 0                                        ;
; Total memory bits           ; 71,680                                   ;
; Total PLLs                  ; 1                                        ;
+-----------------------------+------------------------------------------+


+---------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                     ;
+--------------------------------------------------------------------+--------------+---------------+
; Option                                                             ; Setting      ; Default Value ;
+--------------------------------------------------------------------+--------------+---------------+
; Device                                                             ; EP1C6Q240C6  ;               ;
; Family name                                                        ; Cyclone      ; Stratix       ;
; Use smart compilation                                              ; Normal       ; Normal        ;
; Restructure Multiplexers                                           ; Auto         ; Auto          ;
; Create Debugging Nodes for IP Cores                                ; off          ; off           ;
; Preserve fewer node names                                          ; On           ; On            ;
; Disable OpenCore Plus hardware evaluation                          ; Off          ; Off           ;
; Verilog Version                                                    ; Verilog_2001 ; Verilog_2001  ;
; VHDL Version                                                       ; VHDL93       ; VHDL93        ;
; Top-level entity name                                              ; mips_top     ; mips_top      ;
; State Machine Processing                                           ; Auto         ; Auto          ;
; Extract Verilog State Machines                                     ; On           ; On            ;
; Extract VHDL State Machines                                        ; On           ; On            ;
; NOT Gate Push-Back                                                 ; On           ; On            ;
; Power-Up Don't Care                                                ; On           ; On            ;
; Remove Redundant Logic Cells                                       ; Off          ; Off           ;
; Remove Duplicate Registers                                         ; On           ; On            ;
; Ignore CARRY Buffers                                               ; Off          ; Off           ;
; Ignore CASCADE Buffers                                             ; Off          ; Off           ;
; Ignore GLOBAL Buffers                                              ; Off          ; Off           ;
; Ignore ROW GLOBAL Buffers                                          ; Off          ; Off           ;
; Ignore LCELL Buffers                                               ; Off          ; Off           ;
; Ignore SOFT Buffers                                                ; On           ; On            ;
; Limit AHDL Integers to 32 Bits                                     ; Off          ; Off           ;
; Optimization Technique -- Cyclone                                  ; Balanced     ; Balanced      ;
; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II ; 70           ; 70            ;
; Auto Carry Chains                                                  ; On           ; On            ;
; Auto Open-Drain Pins                                               ; On           ; On            ;
; Remove Duplicate Logic                                             ; On           ; On            ;
; Perform WYSIWYG Primitive Resynthesis                              ; Off          ; Off           ;
; Perform gate-level register retiming                               ; Off          ; Off           ;
; Allow register retiming to trade off Tsu/Tco with Fmax             ; On           ; On            ;
; Auto ROM Replacement                                               ; On           ; On            ;
; Auto RAM Replacement                                               ; On           ; On            ;
; Auto Shift Register Replacement                                    ; On           ; On            ;
; Auto Clock Enable Replacement                                      ; On           ; On            ;
; Allows Synchronous Control Signal Usage in Normal Mode Logic Cells ; On           ; On            ;
; Auto RAM Block Balancing                                           ; On           ; On            ;
; Auto Resource Sharing                                              ; Off          ; Off           ;
; Allow Any RAM Size For Recognition                                 ; Off          ; Off           ;
; Allow Any ROM Size For Recognition                                 ; Off          ; Off           ;
; Allow Any Shift Register Size For Recognition                      ; Off          ; Off           ;
; Enable M512 Memory Blocks                                          ; On           ; On            ;
+--------------------------------------------------------------------+--------------+---------------+


+-----------+
; Hierarchy ;
+-----------+
mips_top
 |-- pll50:Ipll
      |-- altpll:altpll_component
 |-- mips_sys:isys
      |-- mips_dvc:imips_dvc
           |-- seg7led_cv:iseg7_cv
           |-- uart0:iuart0
                |-- rxd_d:rxd_rdy_hold_lw
                |-- uart_read:uart_rd_tak
                |-- uart_write:uart_txd
                     |-- fifo512_cyclone:fifo
                          |-- scfifo_Z1:scfifo_component
                               |-- scfifo:U1
                                    |-- scfifo_e4u:auto_generated
                                         |-- a_dpfifo_lqr:dpfifo
                                              |-- a_fefifo_s7f:fifo_state
                                                   |-- cntr_cc7:count_usedw
                                              |-- dpram_4cm:FIFOram
                                                   |-- altsyncram_ihc1:altsyncram1
                                              |-- cntr_ud8:rd_ptr_count
                                              |-- cntr_ud8:wr_ptr
           |-- tmr0:mips_tmr0
      |-- mips_core:mips_core
           |-- mem_module:MEM_CTL
                |-- infile_dmem_ctl_reg:dmem_ctl_post
                |-- mem_addr_ctl:i_mem_addr_ctl
                     |-- SYNLPM_LATRS1:wr_en_1_0_
                          |-- lpm_latch:U1
                     |-- SYNLPM_LATRS1:wr_en_1_1_
                          |-- lpm_latch:U1
                     |-- SYNLPM_LATRS1:wr_en_1_2_
                          |-- lpm_latch:U1
                     |-- SYNLPM_LATRS1:wr_en_1_3_
                          |-- lpm_latch:U1
                |-- mem_din_ctl:i_mem_din_ctl
                |-- mem_dout_ctl:i_mem_dout_ctl
                     |-- SYNLPM_LATR1:dout_1_0__Z
                          |-- lpm_latch:U1
                     |-- SYNLPM_LATR1:dout_1_1__Z
                          |-- lpm_latch:U1
                     |-- SYNLPM_LATR1:dout_1_2__Z
                          |-- lpm_latch:U1
                     |-- SYNLPM_LATR1:dout_1_3__Z
                          |-- lpm_latch:U1
                     |-- SYNLPM_LATR1:dout_1_4__Z
                          |-- lpm_latch:U1
                     |-- SYNLPM_LATR1:dout_1_5__Z
                          |-- lpm_latch:U1
                     |-- SYNLPM_LATR1:dout_1_6__Z
                          |-- lpm_latch:U1
                     |-- SYNLPM_LATR1:dout_1_7__Z
                          |-- lpm_latch:U1
                     |-- SYNLPM_LATR1:dout_1_8__Z
                          |-- lpm_latch:U1
                     |-- SYNLPM_LATR1:dout_1_9__Z
                          |-- lpm_latch:U1
                     |-- SYNLPM_LATR1:dout_1_10__Z
                          |-- lpm_latch:U1
                     |-- SYNLPM_LATR1:dout_1_11__Z
                          |-- lpm_latch:U1
                     |-- SYNLPM_LATR1:dout_1_12__Z
                          |-- lpm_latch:U1
                     |-- SYNLPM_LATR1:dout_1_13__Z
                          |-- lpm_latch:U1
                     |-- SYNLPM_LATR1:dout_1_14__Z
                          |-- lpm_latch:U1
                     |-- SYNLPM_LATR1:dout_1_15__Z
                          |-- lpm_latch:U1
                     |-- SYNLPM_LATR1:dout_1_16__Z
                          |-- lpm_latch:U1
                     |-- SYNLPM_LATR1:dout_1_17__Z
                          |-- lpm_latch:U1
                     |-- SYNLPM_LATR1:dout_1_18__Z
                          |-- lpm_latch:U1
                     |-- SYNLPM_LATR1:dout_1_19__Z
                          |-- lpm_latch:U1
                     |-- SYNLPM_LATR1:dout_1_20__Z
                          |-- lpm_latch:U1
                     |-- SYNLPM_LATR1:dout_1_21__Z
                          |-- lpm_latch:U1
                     |-- SYNLPM_LATR1:dout_1_22__Z
                          |-- lpm_latch:U1
                     |-- SYNLPM_LATR1:dout_1_23__Z
                          |-- lpm_latch:U1
                     |-- SYNLPM_LATR1:dout_1_24__Z
                          |-- lpm_latch:U1
                     |-- SYNLPM_LATR1:dout_1_25__Z
                          |-- lpm_latch:U1
                     |-- SYNLPM_LATR1:dout_1_26__Z
                          |-- lpm_latch:U1
                     |-- SYNLPM_LATR1:dout_1_27__Z
                          |-- lpm_latch:U1
                     |-- SYNLPM_LATR1:dout_1_28__Z
                          |-- lpm_latch:U1
                     |-- SYNLPM_LATR1:dout_1_29__Z
                          |-- lpm_latch:U1
                     |-- SYNLPM_LATR1:dout_1_30__Z
                          |-- lpm_latch:U1
                     |-- SYNLPM_LATR1:dout_1_31__Z
                          |-- lpm_latch:U1
           |-- r32_reg_1:alu_pass0
           |-- r32_reg_2:alu_pass1
           |-- r32_reg_3:cop_data_reg
           |-- r32_reg_4:cop_dout_reg
           |-- decode_pipe:decoder_pipe
                |-- decoder:idecoder
                     |-- SYNLPM_LATR1:alu_func_1_0_
                          |-- lpm_latch:U1
                     |-- SYNLPM_LATR1:alu_func_1_1_
                          |-- lpm_latch:U1
                     |-- SYNLPM_LATRS1:alu_func_1_2_
                          |-- lpm_latch:U1
                     |-- SYNLPM_LATRS1:alu_func_1_3_
                          |-- lpm_latch:U1
                     |-- SYNLPM_LATR1:alu_func_1_4_
                          |-- lpm_latch:U1
                     |-- SYNLPM_LATR1:alu_we_0_
                          |-- lpm_latch:U1
                     |-- SYNLPM_LATR1:cmp_ctl_1_0_
                          |-- lpm_latch:U1
                     |-- SYNLPM_LATR1:cmp_ctl_1_1_
                          |-- lpm_latch:U1
                     |-- SYNLPM_LATR1:cmp_ctl_1_2_
                          |-- lpm_latch:U1
                     |-- SYNLPM_LATRS1:dmem_ctl_1_0_
                          |-- lpm_latch:U1
                     |-- SYNLPM_LATRS1:dmem_ctl_1_1_
                          |-- lpm_latch:U1
                     |-- SYNLPM_LATRS1:dmem_ctl_1_2_
                          |-- lpm_latch:U1
                     |-- SYNLPM_LATR1:dmem_ctl_1_3_
                          |-- lpm_latch:U1
                     |-- SYNLPM_LATRS1:ext_ctl_1_0_
                          |-- lpm_latch:U1
                     |-- SYNLPM_LATR1:ext_ctl_1_1_
                          |-- lpm_latch:U1
                     |-- SYNLPM_LATR1:ext_ctl_1_2_
                          |-- lpm_latch:U1
                     |-- SYNLPM_LATR1:fsm_dly_1_0_
                          |-- lpm_latch:U1
                     |-- SYNLPM_LATR1:fsm_dly_1_1__Z
                          |-- lpm_latch:U1
                     |-- SYNLPM_LATR1:fsm_dly_1_2__Z
                          |-- lpm_latch:U1
                     |-- SYNLPM_LATR1:muxa_ctl_1_0_
                          |-- lpm_latch:U1
                     |-- SYNLPM_LATRS1:muxa_ctl_1_1_
                          |-- lpm_latch:U1
                     |-- SYNLPM_LATR1:muxb_ctl_1_0_
                          |-- lpm_latch:U1
                     |-- SYNLPM_LATRS1:muxb_ctl_1_1_
                          |-- lpm_latch:U1
                     |-- SYNLPM_LATRS1:pc_gen_ctl_1_0_
                          |-- lpm_latch:U1
                     |-- SYNLPM_LATR1:pc_gen_ctl_1_1_
                          |-- lpm_latch:U1
                     |-- SYNLPM_LATRS1:pc_gen_ctl_1_2_
                          |-- lpm_latch:U1
                     |-- SYNLPM_LATR1:rd_sel_1_0_
                          |-- lpm_latch:U1
                     |-- SYNLPM_LATRS1:rd_sel_1_1_
                          |-- lpm_latch:U1
                     |-- SYNLPM_LATR1:wb_mux_0_
                          |-- lpm_latch:U1
                     |-- SYNLPM_LATR1:wb_we_0_
                          |-- lpm_latch:U1
                |-- pipelinedregs:pipereg
                     |-- muxb_ctl_reg_clr_cls:U1
                     |-- cmp_ctl_reg_clr_cls:U2
                     |-- dmem_ctl_reg_clr_cls:U3
                     |-- ext_ctl_reg_clr_cls:U4
                     |-- rd_sel_reg_clr_cls:U5
                     |-- alu_we_reg_clr_cls:U6
                     |-- muxa_ctl_reg_clr_cls:U7
                     |-- pc_gen_ctl_reg_clr_cls:U8
                     |-- dmem_ctl_reg:U9
                     |-- wb_mux_ctl_reg_clr_cls:U10
                     |-- wb_we_reg_clr_cls:U11
                     |-- wb_we_reg:U12
                     |-- wb_mux_ctl_reg_clr:U13
                     |-- muxb_ctl_reg_clr:U14
                     |-- dmem_ctl_reg_clr:U15
                     |-- alu_func_reg_clr:U16
                     |-- muxa_ctl_reg_clr:U17
                     |-- wb_mux_ctl_reg:U18
                     |-- wb_we_reg_clr:U19
                     |-- wb_we_reg_1:U20
                     |-- wb_mux_ctl_reg_1:U21
                     |-- wb_we_reg_2:U22
                     |-- alu_we_reg_clr:U24
                     |-- alu_func_reg_clr_cls:U26
           |-- r32_reg_5:ext_reg
           |-- rf_stage:iRF_stage
                |-- ctl_FSM:MIAN_FSM
                     |-- SYNLPM_LATR1:next_delay_counter_Sreg0_0_
                          |-- lpm_latch:U1
                     |-- SYNLPM_LATS1:next_delay_counter_Sreg0_1_
                          |-- lpm_latch:U1
                     |-- SYNLPM_LATR1:next_delay_counter_Sreg0_2__Z
                          |-- lpm_latch:U1
                     |-- SYNLPM_LATR1:next_delay_counter_Sreg0_3__Z
                          |-- lpm_latch:U1
                     |-- SYNLPM_LATR1:next_delay_counter_Sreg0_4__Z
                          |-- lpm_latch:U1
                     |-- SYNLPM_LATS1:next_delay_counter_Sreg0_5_
                          |-- lpm_latch:U1
                |-- compare:i_cmp
                |-- ext:i_ext
                |-- pc_gen:i_pc_gen
                |-- r32_reg_clr_cls:ins_reg
                |-- reg_array:reg_bank_cZ
                     |-- altsyncram:reg_bank_1_I_1_Z
                          |-- altsyncram_3mc1:auto_generated
                     |-- altsyncram:reg_bank_I_1_Z
                          |-- altsyncram_3mc1:auto_generated
                |-- fwd_mux:rf_fwd_rt
                |-- fwd_mux_1:rs_fwd_rs
           |-- exec_stage:iexec_stage
                |-- big_alu:MIPS_alu
                     |-- alu:mips_alu
                     |-- shifter_tak:mips_shifter
                     |-- muldiv_ff:muldiv_ff
                |-- fwd_mux_2:dmem_fw_mux
                |-- alu_muxa:i_alu_muxa
                |-- alu_muxb:i_alu_muxb
                |-- r32_reg:pc_nxt
                |-- r32_reg_cls:spc
           |-- forward:iforward
                |-- forward_node_fw_alu_rs:fw_alu_rs
                |-- forward_node_fw_alu_rs_1:fw_alu_rt
                |-- forward_node_fw_alu_rs_2:fw_cmp_rs
                |-- forward_node_fw_alu_rs_3:fw_cmp_rt
                |-- fw_latch5:fw_reg_rns
                |-- fw_latch5_1:fw_reg_rnt
           |-- r32_reg_6:pc
           |-- r5_reg:rnd_pass0
           |-- r5_reg_1:rnd_pass1
           |-- r5_reg_2:rnd_pass2
           |-- r32_reg_7:rs_reg
           |-- r32_reg_8:rt_reg
 |-- mem_array:ram_8k
      |-- ram2048x8_0:ram0
           |-- altsyncram:altsyncram_component
                |-- altsyncram_eht1:auto_generated
      |-- ram2048x8_1:ram1
           |-- altsyncram:altsyncram_component
                |-- altsyncram_fht1:auto_generated
      |-- ram2048x8_2:ram2
           |-- altsyncram:altsyncram_component
                |-- altsyncram_ght1:auto_generated
      |-- ram2048x8_3:ram3
           |-- altsyncram:altsyncram_component
                |-- altsyncram_hht1:auto_generated


+-------------------------------------------------------------------------------------------------------------------------------------------+
; Cut Buffers Inserted to Break Combinational Loops                                                                                         ;
+--------------------------------------------------------------------------------------------------------------------------------------+----+
; Buffer Name                                                                                                                          ;    ;
+--------------------------------------------------------------------------------------------------------------------------------------+----+
; mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_7__Z|lpm_latch:U1|q[0]~0        ;    ;
; mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_6__Z|lpm_latch:U1|q[0]~0        ;    ;
; mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_5__Z|lpm_latch:U1|q[0]~0        ;    ;
; mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_4__Z|lpm_latch:U1|q[0]~0        ;    ;
; mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_3__Z|lpm_latch:U1|q[0]~0        ;    ;
; mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_2__Z|lpm_latch:U1|q[0]~0        ;    ;
; mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_1__Z|lpm_latch:U1|q[0]~0        ;    ;
; mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_0__Z|lpm_latch:U1|q[0]~0        ;    ;
; mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:alu_func_1_1_|lpm_latch:U1|q[0]~0           ;    ;
; mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:alu_func_1_4_|lpm_latch:U1|q[0]~0           ;    ;
; mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:alu_func_1_0_|lpm_latch:U1|q[0]~0           ;    ;
; mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:dmem_ctl_1_2_|lpm_latch:U1|q[0]~0          ;    ;
; mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:dmem_ctl_1_0_|lpm_latch:U1|q[0]~0          ;    ;
; mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:dmem_ctl_1_1_|lpm_latch:U1|q[0]~0          ;    ;
; mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:wb_mux_0_|lpm_latch:U1|q[0]~0               ;    ;
; mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:wb_we_0_|lpm_latch:U1|q[0]~0                ;    ;
; mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:alu_we_0_|lpm_latch:U1|q[0]~0               ;    ;
; mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:fsm_dly_1_0_|lpm_latch:U1|q[0]~0            ;    ;
; mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:fsm_dly_1_1__Z|lpm_latch:U1|q[0]~0          ;    ;
; mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:fsm_dly_1_2__Z|lpm_latch:U1|q[0]~0          ;    ;
; mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:alu_func_1_2_|lpm_latch:U1|q[0]~0          ;    ;
; mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:alu_func_1_3_|lpm_latch:U1|q[0]~0          ;    ;
; mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:muxa_ctl_1_0_|lpm_latch:U1|q[0]~0           ;    ;
; mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:rd_sel_1_0_|lpm_latch:U1|q[0]~0             ;    ;
; mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:rd_sel_1_1_|lpm_latch:U1|q[0]~0            ;    ;
; mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:muxa_ctl_1_1_|lpm_latch:U1|q[0]~0          ;    ;
; mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:dmem_ctl_1_3_|lpm_latch:U1|q[0]~0           ;    ;
; mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_addr_ctl:i_mem_addr_ctl|SYNLPM_LATRS1:wr_en_1_0_|lpm_latch:U1|q[0]~0        ;    ;
; mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_addr_ctl:i_mem_addr_ctl|SYNLPM_LATRS1:wr_en_1_2_|lpm_latch:U1|q[0]~0        ;    ;
; mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:muxb_ctl_1_0_|lpm_latch:U1|q[0]~0           ;    ;
; mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:muxb_ctl_1_1_|lpm_latch:U1|q[0]~0          ;    ;
; mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:ext_ctl_1_1_|lpm_latch:U1|q[0]~0            ;    ;
; mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:ext_ctl_1_2_|lpm_latch:U1|q[0]~0            ;    ;
; mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:ext_ctl_1_0_|lpm_latch:U1|q[0]~0           ;    ;
; mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_8__Z|lpm_latch:U1|q[0]~0        ;    ;
; mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_9__Z|lpm_latch:U1|q[0]~0        ;    ;
; mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|SYNLPM_LATR1:next_delay_counter_Sreg0_0_|lpm_latch:U1|q[0]~0   ;    ;
; mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|SYNLPM_LATS1:next_delay_counter_Sreg0_5_|lpm_latch:U1|q[0]~0   ;    ;
; mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_addr_ctl:i_mem_addr_ctl|SYNLPM_LATRS1:wr_en_1_1_|lpm_latch:U1|q[0]~0        ;    ;
; mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_addr_ctl:i_mem_addr_ctl|SYNLPM_LATRS1:wr_en_1_3_|lpm_latch:U1|q[0]~0        ;    ;
; mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_31__Z|lpm_latch:U1|q[0]~0       ;    ;
; mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:pc_gen_ctl_1_2_|lpm_latch:U1|q[0]~0        ;    ;
; mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:pc_gen_ctl_1_0_|lpm_latch:U1|q[0]~0        ;    ;
; mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:pc_gen_ctl_1_1_|lpm_latch:U1|q[0]~0         ;    ;
; mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|SYNLPM_LATS1:next_delay_counter_Sreg0_1_|lpm_latch:U1|q[0]~0   ;    ;
; mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|SYNLPM_LATR1:next_delay_counter_Sreg0_2__Z|lpm_latch:U1|q[0]~0 ;    ;
; mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|SYNLPM_LATR1:next_delay_counter_Sreg0_3__Z|lpm_latch:U1|q[0]~0 ;    ;
; mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|SYNLPM_LATR1:next_delay_counter_Sreg0_4__Z|lpm_latch:U1|q[0]~0 ;    ;
; mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_30__Z|lpm_latch:U1|q[0]~0       ;    ;
; mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_28__Z|lpm_latch:U1|q[0]~0       ;    ;
; mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_29__Z|lpm_latch:U1|q[0]~0       ;    ;
; mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_11__Z|lpm_latch:U1|q[0]~0       ;    ;
; mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_13__Z|lpm_latch:U1|q[0]~0       ;    ;
; mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_12__Z|lpm_latch:U1|q[0]~0       ;    ;
; mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_14__Z|lpm_latch:U1|q[0]~0       ;    ;
; mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_21__Z|lpm_latch:U1|q[0]~0       ;    ;
; mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_22__Z|lpm_latch:U1|q[0]~0       ;    ;
; mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_25__Z|lpm_latch:U1|q[0]~0       ;    ;
; mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_26__Z|lpm_latch:U1|q[0]~0       ;    ;
; mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_17__Z|lpm_latch:U1|q[0]~0       ;    ;
; mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_18__Z|lpm_latch:U1|q[0]~0       ;    ;
; mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_10__Z|lpm_latch:U1|q[0]~0       ;    ;
; mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_15__Z|lpm_latch:U1|q[0]~0       ;    ;
; mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_27__Z|lpm_latch:U1|q[0]~0       ;    ;
; mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_19__Z|lpm_latch:U1|q[0]~0       ;    ;
; mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_20__Z|lpm_latch:U1|q[0]~0       ;    ;
; mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_16__Z|lpm_latch:U1|q[0]~0       ;    ;
; mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_23__Z|lpm_latch:U1|q[0]~0       ;    ;
; mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_24__Z|lpm_latch:U1|q[0]~0       ;    ;
; mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:cmp_ctl_1_0_|lpm_latch:U1|q[0]~0            ;    ;
; mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:cmp_ctl_1_2_|lpm_latch:U1|q[0]~0            ;    ;
; mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:cmp_ctl_1_1_|lpm_latch:U1|q[0]~0            ;    ;
; Number of buffers inserted to break combinational loops                                                                              ; 72 ;
+--------------------------------------------------------------------------------------------------------------------------------------+----+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 863   ;
; Number of registers using Synchronous Clear  ; 268   ;
; Number of registers using Synchronous Load   ; 32    ;
; Number of registers using Asynchronous Clear ; 1     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 352   ;
; Number of registers using Output Enable      ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+----------------------------------------------------------------+
; WYSIWYG Cells                                                  ;
+--------------------------------------------------------+-------+
; Statistic                                              ; Value ;
+--------------------------------------------------------+-------+
; Number of WYSIWYG cells                                ; 3548  ;
; Number of synthesis-generated cells                    ; 101   ;
; Number of WYSIWYG LUTs                                 ; 3262  ;
; Number of synthesis-generated LUTs                     ; 99    ;
; Number of WYSIWYG registers                            ; 859   ;
; Number of synthesis-generated registers                ; 4     ;
; Number of cells with combinational logic only          ; 2786  ;
; Number of cells with registers only                    ; 288   ;
; Number of cells with combinational logic and registers ; 575   ;
+--------------------------------------------------------+-------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                                                                                                                                                                                         ;
+----------------------------------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Compilation Hierarchy Node                                     ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name                                                                                                                                                                                                               ;
+----------------------------------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; |mips_top                                                      ; 3649 (3)    ; 863          ; 71680       ; 33   ; 0            ; 2786 (1)     ; 288 (2)           ; 575 (0)          ; 460 (0)         ; |mips_top                                                                                                                                                                                                                         ;
;    |mem_array:ram_8k|                                          ; 0 (0)       ; 0            ; 65536       ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mem_array:ram_8k                                                                                                                                                                                                        ;
;       |ram2048x8_0:ram0|                                       ; 0 (0)       ; 0            ; 16384       ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mem_array:ram_8k|ram2048x8_0:ram0                                                                                                                                                                                       ;
;          |altsyncram:altsyncram_component|                     ; 0 (0)       ; 0            ; 16384       ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mem_array:ram_8k|ram2048x8_0:ram0|altsyncram:altsyncram_component                                                                                                                                                       ;
;             |altsyncram_eht1:auto_generated|                   ; 0 (0)       ; 0            ; 16384       ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mem_array:ram_8k|ram2048x8_0:ram0|altsyncram:altsyncram_component|altsyncram_eht1:auto_generated                                                                                                                        ;
;       |ram2048x8_1:ram1|                                       ; 0 (0)       ; 0            ; 16384       ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mem_array:ram_8k|ram2048x8_1:ram1                                                                                                                                                                                       ;
;          |altsyncram:altsyncram_component|                     ; 0 (0)       ; 0            ; 16384       ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mem_array:ram_8k|ram2048x8_1:ram1|altsyncram:altsyncram_component                                                                                                                                                       ;
;             |altsyncram_fht1:auto_generated|                   ; 0 (0)       ; 0            ; 16384       ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mem_array:ram_8k|ram2048x8_1:ram1|altsyncram:altsyncram_component|altsyncram_fht1:auto_generated                                                                                                                        ;
;       |ram2048x8_2:ram2|                                       ; 0 (0)       ; 0            ; 16384       ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mem_array:ram_8k|ram2048x8_2:ram2                                                                                                                                                                                       ;
;          |altsyncram:altsyncram_component|                     ; 0 (0)       ; 0            ; 16384       ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mem_array:ram_8k|ram2048x8_2:ram2|altsyncram:altsyncram_component                                                                                                                                                       ;
;             |altsyncram_ght1:auto_generated|                   ; 0 (0)       ; 0            ; 16384       ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mem_array:ram_8k|ram2048x8_2:ram2|altsyncram:altsyncram_component|altsyncram_ght1:auto_generated                                                                                                                        ;
;       |ram2048x8_3:ram3|                                       ; 0 (0)       ; 0            ; 16384       ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mem_array:ram_8k|ram2048x8_3:ram3                                                                                                                                                                                       ;
;          |altsyncram:altsyncram_component|                     ; 0 (0)       ; 0            ; 16384       ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mem_array:ram_8k|ram2048x8_3:ram3|altsyncram:altsyncram_component                                                                                                                                                       ;
;             |altsyncram_hht1:auto_generated|                   ; 0 (0)       ; 0            ; 16384       ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mem_array:ram_8k|ram2048x8_3:ram3|altsyncram:altsyncram_component|altsyncram_hht1:auto_generated                                                                                                                        ;
;    |mips_sys:isys|                                             ; 3646 (44)   ; 861          ; 6144        ; 31   ; 0            ; 2785 (44)    ; 286 (0)           ; 575 (0)          ; 460 (0)         ; |mips_top|mips_sys:isys                                                                                                                                                                                                           ;
;       |mips_core:mips_core|                                    ; 3242 (31)   ; 604          ; 2048        ; 0    ; 0            ; 2638 (31)    ; 215 (0)           ; 389 (0)          ; 363 (0)         ; |mips_top|mips_sys:isys|mips_core:mips_core                                                                                                                                                                                       ;
;          |decode_pipe:decoder_pipe|                            ; 277 (0)     ; 52           ; 0           ; 0    ; 0            ; 225 (0)      ; 50 (0)            ; 2 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe                                                                                                                                                              ;
;             |decoder:idecoder|                                 ; 225 (184)   ; 0            ; 0           ; 0    ; 0            ; 225 (184)    ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder                                                                                                                                             ;
;                |SYNLPM_LATR1:alu_func_1_0_|                    ; 1 (0)       ; 0            ; 0           ; 0    ; 0            ; 1 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:alu_func_1_0_                                                                                                                  ;
;                   |lpm_latch:U1|                               ; 1 (1)       ; 0            ; 0           ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:alu_func_1_0_|lpm_latch:U1                                                                                                     ;
;                |SYNLPM_LATR1:alu_func_1_1_|                    ; 1 (0)       ; 0            ; 0           ; 0    ; 0            ; 1 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:alu_func_1_1_                                                                                                                  ;
;                   |lpm_latch:U1|                               ; 1 (1)       ; 0            ; 0           ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:alu_func_1_1_|lpm_latch:U1                                                                                                     ;
;                |SYNLPM_LATR1:alu_func_1_4_|                    ; 1 (0)       ; 0            ; 0           ; 0    ; 0            ; 1 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:alu_func_1_4_                                                                                                                  ;
;                   |lpm_latch:U1|                               ; 1 (1)       ; 0            ; 0           ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:alu_func_1_4_|lpm_latch:U1                                                                                                     ;
;                |SYNLPM_LATR1:alu_we_0_|                        ; 1 (0)       ; 0            ; 0           ; 0    ; 0            ; 1 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:alu_we_0_                                                                                                                      ;
;                   |lpm_latch:U1|                               ; 1 (1)       ; 0            ; 0           ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:alu_we_0_|lpm_latch:U1                                                                                                         ;
;                |SYNLPM_LATR1:cmp_ctl_1_0_|                     ; 1 (0)       ; 0            ; 0           ; 0    ; 0            ; 1 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:cmp_ctl_1_0_                                                                                                                   ;
;                   |lpm_latch:U1|                               ; 1 (1)       ; 0            ; 0           ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:cmp_ctl_1_0_|lpm_latch:U1                                                                                                      ;
;                |SYNLPM_LATR1:cmp_ctl_1_1_|                     ; 1 (0)       ; 0            ; 0           ; 0    ; 0            ; 1 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:cmp_ctl_1_1_                                                                                                                   ;
;                   |lpm_latch:U1|                               ; 1 (1)       ; 0            ; 0           ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:cmp_ctl_1_1_|lpm_latch:U1                                                                                                      ;
;                |SYNLPM_LATR1:cmp_ctl_1_2_|                     ; 1 (0)       ; 0            ; 0           ; 0    ; 0            ; 1 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:cmp_ctl_1_2_                                                                                                                   ;
;                   |lpm_latch:U1|                               ; 1 (1)       ; 0            ; 0           ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:cmp_ctl_1_2_|lpm_latch:U1                                                                                                      ;
;                |SYNLPM_LATR1:dmem_ctl_1_3_|                    ; 1 (0)       ; 0            ; 0           ; 0    ; 0            ; 1 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:dmem_ctl_1_3_                                                                                                                  ;
;                   |lpm_latch:U1|                               ; 1 (1)       ; 0            ; 0           ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:dmem_ctl_1_3_|lpm_latch:U1                                                                                                     ;
;                |SYNLPM_LATR1:ext_ctl_1_1_|                     ; 1 (0)       ; 0            ; 0           ; 0    ; 0            ; 1 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:ext_ctl_1_1_                                                                                                                   ;
;                   |lpm_latch:U1|                               ; 1 (1)       ; 0            ; 0           ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:ext_ctl_1_1_|lpm_latch:U1                                                                                                      ;
;                |SYNLPM_LATR1:ext_ctl_1_2_|                     ; 1 (0)       ; 0            ; 0           ; 0    ; 0            ; 1 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:ext_ctl_1_2_                                                                                                                   ;
;                   |lpm_latch:U1|                               ; 1 (1)       ; 0            ; 0           ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:ext_ctl_1_2_|lpm_latch:U1                                                                                                      ;
;                |SYNLPM_LATR1:fsm_dly_1_0_|                     ; 1 (0)       ; 0            ; 0           ; 0    ; 0            ; 1 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:fsm_dly_1_0_                                                                                                                   ;
;                   |lpm_latch:U1|                               ; 1 (1)       ; 0            ; 0           ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:fsm_dly_1_0_|lpm_latch:U1                                                                                                      ;
;                |SYNLPM_LATR1:fsm_dly_1_1__Z|                   ; 1 (0)       ; 0            ; 0           ; 0    ; 0            ; 1 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:fsm_dly_1_1__Z                                                                                                                 ;
;                   |lpm_latch:U1|                               ; 1 (1)       ; 0            ; 0           ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:fsm_dly_1_1__Z|lpm_latch:U1                                                                                                    ;
;                |SYNLPM_LATR1:fsm_dly_1_2__Z|                   ; 1 (0)       ; 0            ; 0           ; 0    ; 0            ; 1 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:fsm_dly_1_2__Z                                                                                                                 ;
;                   |lpm_latch:U1|                               ; 1 (1)       ; 0            ; 0           ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:fsm_dly_1_2__Z|lpm_latch:U1                                                                                                    ;
;                |SYNLPM_LATR1:muxa_ctl_1_0_|                    ; 1 (0)       ; 0            ; 0           ; 0    ; 0            ; 1 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:muxa_ctl_1_0_                                                                                                                  ;
;                   |lpm_latch:U1|                               ; 1 (1)       ; 0            ; 0           ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:muxa_ctl_1_0_|lpm_latch:U1                                                                                                     ;
;                |SYNLPM_LATR1:muxb_ctl_1_0_|                    ; 1 (0)       ; 0            ; 0           ; 0    ; 0            ; 1 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:muxb_ctl_1_0_                                                                                                                  ;
;                   |lpm_latch:U1|                               ; 1 (1)       ; 0            ; 0           ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:muxb_ctl_1_0_|lpm_latch:U1                                                                                                     ;
;                |SYNLPM_LATR1:pc_gen_ctl_1_1_|                  ; 1 (0)       ; 0            ; 0           ; 0    ; 0            ; 1 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:pc_gen_ctl_1_1_                                                                                                                ;
;                   |lpm_latch:U1|                               ; 1 (1)       ; 0            ; 0           ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:pc_gen_ctl_1_1_|lpm_latch:U1                                                                                                   ;
;                |SYNLPM_LATR1:rd_sel_1_0_|                      ; 1 (0)       ; 0            ; 0           ; 0    ; 0            ; 1 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:rd_sel_1_0_                                                                                                                    ;
;                   |lpm_latch:U1|                               ; 1 (1)       ; 0            ; 0           ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:rd_sel_1_0_|lpm_latch:U1                                                                                                       ;
;                |SYNLPM_LATR1:wb_mux_0_|                        ; 1 (0)       ; 0            ; 0           ; 0    ; 0            ; 1 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:wb_mux_0_                                                                                                                      ;
;                   |lpm_latch:U1|                               ; 1 (1)       ; 0            ; 0           ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:wb_mux_0_|lpm_latch:U1                                                                                                         ;
;                |SYNLPM_LATR1:wb_we_0_|                         ; 1 (0)       ; 0            ; 0           ; 0    ; 0            ; 1 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:wb_we_0_                                                                                                                       ;
;                   |lpm_latch:U1|                               ; 1 (1)       ; 0            ; 0           ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:wb_we_0_|lpm_latch:U1                                                                                                          ;
;                |SYNLPM_LATRS1:alu_func_1_2_|                   ; 2 (0)       ; 0            ; 0           ; 0    ; 0            ; 2 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:alu_func_1_2_                                                                                                                 ;
;                   |lpm_latch:U1|                               ; 2 (2)       ; 0            ; 0           ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:alu_func_1_2_|lpm_latch:U1                                                                                                    ;
;                |SYNLPM_LATRS1:alu_func_1_3_|                   ; 2 (0)       ; 0            ; 0           ; 0    ; 0            ; 2 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:alu_func_1_3_                                                                                                                 ;
;                   |lpm_latch:U1|                               ; 2 (2)       ; 0            ; 0           ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:alu_func_1_3_|lpm_latch:U1                                                                                                    ;
;                |SYNLPM_LATRS1:dmem_ctl_1_0_|                   ; 2 (0)       ; 0            ; 0           ; 0    ; 0            ; 2 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:dmem_ctl_1_0_                                                                                                                 ;
;                   |lpm_latch:U1|                               ; 2 (2)       ; 0            ; 0           ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:dmem_ctl_1_0_|lpm_latch:U1                                                                                                    ;
;                |SYNLPM_LATRS1:dmem_ctl_1_1_|                   ; 2 (0)       ; 0            ; 0           ; 0    ; 0            ; 2 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:dmem_ctl_1_1_                                                                                                                 ;
;                   |lpm_latch:U1|                               ; 2 (2)       ; 0            ; 0           ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:dmem_ctl_1_1_|lpm_latch:U1                                                                                                    ;
;                |SYNLPM_LATRS1:dmem_ctl_1_2_|                   ; 2 (0)       ; 0            ; 0           ; 0    ; 0            ; 2 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:dmem_ctl_1_2_                                                                                                                 ;
;                   |lpm_latch:U1|                               ; 2 (2)       ; 0            ; 0           ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:dmem_ctl_1_2_|lpm_latch:U1                                                                                                    ;
;                |SYNLPM_LATRS1:ext_ctl_1_0_|                    ; 2 (0)       ; 0            ; 0           ; 0    ; 0            ; 2 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:ext_ctl_1_0_                                                                                                                  ;
;                   |lpm_latch:U1|                               ; 2 (2)       ; 0            ; 0           ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:ext_ctl_1_0_|lpm_latch:U1                                                                                                     ;
;                |SYNLPM_LATRS1:muxa_ctl_1_1_|                   ; 2 (0)       ; 0            ; 0           ; 0    ; 0            ; 2 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:muxa_ctl_1_1_                                                                                                                 ;
;                   |lpm_latch:U1|                               ; 2 (2)       ; 0            ; 0           ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:muxa_ctl_1_1_|lpm_latch:U1                                                                                                    ;
;                |SYNLPM_LATRS1:muxb_ctl_1_1_|                   ; 2 (0)       ; 0            ; 0           ; 0    ; 0            ; 2 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:muxb_ctl_1_1_                                                                                                                 ;
;                   |lpm_latch:U1|                               ; 2 (2)       ; 0            ; 0           ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:muxb_ctl_1_1_|lpm_latch:U1                                                                                                    ;
;                |SYNLPM_LATRS1:pc_gen_ctl_1_0_|                 ; 2 (0)       ; 0            ; 0           ; 0    ; 0            ; 2 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:pc_gen_ctl_1_0_                                                                                                               ;
;                   |lpm_latch:U1|                               ; 2 (2)       ; 0            ; 0           ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:pc_gen_ctl_1_0_|lpm_latch:U1                                                                                                  ;
;                |SYNLPM_LATRS1:pc_gen_ctl_1_2_|                 ; 2 (0)       ; 0            ; 0           ; 0    ; 0            ; 2 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:pc_gen_ctl_1_2_                                                                                                               ;
;                   |lpm_latch:U1|                               ; 2 (2)       ; 0            ; 0           ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:pc_gen_ctl_1_2_|lpm_latch:U1                                                                                                  ;
;                |SYNLPM_LATRS1:rd_sel_1_1_|                     ; 2 (0)       ; 0            ; 0           ; 0    ; 0            ; 2 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:rd_sel_1_1_                                                                                                                   ;
;                   |lpm_latch:U1|                               ; 2 (2)       ; 0            ; 0           ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:rd_sel_1_1_|lpm_latch:U1                                                                                                      ;
;             |pipelinedregs:pipereg|                            ; 52 (0)      ; 52           ; 0           ; 0    ; 0            ; 0 (0)        ; 50 (0)            ; 2 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg                                                                                                                                        ;
;                |alu_func_reg_clr:U16|                          ; 5 (5)       ; 5            ; 0           ; 0    ; 0            ; 0 (0)        ; 5 (5)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|alu_func_reg_clr:U16                                                                                                                   ;
;                |alu_func_reg_clr_cls:U26|                      ; 5 (5)       ; 5            ; 0           ; 0    ; 0            ; 0 (0)        ; 5 (5)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|alu_func_reg_clr_cls:U26                                                                                                               ;
;                |alu_we_reg_clr:U24|                            ; 1 (1)       ; 1            ; 0           ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|alu_we_reg_clr:U24                                                                                                                     ;
;                |alu_we_reg_clr_cls:U6|                         ; 1 (1)       ; 1            ; 0           ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|alu_we_reg_clr_cls:U6                                                                                                                  ;
;                |cmp_ctl_reg_clr_cls:U2|                        ; 3 (3)       ; 3            ; 0           ; 0    ; 0            ; 0 (0)        ; 3 (3)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|cmp_ctl_reg_clr_cls:U2                                                                                                                 ;
;                |dmem_ctl_reg:U9|                               ; 4 (4)       ; 4            ; 0           ; 0    ; 0            ; 0 (0)        ; 3 (3)             ; 1 (1)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|dmem_ctl_reg:U9                                                                                                                        ;
;                |dmem_ctl_reg_clr:U15|                          ; 4 (4)       ; 4            ; 0           ; 0    ; 0            ; 0 (0)        ; 4 (4)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|dmem_ctl_reg_clr:U15                                                                                                                   ;
;                |dmem_ctl_reg_clr_cls:U3|                       ; 4 (4)       ; 4            ; 0           ; 0    ; 0            ; 0 (0)        ; 4 (4)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|dmem_ctl_reg_clr_cls:U3                                                                                                                ;
;                |ext_ctl_reg_clr_cls:U4|                        ; 3 (3)       ; 3            ; 0           ; 0    ; 0            ; 0 (0)        ; 3 (3)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|ext_ctl_reg_clr_cls:U4                                                                                                                 ;
;                |muxa_ctl_reg_clr:U17|                          ; 2 (2)       ; 2            ; 0           ; 0    ; 0            ; 0 (0)        ; 2 (2)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|muxa_ctl_reg_clr:U17                                                                                                                   ;
;                |muxa_ctl_reg_clr_cls:U7|                       ; 2 (2)       ; 2            ; 0           ; 0    ; 0            ; 0 (0)        ; 2 (2)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|muxa_ctl_reg_clr_cls:U7                                                                                                                ;
;                |muxb_ctl_reg_clr:U14|                          ; 2 (2)       ; 2            ; 0           ; 0    ; 0            ; 0 (0)        ; 2 (2)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|muxb_ctl_reg_clr:U14                                                                                                                   ;
;                |muxb_ctl_reg_clr_cls:U1|                       ; 2 (2)       ; 2            ; 0           ; 0    ; 0            ; 0 (0)        ; 2 (2)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|muxb_ctl_reg_clr_cls:U1                                                                                                                ;
;                |pc_gen_ctl_reg_clr_cls:U8|                     ; 3 (3)       ; 3            ; 0           ; 0    ; 0            ; 0 (0)        ; 3 (3)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|pc_gen_ctl_reg_clr_cls:U8                                                                                                              ;
;                |rd_sel_reg_clr_cls:U5|                         ; 2 (2)       ; 2            ; 0           ; 0    ; 0            ; 0 (0)        ; 2 (2)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|rd_sel_reg_clr_cls:U5                                                                                                                  ;
;                |wb_mux_ctl_reg:U18|                            ; 1 (1)       ; 1            ; 0           ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|wb_mux_ctl_reg:U18                                                                                                                     ;
;                |wb_mux_ctl_reg_1:U21|                          ; 1 (1)       ; 1            ; 0           ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|wb_mux_ctl_reg_1:U21                                                                                                                   ;
;                |wb_mux_ctl_reg_clr:U13|                        ; 1 (1)       ; 1            ; 0           ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|wb_mux_ctl_reg_clr:U13                                                                                                                 ;
;                |wb_mux_ctl_reg_clr_cls:U10|                    ; 1 (1)       ; 1            ; 0           ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|wb_mux_ctl_reg_clr_cls:U10                                                                                                             ;
;                |wb_we_reg:U12|                                 ; 1 (1)       ; 1            ; 0           ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 1 (1)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|wb_we_reg:U12                                                                                                                          ;
;                |wb_we_reg_1:U20|                               ; 1 (1)       ; 1            ; 0           ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|wb_we_reg_1:U20                                                                                                                        ;
;                |wb_we_reg_2:U22|                               ; 1 (1)       ; 1            ; 0           ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|wb_we_reg_2:U22                                                                                                                        ;
;                |wb_we_reg_clr:U19|                             ; 1 (1)       ; 1            ; 0           ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|wb_we_reg_clr:U19                                                                                                                      ;
;                |wb_we_reg_clr_cls:U11|                         ; 1 (1)       ; 1            ; 0           ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|wb_we_reg_clr_cls:U11                                                                                                                  ;
;          |exec_stage:iexec_stage|                              ; 1982 (1)    ; 179          ; 0           ; 0    ; 0            ; 1803 (1)     ; 34 (0)            ; 145 (0)          ; 331 (1)         ; |mips_top|mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage                                                                                                                                                                ;
;             |alu_muxa:i_alu_muxa|                              ; 162 (162)   ; 0            ; 0           ; 0    ; 0            ; 162 (162)    ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa                                                                                                                                            ;
;             |alu_muxb:i_alu_muxb|                              ; 6 (6)       ; 0            ; 0           ; 0    ; 0            ; 6 (6)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxb:i_alu_muxb                                                                                                                                            ;
;             |big_alu:MIPS_alu|                                 ; 1716 (95)   ; 115          ; 0           ; 0    ; 0            ; 1601 (95)    ; 1 (0)             ; 114 (0)          ; 301 (0)         ; |mips_top|mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu                                                                                                                                               ;
;                |alu:mips_alu|                                  ; 242 (242)   ; 0            ; 0           ; 0    ; 0            ; 242 (242)    ; 0 (0)             ; 0 (0)            ; 98 (98)         ; |mips_top|mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu                                                                                                                                  ;
;                |muldiv_ff:muldiv_ff|                           ; 769 (769)   ; 115          ; 0           ; 0    ; 0            ; 654 (654)    ; 1 (1)             ; 114 (114)        ; 203 (203)       ; |mips_top|mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff                                                                                                                           ;
;                |shifter_tak:mips_shifter|                      ; 610 (610)   ; 0            ; 0           ; 0    ; 0            ; 610 (610)    ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter                                                                                                                      ;
;             |fwd_mux_2:dmem_fw_mux|                            ; 33 (33)     ; 0            ; 0           ; 0    ; 0            ; 33 (33)      ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|fwd_mux_2:dmem_fw_mux                                                                                                                                          ;
;             |r32_reg:pc_nxt|                                   ; 32 (32)     ; 32           ; 0           ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 31 (31)          ; 29 (29)         ; |mips_top|mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt                                                                                                                                                 ;
;             |r32_reg_cls:spc|                                  ; 32 (32)     ; 32           ; 0           ; 0    ; 0            ; 0 (0)        ; 32 (32)           ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg_cls:spc                                                                                                                                                ;
;          |forward:iforward|                                    ; 43 (0)      ; 10           ; 0           ; 0    ; 0            ; 33 (0)       ; 10 (0)            ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|forward:iforward                                                                                                                                                                      ;
;             |forward_node_fw_alu_rs:fw_alu_rs|                 ; 10 (10)     ; 0            ; 0           ; 0    ; 0            ; 10 (10)      ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|forward:iforward|forward_node_fw_alu_rs:fw_alu_rs                                                                                                                                     ;
;             |forward_node_fw_alu_rs_1:fw_alu_rt|               ; 8 (8)       ; 0            ; 0           ; 0    ; 0            ; 8 (8)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|forward:iforward|forward_node_fw_alu_rs_1:fw_alu_rt                                                                                                                                   ;
;             |forward_node_fw_alu_rs_2:fw_cmp_rs|               ; 7 (7)       ; 0            ; 0           ; 0    ; 0            ; 7 (7)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|forward:iforward|forward_node_fw_alu_rs_2:fw_cmp_rs                                                                                                                                   ;
;             |forward_node_fw_alu_rs_3:fw_cmp_rt|               ; 8 (8)       ; 0            ; 0           ; 0    ; 0            ; 8 (8)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|forward:iforward|forward_node_fw_alu_rs_3:fw_cmp_rt                                                                                                                                   ;
;             |fw_latch5:fw_reg_rns|                             ; 5 (5)       ; 5            ; 0           ; 0    ; 0            ; 0 (0)        ; 5 (5)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|forward:iforward|fw_latch5:fw_reg_rns                                                                                                                                                 ;
;             |fw_latch5_1:fw_reg_rnt|                           ; 5 (5)       ; 5            ; 0           ; 0    ; 0            ; 0 (0)        ; 5 (5)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|forward:iforward|fw_latch5_1:fw_reg_rnt                                                                                                                                               ;
;          |mem_module:MEM_CTL|                                  ; 176 (0)     ; 6            ; 0           ; 0    ; 0            ; 170 (0)      ; 0 (0)             ; 6 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL                                                                                                                                                                    ;
;             |infile_dmem_ctl_reg:dmem_ctl_post|                ; 6 (6)       ; 6            ; 0           ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 6 (6)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|infile_dmem_ctl_reg:dmem_ctl_post                                                                                                                                  ;
;             |mem_addr_ctl:i_mem_addr_ctl|                      ; 14 (6)      ; 0            ; 0           ; 0    ; 0            ; 14 (6)       ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_addr_ctl:i_mem_addr_ctl                                                                                                                                        ;
;                |SYNLPM_LATRS1:wr_en_1_0_|                      ; 2 (0)       ; 0            ; 0           ; 0    ; 0            ; 2 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_addr_ctl:i_mem_addr_ctl|SYNLPM_LATRS1:wr_en_1_0_                                                                                                               ;
;                   |lpm_latch:U1|                               ; 2 (2)       ; 0            ; 0           ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_addr_ctl:i_mem_addr_ctl|SYNLPM_LATRS1:wr_en_1_0_|lpm_latch:U1                                                                                                  ;
;                |SYNLPM_LATRS1:wr_en_1_1_|                      ; 2 (0)       ; 0            ; 0           ; 0    ; 0            ; 2 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_addr_ctl:i_mem_addr_ctl|SYNLPM_LATRS1:wr_en_1_1_                                                                                                               ;
;                   |lpm_latch:U1|                               ; 2 (2)       ; 0            ; 0           ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_addr_ctl:i_mem_addr_ctl|SYNLPM_LATRS1:wr_en_1_1_|lpm_latch:U1                                                                                                  ;
;                |SYNLPM_LATRS1:wr_en_1_2_|                      ; 2 (0)       ; 0            ; 0           ; 0    ; 0            ; 2 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_addr_ctl:i_mem_addr_ctl|SYNLPM_LATRS1:wr_en_1_2_                                                                                                               ;
;                   |lpm_latch:U1|                               ; 2 (2)       ; 0            ; 0           ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_addr_ctl:i_mem_addr_ctl|SYNLPM_LATRS1:wr_en_1_2_|lpm_latch:U1                                                                                                  ;
;                |SYNLPM_LATRS1:wr_en_1_3_|                      ; 2 (0)       ; 0            ; 0           ; 0    ; 0            ; 2 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_addr_ctl:i_mem_addr_ctl|SYNLPM_LATRS1:wr_en_1_3_                                                                                                               ;
;                   |lpm_latch:U1|                               ; 2 (2)       ; 0            ; 0           ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_addr_ctl:i_mem_addr_ctl|SYNLPM_LATRS1:wr_en_1_3_|lpm_latch:U1                                                                                                  ;
;             |mem_din_ctl:i_mem_din_ctl|                        ; 34 (34)     ; 0            ; 0           ; 0    ; 0            ; 34 (34)      ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_din_ctl:i_mem_din_ctl                                                                                                                                          ;
;             |mem_dout_ctl:i_mem_dout_ctl|                      ; 122 (90)    ; 0            ; 0           ; 0    ; 0            ; 122 (90)     ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl                                                                                                                                        ;
;                |SYNLPM_LATR1:dout_1_0__Z|                      ; 1 (0)       ; 0            ; 0           ; 0    ; 0            ; 1 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_0__Z                                                                                                               ;
;                   |lpm_latch:U1|                               ; 1 (1)       ; 0            ; 0           ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_0__Z|lpm_latch:U1                                                                                                  ;
;                |SYNLPM_LATR1:dout_1_10__Z|                     ; 1 (0)       ; 0            ; 0           ; 0    ; 0            ; 1 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_10__Z                                                                                                              ;
;                   |lpm_latch:U1|                               ; 1 (1)       ; 0            ; 0           ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_10__Z|lpm_latch:U1                                                                                                 ;
;                |SYNLPM_LATR1:dout_1_11__Z|                     ; 1 (0)       ; 0            ; 0           ; 0    ; 0            ; 1 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_11__Z                                                                                                              ;
;                   |lpm_latch:U1|                               ; 1 (1)       ; 0            ; 0           ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_11__Z|lpm_latch:U1                                                                                                 ;
;                |SYNLPM_LATR1:dout_1_12__Z|                     ; 1 (0)       ; 0            ; 0           ; 0    ; 0            ; 1 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_12__Z                                                                                                              ;
;                   |lpm_latch:U1|                               ; 1 (1)       ; 0            ; 0           ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_12__Z|lpm_latch:U1                                                                                                 ;
;                |SYNLPM_LATR1:dout_1_13__Z|                     ; 1 (0)       ; 0            ; 0           ; 0    ; 0            ; 1 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_13__Z                                                                                                              ;
;                   |lpm_latch:U1|                               ; 1 (1)       ; 0            ; 0           ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_13__Z|lpm_latch:U1                                                                                                 ;
;                |SYNLPM_LATR1:dout_1_14__Z|                     ; 1 (0)       ; 0            ; 0           ; 0    ; 0            ; 1 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_14__Z                                                                                                              ;
;                   |lpm_latch:U1|                               ; 1 (1)       ; 0            ; 0           ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_14__Z|lpm_latch:U1                                                                                                 ;
;                |SYNLPM_LATR1:dout_1_15__Z|                     ; 1 (0)       ; 0            ; 0           ; 0    ; 0            ; 1 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_15__Z                                                                                                              ;
;                   |lpm_latch:U1|                               ; 1 (1)       ; 0            ; 0           ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_15__Z|lpm_latch:U1                                                                                                 ;
;                |SYNLPM_LATR1:dout_1_16__Z|                     ; 1 (0)       ; 0            ; 0           ; 0    ; 0            ; 1 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_16__Z                                                                                                              ;
;                   |lpm_latch:U1|                               ; 1 (1)       ; 0            ; 0           ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_16__Z|lpm_latch:U1                                                                                                 ;
;                |SYNLPM_LATR1:dout_1_17__Z|                     ; 1 (0)       ; 0            ; 0           ; 0    ; 0            ; 1 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_17__Z                                                                                                              ;
;                   |lpm_latch:U1|                               ; 1 (1)       ; 0            ; 0           ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_17__Z|lpm_latch:U1                                                                                                 ;
;                |SYNLPM_LATR1:dout_1_18__Z|                     ; 1 (0)       ; 0            ; 0           ; 0    ; 0            ; 1 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_18__Z                                                                                                              ;
;                   |lpm_latch:U1|                               ; 1 (1)       ; 0            ; 0           ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_18__Z|lpm_latch:U1                                                                                                 ;
;                |SYNLPM_LATR1:dout_1_19__Z|                     ; 1 (0)       ; 0            ; 0           ; 0    ; 0            ; 1 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_19__Z                                                                                                              ;
;                   |lpm_latch:U1|                               ; 1 (1)       ; 0            ; 0           ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_19__Z|lpm_latch:U1                                                                                                 ;
;                |SYNLPM_LATR1:dout_1_1__Z|                      ; 1 (0)       ; 0            ; 0           ; 0    ; 0            ; 1 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_1__Z                                                                                                               ;
;                   |lpm_latch:U1|                               ; 1 (1)       ; 0            ; 0           ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_1__Z|lpm_latch:U1                                                                                                  ;
;                |SYNLPM_LATR1:dout_1_20__Z|                     ; 1 (0)       ; 0            ; 0           ; 0    ; 0            ; 1 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_20__Z                                                                                                              ;
;                   |lpm_latch:U1|                               ; 1 (1)       ; 0            ; 0           ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_20__Z|lpm_latch:U1                                                                                                 ;
;                |SYNLPM_LATR1:dout_1_21__Z|                     ; 1 (0)       ; 0            ; 0           ; 0    ; 0            ; 1 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_21__Z                                                                                                              ;
;                   |lpm_latch:U1|                               ; 1 (1)       ; 0            ; 0           ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_21__Z|lpm_latch:U1                                                                                                 ;
;                |SYNLPM_LATR1:dout_1_22__Z|                     ; 1 (0)       ; 0            ; 0           ; 0    ; 0            ; 1 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_22__Z                                                                                                              ;
;                   |lpm_latch:U1|                               ; 1 (1)       ; 0            ; 0           ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_22__Z|lpm_latch:U1                                                                                                 ;
;                |SYNLPM_LATR1:dout_1_23__Z|                     ; 1 (0)       ; 0            ; 0           ; 0    ; 0            ; 1 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_23__Z                                                                                                              ;
;                   |lpm_latch:U1|                               ; 1 (1)       ; 0            ; 0           ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_23__Z|lpm_latch:U1                                                                                                 ;
;                |SYNLPM_LATR1:dout_1_24__Z|                     ; 1 (0)       ; 0            ; 0           ; 0    ; 0            ; 1 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_24__Z                                                                                                              ;
;                   |lpm_latch:U1|                               ; 1 (1)       ; 0            ; 0           ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_24__Z|lpm_latch:U1                                                                                                 ;
;                |SYNLPM_LATR1:dout_1_25__Z|                     ; 1 (0)       ; 0            ; 0           ; 0    ; 0            ; 1 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_25__Z                                                                                                              ;
;                   |lpm_latch:U1|                               ; 1 (1)       ; 0            ; 0           ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_25__Z|lpm_latch:U1                                                                                                 ;
;                |SYNLPM_LATR1:dout_1_26__Z|                     ; 1 (0)       ; 0            ; 0           ; 0    ; 0            ; 1 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_26__Z                                                                                                              ;
;                   |lpm_latch:U1|                               ; 1 (1)       ; 0            ; 0           ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_26__Z|lpm_latch:U1                                                                                                 ;
;                |SYNLPM_LATR1:dout_1_27__Z|                     ; 1 (0)       ; 0            ; 0           ; 0    ; 0            ; 1 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_27__Z                                                                                                              ;
;                   |lpm_latch:U1|                               ; 1 (1)       ; 0            ; 0           ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_27__Z|lpm_latch:U1                                                                                                 ;
;                |SYNLPM_LATR1:dout_1_28__Z|                     ; 1 (0)       ; 0            ; 0           ; 0    ; 0            ; 1 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_28__Z                                                                                                              ;
;                   |lpm_latch:U1|                               ; 1 (1)       ; 0            ; 0           ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_28__Z|lpm_latch:U1                                                                                                 ;
;                |SYNLPM_LATR1:dout_1_29__Z|                     ; 1 (0)       ; 0            ; 0           ; 0    ; 0            ; 1 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_29__Z                                                                                                              ;
;                   |lpm_latch:U1|                               ; 1 (1)       ; 0            ; 0           ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_29__Z|lpm_latch:U1                                                                                                 ;
;                |SYNLPM_LATR1:dout_1_2__Z|                      ; 1 (0)       ; 0            ; 0           ; 0    ; 0            ; 1 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_2__Z                                                                                                               ;
;                   |lpm_latch:U1|                               ; 1 (1)       ; 0            ; 0           ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_2__Z|lpm_latch:U1                                                                                                  ;
;                |SYNLPM_LATR1:dout_1_30__Z|                     ; 1 (0)       ; 0            ; 0           ; 0    ; 0            ; 1 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_30__Z                                                                                                              ;
;                   |lpm_latch:U1|                               ; 1 (1)       ; 0            ; 0           ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_30__Z|lpm_latch:U1                                                                                                 ;
;                |SYNLPM_LATR1:dout_1_31__Z|                     ; 1 (0)       ; 0            ; 0           ; 0    ; 0            ; 1 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_31__Z                                                                                                              ;
;                   |lpm_latch:U1|                               ; 1 (1)       ; 0            ; 0           ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_31__Z|lpm_latch:U1                                                                                                 ;
;                |SYNLPM_LATR1:dout_1_3__Z|                      ; 1 (0)       ; 0            ; 0           ; 0    ; 0            ; 1 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_3__Z                                                                                                               ;
;                   |lpm_latch:U1|                               ; 1 (1)       ; 0            ; 0           ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_3__Z|lpm_latch:U1                                                                                                  ;
;                |SYNLPM_LATR1:dout_1_4__Z|                      ; 1 (0)       ; 0            ; 0           ; 0    ; 0            ; 1 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_4__Z                                                                                                               ;
;                   |lpm_latch:U1|                               ; 1 (1)       ; 0            ; 0           ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_4__Z|lpm_latch:U1                                                                                                  ;
;                |SYNLPM_LATR1:dout_1_5__Z|                      ; 1 (0)       ; 0            ; 0           ; 0    ; 0            ; 1 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_5__Z                                                                                                               ;
;                   |lpm_latch:U1|                               ; 1 (1)       ; 0            ; 0           ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_5__Z|lpm_latch:U1                                                                                                  ;
;                |SYNLPM_LATR1:dout_1_6__Z|                      ; 1 (0)       ; 0            ; 0           ; 0    ; 0            ; 1 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_6__Z                                                                                                               ;
;                   |lpm_latch:U1|                               ; 1 (1)       ; 0            ; 0           ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_6__Z|lpm_latch:U1                                                                                                  ;
;                |SYNLPM_LATR1:dout_1_7__Z|                      ; 1 (0)       ; 0            ; 0           ; 0    ; 0            ; 1 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_7__Z                                                                                                               ;
;                   |lpm_latch:U1|                               ; 1 (1)       ; 0            ; 0           ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_7__Z|lpm_latch:U1                                                                                                  ;
;                |SYNLPM_LATR1:dout_1_8__Z|                      ; 1 (0)       ; 0            ; 0           ; 0    ; 0            ; 1 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_8__Z                                                                                                               ;
;                   |lpm_latch:U1|                               ; 1 (1)       ; 0            ; 0           ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_8__Z|lpm_latch:U1                                                                                                  ;
;                |SYNLPM_LATR1:dout_1_9__Z|                      ; 1 (0)       ; 0            ; 0           ; 0    ; 0            ; 1 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_9__Z                                                                                                               ;
;                   |lpm_latch:U1|                               ; 1 (1)       ; 0            ; 0           ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_9__Z|lpm_latch:U1                                                                                                  ;
;          |r32_reg_1:alu_pass0|                                 ; 30 (30)     ; 30           ; 0           ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 30 (30)          ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|r32_reg_1:alu_pass0                                                                                                                                                                   ;
;          |r32_reg_2:alu_pass1|                                 ; 32 (32)     ; 32           ; 0           ; 0    ; 0            ; 0 (0)        ; 32 (32)           ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|r32_reg_2:alu_pass1                                                                                                                                                                   ;
;          |r32_reg_3:cop_data_reg|                              ; 32 (32)     ; 32           ; 0           ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 32 (32)          ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg                                                                                                                                                                ;
;          |r32_reg_4:cop_dout_reg|                              ; 32 (32)     ; 32           ; 0           ; 0    ; 0            ; 0 (0)        ; 32 (32)           ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|r32_reg_4:cop_dout_reg                                                                                                                                                                ;
;          |r32_reg_5:ext_reg|                                   ; 32 (32)     ; 32           ; 0           ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 32 (32)          ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg                                                                                                                                                                     ;
;          |r32_reg_6:pc|                                        ; 32 (32)     ; 32           ; 0           ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 32 (32)          ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|r32_reg_6:pc                                                                                                                                                                          ;
;          |r32_reg_7:rs_reg|                                    ; 32 (32)     ; 32           ; 0           ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 32 (32)          ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg                                                                                                                                                                      ;
;          |r32_reg_8:rt_reg|                                    ; 32 (32)     ; 32           ; 0           ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 32 (32)          ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg                                                                                                                                                                      ;
;          |r5_reg:rnd_pass0|                                    ; 5 (5)       ; 5            ; 0           ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 5 (5)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|r5_reg:rnd_pass0                                                                                                                                                                      ;
;          |r5_reg_1:rnd_pass1|                                  ; 5 (5)       ; 5            ; 0           ; 0    ; 0            ; 0 (0)        ; 5 (5)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|r5_reg_1:rnd_pass1                                                                                                                                                                    ;
;          |r5_reg_2:rnd_pass2|                                  ; 5 (5)       ; 5            ; 0           ; 0    ; 0            ; 0 (0)        ; 5 (5)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|r5_reg_2:rnd_pass2                                                                                                                                                                    ;
;          |rf_stage:iRF_stage|                                  ; 464 (0)     ; 88           ; 2048        ; 0    ; 0            ; 376 (0)      ; 47 (0)            ; 41 (0)           ; 32 (0)          ; |mips_top|mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage                                                                                                                                                                    ;
;             |compare:i_cmp|                                    ; 37 (37)     ; 0            ; 0           ; 0    ; 0            ; 37 (37)      ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|compare:i_cmp                                                                                                                                                      ;
;             |ctl_FSM:MIAN_FSM|                                 ; 39 (33)     ; 14           ; 0           ; 0    ; 0            ; 25 (19)      ; 5 (5)             ; 9 (9)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM                                                                                                                                                   ;
;                |SYNLPM_LATR1:next_delay_counter_Sreg0_0_|      ; 1 (0)       ; 0            ; 0           ; 0    ; 0            ; 1 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|SYNLPM_LATR1:next_delay_counter_Sreg0_0_                                                                                                          ;
;                   |lpm_latch:U1|                               ; 1 (1)       ; 0            ; 0           ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|SYNLPM_LATR1:next_delay_counter_Sreg0_0_|lpm_latch:U1                                                                                             ;
;                |SYNLPM_LATR1:next_delay_counter_Sreg0_2__Z|    ; 1 (0)       ; 0            ; 0           ; 0    ; 0            ; 1 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|SYNLPM_LATR1:next_delay_counter_Sreg0_2__Z                                                                                                        ;
;                   |lpm_latch:U1|                               ; 1 (1)       ; 0            ; 0           ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|SYNLPM_LATR1:next_delay_counter_Sreg0_2__Z|lpm_latch:U1                                                                                           ;
;                |SYNLPM_LATR1:next_delay_counter_Sreg0_3__Z|    ; 1 (0)       ; 0            ; 0           ; 0    ; 0            ; 1 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|SYNLPM_LATR1:next_delay_counter_Sreg0_3__Z                                                                                                        ;
;                   |lpm_latch:U1|                               ; 1 (1)       ; 0            ; 0           ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|SYNLPM_LATR1:next_delay_counter_Sreg0_3__Z|lpm_latch:U1                                                                                           ;
;                |SYNLPM_LATR1:next_delay_counter_Sreg0_4__Z|    ; 1 (0)       ; 0            ; 0           ; 0    ; 0            ; 1 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|SYNLPM_LATR1:next_delay_counter_Sreg0_4__Z                                                                                                        ;
;                   |lpm_latch:U1|                               ; 1 (1)       ; 0            ; 0           ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|SYNLPM_LATR1:next_delay_counter_Sreg0_4__Z|lpm_latch:U1                                                                                           ;
;                |SYNLPM_LATS1:next_delay_counter_Sreg0_1_|      ; 1 (0)       ; 0            ; 0           ; 0    ; 0            ; 1 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|SYNLPM_LATS1:next_delay_counter_Sreg0_1_                                                                                                          ;
;                   |lpm_latch:U1|                               ; 1 (1)       ; 0            ; 0           ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|SYNLPM_LATS1:next_delay_counter_Sreg0_1_|lpm_latch:U1                                                                                             ;
;                |SYNLPM_LATS1:next_delay_counter_Sreg0_5_|      ; 1 (0)       ; 0            ; 0           ; 0    ; 0            ; 1 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|SYNLPM_LATS1:next_delay_counter_Sreg0_5_                                                                                                          ;
;                   |lpm_latch:U1|                               ; 1 (1)       ; 0            ; 0           ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|SYNLPM_LATS1:next_delay_counter_Sreg0_5_|lpm_latch:U1                                                                                             ;
;             |ext:i_ext|                                        ; 22 (22)     ; 0            ; 0           ; 0    ; 0            ; 22 (22)      ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ext:i_ext                                                                                                                                                          ;
;             |fwd_mux:rf_fwd_rt|                                ; 65 (65)     ; 0            ; 0           ; 0    ; 0            ; 65 (65)      ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt                                                                                                                                                  ;
;             |fwd_mux_1:rs_fwd_rs|                              ; 64 (64)     ; 0            ; 0           ; 0    ; 0            ; 64 (64)      ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs                                                                                                                                                ;
;             |pc_gen:i_pc_gen|                                  ; 136 (136)   ; 0            ; 0           ; 0    ; 0            ; 136 (136)    ; 0 (0)             ; 0 (0)            ; 32 (32)         ; |mips_top|mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen                                                                                                                                                    ;
;             |r32_reg_clr_cls:ins_reg|                          ; 26 (26)     ; 26           ; 0           ; 0    ; 0            ; 0 (0)        ; 26 (26)           ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|r32_reg_clr_cls:ins_reg                                                                                                                                            ;
;             |reg_array:reg_bank_cZ|                            ; 75 (75)     ; 48           ; 2048        ; 0    ; 0            ; 27 (27)      ; 16 (16)           ; 32 (32)          ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ                                                                                                                                              ;
;                |altsyncram:reg_bank_1_I_1_Z|                   ; 0 (0)       ; 0            ; 1024        ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_1_I_1_Z                                                                                                                  ;
;                   |altsyncram_3mc1:auto_generated|             ; 0 (0)       ; 0            ; 1024        ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_1_I_1_Z|altsyncram_3mc1:auto_generated                                                                                   ;
;                |altsyncram:reg_bank_I_1_Z|                     ; 0 (0)       ; 0            ; 1024        ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_I_1_Z                                                                                                                    ;
;                   |altsyncram_3mc1:auto_generated|             ; 0 (0)       ; 0            ; 1024        ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_I_1_Z|altsyncram_3mc1:auto_generated                                                                                     ;
;       |mips_dvc:imips_dvc|                                     ; 360 (121)   ; 257          ; 4096        ; 0    ; 0            ; 103 (37)     ; 71 (50)           ; 186 (34)         ; 97 (0)          ; |mips_top|mips_sys:isys|mips_dvc:imips_dvc                                                                                                                                                                                        ;
;          |seg7led_cv:iseg7_cv|                                 ; 14 (14)     ; 0            ; 0           ; 0    ; 0            ; 14 (14)      ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_dvc:imips_dvc|seg7led_cv:iseg7_cv                                                                                                                                                                    ;
;          |tmr0:mips_tmr0|                                      ; 76 (76)     ; 64           ; 0           ; 0    ; 0            ; 12 (12)      ; 0 (0)             ; 64 (64)          ; 32 (32)         ; |mips_top|mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0                                                                                                                                                                         ;
;          |uart0:iuart0|                                        ; 149 (0)     ; 109          ; 4096        ; 0    ; 0            ; 40 (0)       ; 21 (0)            ; 88 (0)           ; 65 (0)          ; |mips_top|mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0                                                                                                                                                                           ;
;             |rxd_d:rxd_rdy_hold_lw|                            ; 1 (1)       ; 1            ; 0           ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 1 (1)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|rxd_d:rxd_rdy_hold_lw                                                                                                                                                     ;
;             |uart_read:uart_rd_tak|                            ; 55 (55)     ; 42           ; 0           ; 0    ; 0            ; 13 (13)      ; 18 (18)           ; 24 (24)          ; 19 (19)         ; |mips_top|mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak                                                                                                                                                     ;
;             |uart_write:uart_txd|                              ; 93 (55)     ; 66           ; 4096        ; 0    ; 0            ; 27 (18)      ; 3 (3)             ; 63 (34)          ; 46 (19)         ; |mips_top|mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd                                                                                                                                                       ;
;                |fifo512_cyclone:fifo|                          ; 38 (0)      ; 29           ; 4096        ; 0    ; 0            ; 9 (0)        ; 0 (0)             ; 29 (0)           ; 27 (0)          ; |mips_top|mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo                                                                                                                                  ;
;                   |scfifo_Z1:scfifo_component|                 ; 38 (0)      ; 29           ; 4096        ; 0    ; 0            ; 9 (0)        ; 0 (0)             ; 29 (0)           ; 27 (0)          ; |mips_top|mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component                                                                                                       ;
;                      |scfifo:U1|                               ; 38 (0)      ; 29           ; 4096        ; 0    ; 0            ; 9 (0)        ; 0 (0)             ; 29 (0)           ; 27 (0)          ; |mips_top|mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1                                                                                             ;
;                         |scfifo_e4u:auto_generated|            ; 38 (0)      ; 29           ; 4096        ; 0    ; 0            ; 9 (0)        ; 0 (0)             ; 29 (0)           ; 27 (0)          ; |mips_top|mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated                                                                   ;
;                            |a_dpfifo_lqr:dpfifo|               ; 38 (2)      ; 29           ; 4096        ; 0    ; 0            ; 9 (2)        ; 0 (0)             ; 29 (0)           ; 27 (0)          ; |mips_top|mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo                                               ;
;                               |a_fefifo_s7f:fifo_state|        ; 18 (9)      ; 11           ; 0           ; 0    ; 0            ; 7 (7)        ; 0 (0)             ; 11 (2)           ; 9 (0)           ; |mips_top|mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|a_fefifo_s7f:fifo_state                       ;
;                                  |cntr_cc7:count_usedw|        ; 9 (9)       ; 9            ; 0           ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 9 (9)            ; 9 (9)           ; |mips_top|mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|a_fefifo_s7f:fifo_state|cntr_cc7:count_usedw  ;
;                               |cntr_ud8:rd_ptr_count|          ; 9 (9)       ; 9            ; 0           ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 9 (9)            ; 9 (9)           ; |mips_top|mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|cntr_ud8:rd_ptr_count                         ;
;                               |cntr_ud8:wr_ptr|                ; 9 (9)       ; 9            ; 0           ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 9 (9)            ; 9 (9)           ; |mips_top|mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|cntr_ud8:wr_ptr                               ;
;                               |dpram_4cm:FIFOram|              ; 0 (0)       ; 0            ; 4096        ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|dpram_4cm:FIFOram                             ;
;                                  |altsyncram_ihc1:altsyncram1| ; 0 (0)       ; 0            ; 4096        ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|dpram_4cm:FIFOram|altsyncram_ihc1:altsyncram1 ;
;    |pll50:Ipll|                                                ; 0 (0)       ; 0            ; 0           ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|pll50:Ipll                                                                                                                                                                                                              ;
;       |altpll:altpll_component|                                ; 0 (0)       ; 0            ; 0           ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mips_top|pll50:Ipll|altpll:altpll_component                                                                                                                                                                                      ;
+----------------------------------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/mips789/mips789/quartus2/mips_top.map.eqn.


+---------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                    ;
+-------------------------------------+-----------------+-------------------------------------------------------------------+
; File Name with User-Entered Path    ; Used in Netlist ; File Name with Absolute Path                                      ;
+-------------------------------------+-----------------+-------------------------------------------------------------------+
; ../synplify_prj/rev_1/mips_sys.vqm  ; yes             ; E:/mips789/mips789/synplify_prj/rev_1/mips_sys.vqm                ;
; ../rtl/verilog/altera/mips_top.v    ; yes             ; E:/mips789/mips789/rtl/verilog/altera/mips_top.v                  ;
; ../rtl/verilog/altera/pll50.v       ; yes             ; E:/mips789/mips789/rtl/verilog/altera/pll50.v                     ;
; ../rtl/verilog/altera/ram2048x8_0.v ; yes             ; E:/mips789/mips789/rtl/verilog/altera/ram2048x8_0.v               ;
; ../rtl/verilog/altera/ram2048x8_1.v ; yes             ; E:/mips789/mips789/rtl/verilog/altera/ram2048x8_1.v               ;
; ../rtl/verilog/altera/ram2048x8_2.v ; yes             ; E:/mips789/mips789/rtl/verilog/altera/ram2048x8_2.v               ;
; ../rtl/verilog/altera/ram2048x8_3.v ; yes             ; E:/mips789/mips789/rtl/verilog/altera/ram2048x8_3.v               ;
; ../rtl/verilog/altera/ram_module.v  ; yes             ; E:/mips789/mips789/rtl/verilog/altera/ram_module.v                ;
; altpll.tdf                          ; yes             ; c:/altera/quartus42/libraries/megafunctions/altpll.tdf            ;
; aglobal42.inc                       ; yes             ; c:/altera/quartus42/libraries/megafunctions/aglobal42.inc         ;
; stratix_pll.inc                     ; yes             ; c:/altera/quartus42/libraries/megafunctions/stratix_pll.inc       ;
; stratixii_pll.inc                   ; yes             ; c:/altera/quartus42/libraries/megafunctions/stratixii_pll.inc     ;
; cycloneii_pll.inc                   ; yes             ; c:/altera/quartus42/libraries/megafunctions/cycloneii_pll.inc     ;
; altsyncram.tdf                      ; yes             ; c:/altera/quartus42/libraries/megafunctions/altsyncram.tdf        ;
; stratix_ram_block.inc               ; yes             ; c:/altera/quartus42/libraries/megafunctions/stratix_ram_block.inc ;
; lpm_mux.inc                         ; yes             ; c:/altera/quartus42/libraries/megafunctions/lpm_mux.inc           ;
; lpm_decode.inc                      ; yes             ; c:/altera/quartus42/libraries/megafunctions/lpm_decode.inc        ;
; altsyncram.inc                      ; yes             ; c:/altera/quartus42/libraries/megafunctions/altsyncram.inc        ;
; a_rdenreg.inc                       ; yes             ; c:/altera/quartus42/libraries/megafunctions/a_rdenreg.inc         ;
; altrom.inc                          ; yes             ; c:/altera/quartus42/libraries/megafunctions/altrom.inc            ;
; altram.inc                          ; yes             ; c:/altera/quartus42/libraries/megafunctions/altram.inc            ;
; altdpram.inc                        ; yes             ; c:/altera/quartus42/libraries/megafunctions/altdpram.inc          ;
; altqpram.inc                        ; yes             ; c:/altera/quartus42/libraries/megafunctions/altqpram.inc          ;
; db/altsyncram_hht1.tdf              ; yes             ; E:/mips789/mips789/quartus2/db/altsyncram_hht1.tdf                ;
; db/altsyncram_ght1.tdf              ; yes             ; E:/mips789/mips789/quartus2/db/altsyncram_ght1.tdf                ;
; db/altsyncram_fht1.tdf              ; yes             ; E:/mips789/mips789/quartus2/db/altsyncram_fht1.tdf                ;
; db/altsyncram_eht1.tdf              ; yes             ; E:/mips789/mips789/quartus2/db/altsyncram_eht1.tdf                ;
; lpm_latch.tdf                       ; yes             ; c:/altera/quartus42/libraries/megafunctions/lpm_latch.tdf         ;
; lpm_constant.inc                    ; yes             ; c:/altera/quartus42/libraries/megafunctions/lpm_constant.inc      ;
; db/altsyncram_3mc1.tdf              ; yes             ; E:/mips789/mips789/quartus2/db/altsyncram_3mc1.tdf                ;
; scfifo.tdf                          ; yes             ; c:/altera/quartus42/libraries/megafunctions/scfifo.tdf            ;
; a_regfifo.inc                       ; yes             ; c:/altera/quartus42/libraries/megafunctions/a_regfifo.inc         ;
; a_dpfifo.inc                        ; yes             ; c:/altera/quartus42/libraries/megafunctions/a_dpfifo.inc          ;
; a_i2fifo.inc                        ; yes             ; c:/altera/quartus42/libraries/megafunctions/a_i2fifo.inc          ;
; a_fffifo.inc                        ; yes             ; c:/altera/quartus42/libraries/megafunctions/a_fffifo.inc          ;
; a_f2fifo.inc                        ; yes             ; c:/altera/quartus42/libraries/megafunctions/a_f2fifo.inc          ;
; db/scfifo_e4u.tdf                   ; yes             ; E:/mips789/mips789/quartus2/db/scfifo_e4u.tdf                     ;
; db/a_dpfifo_lqr.tdf                 ; yes             ; E:/mips789/mips789/quartus2/db/a_dpfifo_lqr.tdf                   ;
; db/a_fefifo_s7f.tdf                 ; yes             ; E:/mips789/mips789/quartus2/db/a_fefifo_s7f.tdf                   ;
; db/cntr_cc7.tdf                     ; yes             ; E:/mips789/mips789/quartus2/db/cntr_cc7.tdf                       ;
; db/dpram_4cm.tdf                    ; yes             ; E:/mips789/mips789/quartus2/db/dpram_4cm.tdf                      ;
; db/altsyncram_ihc1.tdf              ; yes             ; E:/mips789/mips789/quartus2/db/altsyncram_ihc1.tdf                ;
; db/cntr_ud8.tdf                     ; yes             ; E:/mips789/mips789/quartus2/db/cntr_ud8.tdf                       ;
+-------------------------------------+-----------------+-------------------------------------------------------------------+


+------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary                                  ;
+-----------------------------------+------------------------------------------+
; Resource                          ; Usage                                    ;
+-----------------------------------+------------------------------------------+
; Logic cells                       ; 3,649                                    ;
; Total combinational functions     ; 3361                                     ;
; Total 4-input functions           ; 1697                                     ;
; Total 3-input functions           ; 885                                      ;
; Total 2-input functions           ; 699                                      ;
; Total 1-input functions           ; 78                                       ;
; Total 0-input functions           ; 2                                        ;
; Combinational cells for routing   ; 0                                        ;
; Total registers                   ; 863                                      ;
; Total logic cells in carry chains ; 460                                      ;
; I/O pins                          ; 33                                       ;
; Total memory bits                 ; 71680                                    ;
; Total PLLs                        ; 1                                        ;
; Maximum fan-out node              ; pll50:Ipll|altpll:altpll_component|_clk0 ;
; Maximum fan-out                   ; 967                                      ;
; Total fan-out                     ; 15034                                    ;
; Average fan-out                   ; 3.97                                     ;
+-----------------------------------+------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary                                                                                                                                                                                                                                                                                                                ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+--------------+
; Name                                                                                                                                                                                                                               ; Type ; Mode             ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size  ; MIF          ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+--------------+
; mem_array:ram_8k|ram2048x8_0:ram0|altsyncram:altsyncram_component|altsyncram_eht1:auto_generated|ALTSYNCRAM                                                                                                                        ; AUTO ; True Dual Port   ; 2048         ; 8            ; 2048         ; 8            ; 16384 ; qu2_ram0.mif ;
; mem_array:ram_8k|ram2048x8_1:ram1|altsyncram:altsyncram_component|altsyncram_fht1:auto_generated|ALTSYNCRAM                                                                                                                        ; AUTO ; True Dual Port   ; 2048         ; 8            ; 2048         ; 8            ; 16384 ; qu2_ram1.mif ;
; mem_array:ram_8k|ram2048x8_2:ram2|altsyncram:altsyncram_component|altsyncram_ght1:auto_generated|ALTSYNCRAM                                                                                                                        ; AUTO ; True Dual Port   ; 2048         ; 8            ; 2048         ; 8            ; 16384 ; qu2_ram2.mif ;
; mem_array:ram_8k|ram2048x8_3:ram3|altsyncram:altsyncram_component|altsyncram_hht1:auto_generated|ALTSYNCRAM                                                                                                                        ; AUTO ; True Dual Port   ; 2048         ; 8            ; 2048         ; 8            ; 16384 ; qu2_ram3.mif ;
; mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_1_I_1_Z|altsyncram_3mc1:auto_generated|ALTSYNCRAM                                                                                   ; AUTO ; Simple Dual Port ; 32           ; 32           ; 32           ; 32           ; 1024  ; None         ;
; mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_I_1_Z|altsyncram_3mc1:auto_generated|ALTSYNCRAM                                                                                     ; AUTO ; Simple Dual Port ; 32           ; 32           ; 32           ; 32           ; 1024  ; None         ;
; mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|dpram_4cm:FIFOram|altsyncram_ihc1:altsyncram1|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 512          ; 8            ; 512          ; 8            ; 4096  ; None         ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+--------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 4.2 Build 157 12/07/2004 SJ Full Version
    Info: Processing started: Mon Oct 13 11:58:03 2008
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off mips_top -c mips_top
Info: Found 83 design units, including 83 entities, in source file ../synplify_prj/rev_1/mips_sys.vqm
    Info: Found entity 1: infile_dmem_ctl_reg
    Info: Found entity 2: SYNLPM_LATRS1
    Info: Found entity 3: mem_addr_ctl
    Info: Found entity 4: mem_din_ctl
    Info: Found entity 5: SYNLPM_LATR1
    Info: Found entity 6: mem_dout_ctl
    Info: Found entity 7: mem_module
    Info: Found entity 8: SYNLPM_LATS1
    Info: Found entity 9: ctl_FSM
    Info: Found entity 10: pc_gen
    Info: Found entity 11: compare
    Info: Found entity 12: ext
    Info: Found entity 13: r32_reg_clr_cls
    Info: Found entity 14: reg_array
    Info: Found entity 15: fwd_mux
    Info: Found entity 16: fwd_mux_1
    Info: Found entity 17: rf_stage
    Info: Found entity 18: muldiv_ff
    Info: Found entity 19: alu
    Info: Found entity 20: shifter_tak
    Info: Found entity 21: big_alu
    Info: Found entity 22: fwd_mux_2
    Info: Found entity 23: alu_muxa
    Info: Found entity 24: alu_muxb
    Info: Found entity 25: r32_reg
    Info: Found entity 26: r32_reg_cls
    Info: Found entity 27: exec_stage
    Info: Found entity 28: r32_reg_1
    Info: Found entity 29: r32_reg_2
    Info: Found entity 30: r32_reg_3
    Info: Found entity 31: r32_reg_4
    Info: Found entity 32: decoder
    Info: Found entity 33: muxb_ctl_reg_clr_cls
    Info: Found entity 34: wb_mux_ctl_reg_clr_cls
    Info: Found entity 35: wb_we_reg_clr_cls
    Info: Found entity 36: wb_we_reg
    Info: Found entity 37: wb_mux_ctl_reg_clr
    Info: Found entity 38: muxb_ctl_reg_clr
    Info: Found entity 39: dmem_ctl_reg_clr
    Info: Found entity 40: alu_func_reg_clr
    Info: Found entity 41: muxa_ctl_reg_clr
    Info: Found entity 42: wb_mux_ctl_reg
    Info: Found entity 43: wb_we_reg_clr
    Info: Found entity 44: cmp_ctl_reg_clr_cls
    Info: Found entity 45: wb_we_reg_1
    Info: Found entity 46: wb_mux_ctl_reg_1
    Info: Found entity 47: wb_we_reg_2
    Info: Found entity 48: alu_we_reg_clr
    Info: Found entity 49: alu_func_reg_clr_cls
    Info: Found entity 50: dmem_ctl_reg_clr_cls
    Info: Found entity 51: ext_ctl_reg_clr_cls
    Info: Found entity 52: rd_sel_reg_clr_cls
    Info: Found entity 53: alu_we_reg_clr_cls
    Info: Found entity 54: muxa_ctl_reg_clr_cls
    Info: Found entity 55: pc_gen_ctl_reg_clr_cls
    Info: Found entity 56: dmem_ctl_reg
    Info: Found entity 57: pipelinedregs
    Info: Found entity 58: decode_pipe
    Info: Found entity 59: r32_reg_5
    Info: Found entity 60: forward_node_fw_alu_rs
    Info: Found entity 61: forward_node_fw_alu_rs_1
    Info: Found entity 62: forward_node_fw_alu_rs_2
    Info: Found entity 63: forward_node_fw_alu_rs_3
    Info: Found entity 64: fw_latch5
    Info: Found entity 65: fw_latch5_1
    Info: Found entity 66: forward
    Info: Found entity 67: r32_reg_6
    Info: Found entity 68: r5_reg
    Info: Found entity 69: r5_reg_1
    Info: Found entity 70: r5_reg_2
    Info: Found entity 71: r32_reg_7
    Info: Found entity 72: r32_reg_8
    Info: Found entity 73: mips_core
    Info: Found entity 74: uart_read
    Info: Found entity 75: rxd_d
    Info: Found entity 76: scfifo_Z1
    Info: Found entity 77: fifo512_cyclone
    Info: Found entity 78: uart_write
    Info: Found entity 79: uart0
    Info: Found entity 80: seg7led_cv
    Info: Found entity 81: tmr0
    Info: Found entity 82: mips_dvc
    Info: Found entity 83: mips_sys
Info: Found 1 design units, including 1 entities, in source file ../rtl/verilog/altera/mips_top.v
    Info: Found entity 1: mips_top
Info: Found 1 design units, including 1 entities, in source file ../rtl/verilog/altera/pll25.v
    Info: Found entity 1: pll25
Info: Found 1 design units, including 1 entities, in source file ../rtl/verilog/altera/pll40.v
    Info: Found entity 1: pll40
Info: Found 1 design units, including 1 entities, in source file ../rtl/verilog/altera/pll45.v
    Info: Found entity 1: pll45
Info: Found 1 design units, including 1 entities, in source file ../rtl/verilog/altera/pll50.v
    Info: Found entity 1: pll50
Info: Found 1 design units, including 1 entities, in source file ../rtl/verilog/altera/pll75.v
    Info: Found entity 1: pll75
Info: Found 1 design units, including 1 entities, in source file ../rtl/verilog/altera/ram2048x8_0.v
    Info: Found entity 1: ram2048x8_0
Info: Found 1 design units, including 1 entities, in source file ../rtl/verilog/altera/ram2048x8_1.v
    Info: Found entity 1: ram2048x8_1
Info: Found 1 design units, including 1 entities, in source file ../rtl/verilog/altera/ram2048x8_2.v
    Info: Found entity 1: ram2048x8_2
Info: Found 1 design units, including 1 entities, in source file ../rtl/verilog/altera/ram2048x8_3.v
    Info: Found entity 1: ram2048x8_3
Info: Found 1 design units, including 1 entities, in source file ../rtl/verilog/altera/ram_module.v
    Info: Found entity 1: mem_array
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus42/libraries/megafunctions/altpll.tdf
    Info: Found entity 1: altpll
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus42/libraries/megafunctions/altsyncram.tdf
    Info: Found entity 1: altsyncram
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_hht1.tdf
    Info: Found entity 1: altsyncram_hht1
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_ght1.tdf
    Info: Found entity 1: altsyncram_ght1
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_fht1.tdf
    Info: Found entity 1: altsyncram_fht1
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_eht1.tdf
    Info: Found entity 1: altsyncram_eht1
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus42/libraries/megafunctions/lpm_latch.tdf
    Info: Found entity 1: lpm_latch
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_3mc1.tdf
    Info: Found entity 1: altsyncram_3mc1
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus42/libraries/megafunctions/scfifo.tdf
    Info: Found entity 1: scfifo
Info: Found 1 design units, including 1 entities, in source file db/scfifo_e4u.tdf
    Info: Found entity 1: scfifo_e4u
Info: Found 1 design units, including 1 entities, in source file db/a_dpfifo_lqr.tdf
    Info: Found entity 1: a_dpfifo_lqr
Info: Found 1 design units, including 1 entities, in source file db/a_fefifo_s7f.tdf
    Info: Found entity 1: a_fefifo_s7f
Info: Found 1 design units, including 1 entities, in source file db/cntr_cc7.tdf
    Info: Found entity 1: cntr_cc7
Info: Found 1 design units, including 1 entities, in source file db/dpram_4cm.tdf
    Info: Found entity 1: dpram_4cm
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_ihc1.tdf
    Info: Found entity 1: altsyncram_ihc1
Info: Found 1 design units, including 1 entities, in source file db/cntr_ud8.tdf
    Info: Found entity 1: cntr_ud8
Info: WYSIWYG I/O primitives converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|clk_in" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|rst_in" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_din_in_7_" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_ins_i_in_20_" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_din_in_22_" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_din_in_21_" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_din_in_20_" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_din_in_19_" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_din_in_18_" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_din_in_17_" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_din_in_16_" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_din_in_23_" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_ins_i_in_16_" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_ins_i_in_17_" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_ins_i_in_18_" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_ins_i_in_19_" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_din_in_6_" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_din_in_14_" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_din_in_30_" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_din_in_5_" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_din_in_13_" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_din_in_29_" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_din_in_4_" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_din_in_28_" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_din_in_12_" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_din_in_3_" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_din_in_11_" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_din_in_27_" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_din_in_2_" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_din_in_26_" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_din_in_10_" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_din_in_1_" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_din_in_25_" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_din_in_9_" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_din_in_0_" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_din_in_8_" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_din_in_24_" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_wr_en_o[0]" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_pc_o[2]" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_pc_o[3]" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_pc_o[4]" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_pc_o[5]" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_pc_o[6]" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_pc_o[7]" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_pc_o[8]" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_pc_o[9]" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_pc_o[10]" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_pc_o[11]" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_pc_o[12]" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_dout[7]" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_addr_o[2]" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_addr_o[3]" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_addr_o[4]" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_addr_o[5]" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_addr_o[6]" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_addr_o[7]" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_addr_o[8]" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_addr_o[9]" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_addr_o[10]" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_addr_o[11]" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_addr_o[12]" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_din_in_15_" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_din_in_31_" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_ins_i_in_15_" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_ins_i_in_14_" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_ins_i_in_13_" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_ins_i_in_12_" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_ins_i_in_11_" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_wr_en_o[2]" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_dout[20]" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_ins_i_in_30_" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_ins_i_in_31_" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_ins_i_in_2_" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_ins_i_in_3_" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_ins_i_in_5_" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_ins_i_in_26_" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_ins_i_in_28_" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_ins_i_in_29_" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_ins_i_in_27_" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_dout[22]" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_dout[21]" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_dout[19]" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_dout[18]" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_dout[17]" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_dout[16]" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_dout[23]" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_ins_i_in_0_" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_ins_i_in_7_" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_ins_i_in_1_" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_ins_i_in_6_" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_ins_i_in_23_" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_ins_i_in_4_" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_ins_i_in_10_" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_dout[6]" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_wr_en_o[1]" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_dout[14]" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_wr_en_o[3]" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_dout[30]" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_dout[5]" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_dout[13]" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_dout[29]" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_dout[4]" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_dout[28]" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_dout[12]" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_dout[3]" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_dout[11]" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_dout[27]" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_dout[2]" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_dout[26]" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_dout[10]" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_dout[1]" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_dout[25]" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_dout[9]" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_dout[0]" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_dout[8]" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_dout[24]" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_dout[15]" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_dout[31]" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_ins_i_in_9_" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_ins_i_in_8_" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_ins_i_in_25_" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_ins_i_in_21_" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_ins_i_in_22_" converted to equivalent logic
    Info: WYSIWYG I/O primitive "mips_sys:isys|zz_ins_i_in_24_" converted to equivalent logic
Info: Implemented 3787 device resources after synthesis - the final resource count might be different
    Info: Implemented 5 input pins
    Info: Implemented 28 output pins
    Info: Implemented 3649 logic cells
    Info: Implemented 104 RAM segments
    Info: Implemented 1 ClockLock PLLs
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
    Info: Processing ended: Mon Oct 13 11:59:16 2008
    Info: Elapsed time: 00:01:13


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