Subversion Repositories mips789

#-- Synplicity, Inc.
#-- Version Synplify Pro 8.1
#-- Project file F:\a\syn\mips_sys.prj
#-- Written on Thu Sep 20 09:14:09 2007


#add_file options
add_file -verilog "../rtl/verilog/ctl_fsm.v"
add_file -verilog "../rtl/verilog/decode_pipe.v"
add_file -verilog "../rtl/verilog/dvc.v"
add_file -verilog "../rtl/verilog/EXEC_stage.v"
add_file -verilog "../rtl/verilog/fifo.v"
add_file -verilog "../rtl/verilog/forward.v"
add_file -_include "../rtl/verilog/include.h"
add_file -verilog "../rtl/verilog/mem_module.v"
add_file -verilog "../rtl/verilog/mips_core.v"
add_file -verilog "../rtl/verilog/mips_dvc.v"
add_file -verilog "../rtl/verilog/mips_sys.v"
add_file -verilog "../rtl/verilog/mips_uart.v"
add_file -verilog "../rtl/verilog/ram_module.v"
add_file -verilog "../rtl/verilog/RF_components.v"
add_file -verilog "../rtl/verilog/RF_stage.v"
add_file -verilog "../rtl/verilog/sim_ram.v"
add_file -verilog "../rtl/verilog/tools.v"
add_file -verilog "../rtl/verilog/altera/ram_module.v"
add_file -verilog "../rtl/verilog/altera/mips_top.v"
add_file -verilog "../rtl/verilog/altera/ram2048x8_0.v"
add_file -verilog "../rtl/verilog/altera/ram2048x8_1.v"
add_file -verilog "../rtl/verilog/altera/ram2048x8_2.v"
add_file -verilog "../rtl/verilog/altera/ram2048x8_3.v"
add_file -verilog "../rtl/verilog/altera/mips_pll.v"
add_file -verilog "../rtl/verilog/altera/fifo512_cyclone.v"


#implementation: "mips_sys"
impl -add mips_sys

#device options
set_option -technology CYCLONE
set_option -part EP1C6
set_option -package QC240
set_option -speed_grade -6

#compilation/mapping options
set_option -default_enum_encoding onehot
set_option -symbolic_fsm_compiler 1
set_option -resource_sharing 1
set_option -use_fsm_explorer 1
set_option -top_module "mips_sys"

#map options
set_option -frequency auto
set_option -run_prop_extract 0
set_option -fanout_limit 30
set_option -disable_io_insertion 0
set_option -verification_mode 0
set_option -pipe 1
set_option -update_models_cp 0
set_option -retiming 0
set_option -fixgatedclocks 0
set_option -no_sequential_opt 0

#simulation options
set_option -write_verilog 0
set_option -write_vhdl 0

#VIF options
set_option -write_vif 1

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_file "mips_sys/mips_sys.vqm"

#
#implementation attributes

set_option -vlog_std v2001
set_option -dup 0
set_option -project_relative_includes 1

#par_1 attributes
set_option -job par_1 -add par
set_option -job par_1 -option enable_run 1
set_option -job par_1 -option run_backannotation 0


#implementation: "mips_top"
impl -add mips_top

#device options
set_option -technology CYCLONE
set_option -part EP1C6
set_option -package QC240
set_option -speed_grade -6

#compilation/mapping options
set_option -default_enum_encoding onehot
set_option -symbolic_fsm_compiler 1
set_option -resource_sharing 1
set_option -use_fsm_explorer 0
set_option -top_module "mips_top"

#map options
set_option -frequency auto
set_option -run_prop_extract 0
set_option -fanout_limit 30
set_option -disable_io_insertion 0
set_option -verification_mode 0
set_option -pipe 1
set_option -update_models_cp 0
set_option -retiming 1
set_option -fixgatedclocks 0
set_option -no_sequential_opt 0

#simulation options
set_option -write_verilog 0
set_option -write_vhdl 0

#VIF options
set_option -write_vif 1

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_file "mips_top/mips_top.vqm"

#
#implementation attributes

set_option -vlog_std v2001
set_option -dup 0
set_option -project_relative_includes 1

#par_1 attributes
set_option -job par_1 -add par
set_option -job par_1 -option run_backannotation 0


#implementation: "mips_core"
impl -add mips_core

#device options
set_option -technology CYCLONE
set_option -part EP1C6
set_option -package QC240
set_option -speed_grade -6

#compilation/mapping options
set_option -default_enum_encoding onehot
set_option -symbolic_fsm_compiler 1
set_option -resource_sharing 1
set_option -use_fsm_explorer 0
set_option -top_module "mips_core"

#map options
set_option -frequency auto
set_option -run_prop_extract 0
set_option -fanout_limit 30
set_option -disable_io_insertion 0
set_option -verification_mode 0
set_option -pipe 1
set_option -update_models_cp 0
set_option -retiming 1
set_option -fixgatedclocks 0
set_option -no_sequential_opt 0

#simulation options
set_option -write_verilog 0
set_option -write_vhdl 0

#VIF options
set_option -write_vif 1

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_file "mips_core/mips_core.vqm"

#
#implementation attributes

set_option -vlog_std v2001
set_option -dup 0
set_option -project_relative_includes 1

#par_1 attributes
set_option -job par_1 -add par
set_option -job par_1 -option run_backannotation 0
impl -active "mips_sys"