URL
https://opencores.org/ocsvn/mips789/mips789/trunk
Subversion Repositories mips789
[/] [mips789/] [branches/] [avendor/] [synplify_prj/] [mips_top/] [syntmp/] [mips_top_srr.htm] - Rev 51
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<!@TC:1190250600>
#Program: Synplify Pro 8.1
#OS: Windows_NT
<a name=compilerReport7>$ Start of Compile
#Thu Sep 20 09:09:59 2007
Synplicity Verilog Compiler, version 3.1.0, Build 049R, built May 3 2005
Copyright (C) 1994-2005, Synplicity Inc. All Rights Reserved
@I::"C:\Program Files\Synplicity\fpga_81\lib\altera\altera.v"
@I::"C:\Program Files\Synplicity\fpga_81\lib\altera\cyclone.v"
@I::"C:\Program Files\Synplicity\fpga_81\lib\altera\altera_mf.v"
@I::"C:\Program Files\Synplicity\fpga_81\lib\altera\altera_lpm.v"
@I::"F:\a\rtl\verilog\ctl_fsm.v"
@I:"F:\a\rtl\verilog\ctl_fsm.v":"F:\a\rtl\verilog\include.h"
@N: : <a href="f:\a\rtl\verilog\ctl_fsm.v:58:43:58:56:@N::@XP_MSG">ctl_fsm.v(58)</a><!@TM:1190250740> | Read parallel_case directive
@N: : <a href="f:\a\rtl\verilog\ctl_fsm.v:58:57:58:66:@N::@XP_MSG">ctl_fsm.v(58)</a><!@TM:1190250740> | Read full_case directive
<font color=#A52A2A>@W:<a href="@W:CG286:@XP_HELP">CG286</a> : <a href="f:\a\rtl\verilog\ctl_fsm.v:58:8:58:12:@W:CG286:@XP_MSG">ctl_fsm.v(58)</a><!@TM:1190250740> | Case statement has both a full_case directive and a default clause. The full_case directive is ignored.</font>
@I::"F:\a\rtl\verilog\decode_pipe.v"
@I:"F:\a\rtl\verilog\decode_pipe.v":"F:\a\rtl\verilog\include.h"
@N: : <a href="f:\a\rtl\verilog\decode_pipe.v:31:34:31:47:@N::@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Read parallel_case directive
@N: : <a href="f:\a\rtl\verilog\decode_pipe.v:34:45:34:58:@N::@XP_MSG">decode_pipe.v(34)</a><!@TM:1190250740> | Read parallel_case directive
@N: : <a href="f:\a\rtl\verilog\decode_pipe.v:533:47:533:60:@N::@XP_MSG">decode_pipe.v(533)</a><!@TM:1190250740> | Read parallel_case directive
@N: : <a href="f:\a\rtl\verilog\decode_pipe.v:835:49:835:62:@N::@XP_MSG">decode_pipe.v(835)</a><!@TM:1190250740> | Read parallel_case directive
@I::"F:\a\rtl\verilog\dvc.v"
@I:"F:\a\rtl\verilog\dvc.v":"F:\a\rtl\verilog\include.h"
@I::"F:\a\rtl\verilog\EXEC_stage.v"
@I:"F:\a\rtl\verilog\EXEC_stage.v":"F:\a\rtl\verilog\include.h"
@I:"F:\a\rtl\verilog\EXEC_stage.v":"F:\a\rtl\verilog\include.h"
@N: : <a href="f:\a\rtl\verilog\exec_stage.v:694:80:694:93:@N::@XP_MSG">exec_stage.v(694)</a><!@TM:1190250740> | Read parallel_case directive
@I::"F:\a\rtl\verilog\fifo.v"
@I:"F:\a\rtl\verilog\fifo.v":"F:\a\rtl\verilog\include.h"
@I::"F:\a\rtl\verilog\forward.v"
@I:"F:\a\rtl\verilog\forward.v":"F:\a\rtl\verilog\include.h"
@I::"F:\a\rtl\verilog\mem_module.v"
@I:"F:\a\rtl\verilog\mem_module.v":"F:\a\rtl\verilog\include.h"
@I::"F:\a\rtl\verilog\mips_core.v"
@I:"F:\a\rtl\verilog\mips_core.v":"F:\a\rtl\verilog\include.h"
@I::"F:\a\rtl\verilog\mips_dvc.v"
@I:"F:\a\rtl\verilog\mips_dvc.v":"F:\a\rtl\verilog\include.h"
@I::"F:\a\rtl\verilog\mips_sys.v"
@I:"F:\a\rtl\verilog\mips_sys.v":"F:\a\rtl\verilog\include.h"
@I::"F:\a\rtl\verilog\mips_uart.v"
@I:"F:\a\rtl\verilog\mips_uart.v":"F:\a\rtl\verilog\include.h"
@I::"F:\a\rtl\verilog\ram_module.v"
@I:"F:\a\rtl\verilog\ram_module.v":"F:\a\rtl\verilog\include.h"
@I::"F:\a\rtl\verilog\RF_components.v"
@I:"F:\a\rtl\verilog\RF_components.v":"F:\a\rtl\verilog\include.h"
@I::"F:\a\rtl\verilog\RF_stage.v"
@I:"F:\a\rtl\verilog\RF_stage.v":"F:\a\rtl\verilog\include.h"
@I::"F:\a\rtl\verilog\sim_ram.v"
@I::"F:\a\rtl\verilog\tools.v"
@I:"F:\a\rtl\verilog\tools.v":"F:\a\rtl\verilog\include.h"
@I::"F:\a\rtl\verilog\altera\ram_module.v"
@I::"F:\a\rtl\verilog\altera\mips_top.v"
@I::"F:\a\rtl\verilog\altera\ram2048x8_0.v"
@N: : <a href="f:\a\rtl\verilog\altera\ram2048x8_0.v:39:12:39:25:@N::@XP_MSG">ram2048x8_0.v(39)</a><!@TM:1190250740> | Read directive translate_off
@N: : <a href="f:\a\rtl\verilog\altera\ram2048x8_0.v:41:12:41:24:@N::@XP_MSG">ram2048x8_0.v(41)</a><!@TM:1190250740> | Read directive translate_on
@N: : <a href="f:\a\rtl\verilog\altera\ram2048x8_0.v:78:16:78:29:@N::@XP_MSG">ram2048x8_0.v(78)</a><!@TM:1190250740> | Read directive translate_off
@N: : <a href="f:\a\rtl\verilog\altera\ram2048x8_0.v:90:16:90:28:@N::@XP_MSG">ram2048x8_0.v(90)</a><!@TM:1190250740> | Read directive translate_on
@I::"F:\a\rtl\verilog\altera\ram2048x8_1.v"
@N: : <a href="f:\a\rtl\verilog\altera\ram2048x8_1.v:39:12:39:25:@N::@XP_MSG">ram2048x8_1.v(39)</a><!@TM:1190250740> | Read directive translate_off
@N: : <a href="f:\a\rtl\verilog\altera\ram2048x8_1.v:41:12:41:24:@N::@XP_MSG">ram2048x8_1.v(41)</a><!@TM:1190250740> | Read directive translate_on
@N: : <a href="f:\a\rtl\verilog\altera\ram2048x8_1.v:78:16:78:29:@N::@XP_MSG">ram2048x8_1.v(78)</a><!@TM:1190250740> | Read directive translate_off
@N: : <a href="f:\a\rtl\verilog\altera\ram2048x8_1.v:90:16:90:28:@N::@XP_MSG">ram2048x8_1.v(90)</a><!@TM:1190250740> | Read directive translate_on
@I::"F:\a\rtl\verilog\altera\ram2048x8_2.v"
@N: : <a href="f:\a\rtl\verilog\altera\ram2048x8_2.v:39:12:39:25:@N::@XP_MSG">ram2048x8_2.v(39)</a><!@TM:1190250740> | Read directive translate_off
@N: : <a href="f:\a\rtl\verilog\altera\ram2048x8_2.v:41:12:41:24:@N::@XP_MSG">ram2048x8_2.v(41)</a><!@TM:1190250740> | Read directive translate_on
@N: : <a href="f:\a\rtl\verilog\altera\ram2048x8_2.v:78:16:78:29:@N::@XP_MSG">ram2048x8_2.v(78)</a><!@TM:1190250740> | Read directive translate_off
@N: : <a href="f:\a\rtl\verilog\altera\ram2048x8_2.v:90:16:90:28:@N::@XP_MSG">ram2048x8_2.v(90)</a><!@TM:1190250740> | Read directive translate_on
@I::"F:\a\rtl\verilog\altera\ram2048x8_3.v"
@N: : <a href="f:\a\rtl\verilog\altera\ram2048x8_3.v:39:12:39:25:@N::@XP_MSG">ram2048x8_3.v(39)</a><!@TM:1190250740> | Read directive translate_off
@N: : <a href="f:\a\rtl\verilog\altera\ram2048x8_3.v:41:12:41:24:@N::@XP_MSG">ram2048x8_3.v(41)</a><!@TM:1190250740> | Read directive translate_on
@N: : <a href="f:\a\rtl\verilog\altera\ram2048x8_3.v:78:16:78:29:@N::@XP_MSG">ram2048x8_3.v(78)</a><!@TM:1190250740> | Read directive translate_off
@N: : <a href="f:\a\rtl\verilog\altera\ram2048x8_3.v:90:16:90:28:@N::@XP_MSG">ram2048x8_3.v(90)</a><!@TM:1190250740> | Read directive translate_on
@I::"F:\a\rtl\verilog\altera\mips_pll.v"
@N: : <a href="f:\a\rtl\verilog\altera\mips_pll.v:39:12:39:25:@N::@XP_MSG">mips_pll.v(39)</a><!@TM:1190250740> | Read directive translate_off
@N: : <a href="f:\a\rtl\verilog\altera\mips_pll.v:41:12:41:24:@N::@XP_MSG">mips_pll.v(41)</a><!@TM:1190250740> | Read directive translate_on
@N: : <a href="f:\a\rtl\verilog\altera\mips_pll.v:59:16:59:29:@N::@XP_MSG">mips_pll.v(59)</a><!@TM:1190250740> | Read directive translate_off
@N: : <a href="f:\a\rtl\verilog\altera\mips_pll.v:84:16:84:28:@N::@XP_MSG">mips_pll.v(84)</a><!@TM:1190250740> | Read directive translate_on
@I::"F:\a\rtl\verilog\altera\fifo512_cyclone.v"
@N: : <a href="f:\a\rtl\verilog\altera\fifo512_cyclone.v:39:12:39:25:@N::@XP_MSG">fifo512_cyclone.v(39)</a><!@TM:1190250740> | Read directive translate_off
@N: : <a href="f:\a\rtl\verilog\altera\fifo512_cyclone.v:41:12:41:24:@N::@XP_MSG">fifo512_cyclone.v(41)</a><!@TM:1190250740> | Read directive translate_on
@N: : <a href="f:\a\rtl\verilog\altera\fifo512_cyclone.v:74:16:74:29:@N::@XP_MSG">fifo512_cyclone.v(74)</a><!@TM:1190250740> | Read directive translate_off
@N: : <a href="f:\a\rtl\verilog\altera\fifo512_cyclone.v:81:16:81:28:@N::@XP_MSG">fifo512_cyclone.v(81)</a><!@TM:1190250740> | Read directive translate_on
Verilog syntax check successful!
File F:\a\rtl\verilog\altera\mips_top.v changed - recompiling
Selecting top level module mips_top
@N: : <a href="c:\program files\synplicity\fpga_81\lib\altera\altera_mf.v:1714:7:1714:13:@N::@XP_MSG">altera_mf.v(1714)</a><!@TM:1190250740> | Synthesizing module altpll
intended_device_family=56'b01000011011110010110001101101100011011110110111001100101
operation_mode=48'b010011100100111101010010010011010100000101001100
pll_type=32'b01000001010101010101010001001111
qualify_conf_done=24'b010011110100011001000110
compensate_clock=32'b01000011010011000100101100110000
scan_chain=32'b01001100010011110100111001000111
primary_clock=48'b011010010110111001100011011011000110101100110000
inclk0_input_frequency=32'b00000000000000001100001101010000
inclk1_input_frequency=32'b00000000000000000000000000000000
gate_lock_signal=16'b0100111001001111
gate_lock_counter=32'b00000000000000000000000000000000
lock_high=32'b00000000000000000000000000000001
lock_low=32'b00000000000000000000000000000101
valid_lock_multiplier=32'b00000000000000000000000000000001
invalid_lock_multiplier=32'b00000000000000000000000000000101
switch_over_type=32'b01000001010101010101010001001111
switch_over_on_lossclk=24'b010011110100011001000110
switch_over_on_gated_lock=24'b010011110100011001000110
enable_switch_over_counter=24'b010011110100011001000110
switch_over_counter=32'b00000000000000000000000000000000
feedback_source=56'b01000101010110000101010001000011010011000100101100110000
bandwidth=32'b00000000000000000000000000000000
bandwidth_type=48'b010101010100111001010101010100110100010101000100
lpm_hint=48'b010101010100111001010101010100110100010101000100
spread_frequency=32'b00000000000000000000000000000000
down_spread=24'b001100000010111000110000
simulation_type=80'b01100110011101010110111001100011011101000110100101101111011011100110000101101100
source_is_pll=24'b011011110110011001100110
skip_vco=24'b011011110110011001100110
clk5_multiply_by=32'b00000000000000000000000000000001
clk4_multiply_by=32'b00000000000000000000000000000001
clk3_multiply_by=32'b00000000000000000000000000000001
clk2_multiply_by=32'b00000000000000000000000000000001
clk1_multiply_by=32'b00000000000000000000000000000001
clk0_multiply_by=32'b00000000000000000000000000000010
clk5_divide_by=32'b00000000000000000000000000000001
clk4_divide_by=32'b00000000000000000000000000000001
clk3_divide_by=32'b00000000000000000000000000000001
clk2_divide_by=32'b00000000000000000000000000000001
clk1_divide_by=32'b00000000000000000000000000000001
clk0_divide_by=32'b00000000000000000000000000000001
clk5_phase_shift=8'b00110000
clk4_phase_shift=8'b00110000
clk3_phase_shift=8'b00110000
clk2_phase_shift=8'b00110000
clk1_phase_shift=8'b00110000
clk0_phase_shift=8'b00110000
clk5_time_delay=8'b00110000
clk4_time_delay=8'b00110000
clk3_time_delay=8'b00110000
clk2_time_delay=8'b00110000
clk1_time_delay=8'b00110000
clk0_time_delay=8'b00110000
clk5_duty_cycle=32'b00000000000000000000000000110010
clk4_duty_cycle=32'b00000000000000000000000000110010
clk3_duty_cycle=32'b00000000000000000000000000110010
clk2_duty_cycle=32'b00000000000000000000000000110010
clk1_duty_cycle=32'b00000000000000000000000000110010
clk0_duty_cycle=32'b00000000000000000000000000110010
clk2_output_frequency=32'b00000000000000000000000000000000
clk1_output_frequency=32'b00000000000000000000000000000000
clk0_output_frequency=32'b00000000000000000000000000000000
extclk3_multiply_by=32'b00000000000000000000000000000001
extclk2_multiply_by=32'b00000000000000000000000000000001
extclk1_multiply_by=32'b00000000000000000000000000000001
extclk0_multiply_by=32'b00000000000000000000000000000001
extclk3_divide_by=32'b00000000000000000000000000000001
extclk2_divide_by=32'b00000000000000000000000000000001
extclk1_divide_by=32'b00000000000000000000000000000001
extclk0_divide_by=32'b00000000000000000000000000000001
extclk3_phase_shift=8'b00110000
extclk2_phase_shift=8'b00110000
extclk1_phase_shift=8'b00110000
extclk0_phase_shift=8'b00110000
extclk3_time_delay=8'b00110000
extclk2_time_delay=8'b00110000
extclk1_time_delay=8'b00110000
extclk0_time_delay=8'b00110000
extclk3_duty_cycle=32'b00000000000000000000000000110010
extclk2_duty_cycle=32'b00000000000000000000000000110010
extclk1_duty_cycle=32'b00000000000000000000000000110010
extclk0_duty_cycle=32'b00000000000000000000000000110010
vco_multiply_by=32'b00000000000000000000000000000001
vco_divide_by=32'b00000000000000000000000000000001
sclkout0_phase_shift=8'b00110000
sclkout1_phase_shift=8'b00110000
vco_min=32'b00000000000000000000000000000000
vco_max=32'b00000000000000000000000000000000
vco_center=32'b00000000000000000000000000000000
pfd_min=32'b00000000000000000000000000000000
pfd_max=32'b00000000000000000000000000000000
m_initial=32'b00000000000000000000000000000001
m=32'b00000000000000000000000000000000
n=32'b00000000000000000000000000000001
m2=32'b00000000000000000000000000000001
n2=32'b00000000000000000000000000000001
ss=32'b00000000000000000000000000000000
l0_high=32'b00000000000000000000000000000001
l1_high=32'b00000000000000000000000000000001
g0_high=32'b00000000000000000000000000000001
g1_high=32'b00000000000000000000000000000001
g2_high=32'b00000000000000000000000000000001
g3_high=32'b00000000000000000000000000000001
e0_high=32'b00000000000000000000000000000001
e1_high=32'b00000000000000000000000000000001
e2_high=32'b00000000000000000000000000000001
e3_high=32'b00000000000000000000000000000001
l0_low=32'b00000000000000000000000000000001
l1_low=32'b00000000000000000000000000000001
g0_low=32'b00000000000000000000000000000001
g1_low=32'b00000000000000000000000000000001
g2_low=32'b00000000000000000000000000000001
g3_low=32'b00000000000000000000000000000001
e0_low=32'b00000000000000000000000000000001
e1_low=32'b00000000000000000000000000000001
e2_low=32'b00000000000000000000000000000001
e3_low=32'b00000000000000000000000000000001
l0_initial=32'b00000000000000000000000000000001
l1_initial=32'b00000000000000000000000000000001
g0_initial=32'b00000000000000000000000000000001
g1_initial=32'b00000000000000000000000000000001
g2_initial=32'b00000000000000000000000000000001
g3_initial=32'b00000000000000000000000000000001
e0_initial=32'b00000000000000000000000000000001
e1_initial=32'b00000000000000000000000000000001
e2_initial=32'b00000000000000000000000000000001
e3_initial=32'b00000000000000000000000000000001
l0_mode=48'b011000100111100101110000011000010111001101110011
l1_mode=48'b011000100111100101110000011000010111001101110011
g0_mode=48'b011000100111100101110000011000010111001101110011
g1_mode=48'b011000100111100101110000011000010111001101110011
g2_mode=48'b011000100111100101110000011000010111001101110011
g3_mode=48'b011000100111100101110000011000010111001101110011
e0_mode=48'b011000100111100101110000011000010111001101110011
e1_mode=48'b011000100111100101110000011000010111001101110011
e2_mode=48'b011000100111100101110000011000010111001101110011
e3_mode=48'b011000100111100101110000011000010111001101110011
l0_ph=32'b00000000000000000000000000000000
l1_ph=32'b00000000000000000000000000000000
g0_ph=32'b00000000000000000000000000000000
g1_ph=32'b00000000000000000000000000000000
g2_ph=32'b00000000000000000000000000000000
g3_ph=32'b00000000000000000000000000000000
e0_ph=32'b00000000000000000000000000000000
e1_ph=32'b00000000000000000000000000000000
e2_ph=32'b00000000000000000000000000000000
e3_ph=32'b00000000000000000000000000000000
m_ph=32'b00000000000000000000000000000000
l0_time_delay=32'b00000000000000000000000000000000
l1_time_delay=32'b00000000000000000000000000000000
g0_time_delay=32'b00000000000000000000000000000000
g1_time_delay=32'b00000000000000000000000000000000
g2_time_delay=32'b00000000000000000000000000000000
g3_time_delay=32'b00000000000000000000000000000000
e0_time_delay=32'b00000000000000000000000000000000
e1_time_delay=32'b00000000000000000000000000000000
e2_time_delay=32'b00000000000000000000000000000000
e3_time_delay=32'b00000000000000000000000000000000
m_time_delay=32'b00000000000000000000000000000000
n_time_delay=32'b00000000000000000000000000000000
extclk3_counter=16'b0110010100110011
extclk2_counter=16'b0110010100110010
extclk1_counter=16'b0110010100110001
extclk0_counter=16'b0110010100110000
clk5_counter=16'b0110110000110001
clk4_counter=16'b0110110000110000
clk3_counter=16'b0110011100110011
clk2_counter=16'b0110011100110010
clk1_counter=16'b0110011100110001
clk0_counter=16'b0110011100110000
enable0_counter=16'b0110110000110000
enable1_counter=16'b0110110000110000
charge_pump_current=32'b00000000000000000000000000000010
loop_filter_r=24'b001100010010111000110000
loop_filter_c=32'b00000000000000000000000000000101
vco_post_scale=32'b00000000000000000000000000000000
lpm_type=48'b011000010110110001110100011100000110110001101100
c0_high=32'b00000000000000000000000000000001
c1_high=32'b00000000000000000000000000000001
c2_high=32'b00000000000000000000000000000001
c3_high=32'b00000000000000000000000000000001
c4_high=32'b00000000000000000000000000000001
c5_high=32'b00000000000000000000000000000001
c0_low=32'b00000000000000000000000000000001
c1_low=32'b00000000000000000000000000000001
c2_low=32'b00000000000000000000000000000001
c3_low=32'b00000000000000000000000000000001
c4_low=32'b00000000000000000000000000000001
c5_low=32'b00000000000000000000000000000001
c0_initial=32'b00000000000000000000000000000001
c1_initial=32'b00000000000000000000000000000001
c2_initial=32'b00000000000000000000000000000001
c3_initial=32'b00000000000000000000000000000001
c4_initial=32'b00000000000000000000000000000001
c5_initial=32'b00000000000000000000000000000001
c0_mode=48'b011000100111100101110000011000010111001101110011
c1_mode=48'b011000100111100101110000011000010111001101110011
c2_mode=48'b011000100111100101110000011000010111001101110011
c3_mode=48'b011000100111100101110000011000010111001101110011
c4_mode=48'b011000100111100101110000011000010111001101110011
c5_mode=48'b011000100111100101110000011000010111001101110011
c0_ph=32'b00000000000000000000000000000000
c1_ph=32'b00000000000000000000000000000000
c2_ph=32'b00000000000000000000000000000000
c3_ph=32'b00000000000000000000000000000000
c4_ph=32'b00000000000000000000000000000000
c5_ph=32'b00000000000000000000000000000000
c1_use_casc_in=24'b011011110110011001100110
c2_use_casc_in=24'b011011110110011001100110
c3_use_casc_in=24'b011011110110011001100110
c4_use_casc_in=24'b011011110110011001100110
c5_use_casc_in=24'b011011110110011001100110
Generated name = altpll_Z1
@N: : <a href="f:\a\rtl\verilog\altera\mips_pll.v:42:7:42:15:@N::@XP_MSG">mips_pll.v(42)</a><!@TM:1190250740> | Synthesizing module mips_pll
@N: : <a href="c:\program files\synplicity\fpga_81\lib\altera\altera_mf.v:3199:7:3199:17:@N::@XP_MSG">altera_mf.v(3199)</a><!@TM:1190250740> | Synthesizing module altsyncram
width_a=32'b00000000000000000000000000001000
widthad_a=32'b00000000000000000000000000001011
numwords_a=32'b00000000000000000000100000000000
outdata_reg_a=96'b010101010100111001010010010001010100011101001001010100110101010001000101010100100100010101000100
address_aclr_a=32'b01001110010011110100111001000101
outdata_aclr_a=32'b01001110010011110100111001000101
indata_aclr_a=32'b01001110010011110100111001000101
wrcontrol_aclr_a=32'b01001110010011110100111001000101
byteena_aclr_a=32'b01001110010011110100111001000101
width_byteena_a=32'b00000000000000000000000000000001
width_b=32'b00000000000000000000000000001000
widthad_b=32'b00000000000000000000000000001011
numwords_b=32'b00000000000000000000100000000000
rdcontrol_reg_b=48'b010000110100110001001111010000110100101100110001
address_reg_b=48'b010000110100110001001111010000110100101100110000
outdata_reg_b=96'b010101010100111001010010010001010100011101001001010100110101010001000101010100100100010101000100
outdata_aclr_b=32'b01001110010011110100111001000101
rdcontrol_aclr_b=32'b01001110010011110100111001000101
indata_reg_b=48'b010000110100110001001111010000110100101100110000
wrcontrol_wraddress_reg_b=48'b010000110100110001001111010000110100101100110000
byteena_reg_b=48'b010000110100110001001111010000110100101100110001
indata_aclr_b=32'b01001110010011110100111001000101
wrcontrol_aclr_b=32'b01001110010011110100111001000101
address_aclr_b=32'b01001110010011110100111001000101
byteena_aclr_b=32'b01001110010011110100111001000101
width_byteena_b=32'b00000000000000000000000000000001
clock_enable_input_a=48'b010011100100111101010010010011010100000101001100
clock_enable_output_a=48'b010011100100111101010010010011010100000101001100
clock_enable_input_b=48'b010011100100111101010010010011010100000101001100
clock_enable_output_b=48'b010011100100111101010010010011010100000101001100
operation_mode=120'b010000100100100101000100010010010101001001011111010001000101010101000001010011000101111101010000010011110101001001010100
byte_size=32'b00000000000000000000000000001000
read_during_write_mode_mixed_ports=72'b010001000100111101001110010101000101111101000011010000010101001001000101
ram_block_type=32'b01000001010101010101010001001111
init_file=96'b011100010111010100110010010111110111001001100001011011010011001100101110011011010110100101100110
init_file_layout=48'b010101010100111001010101010100110100010101000100
maximum_depth=32'b00000000000000000000000000000000
intended_device_family=56'b01000011011110010110001101101100011011110110111001100101
lpm_hint=48'b010101010100111001010101010100110100010101000100
lpm_type=80'b01100001011011000111010001110011011110010110111001100011011100100110000101101101
cread_during_write_mode_mixed_ports=72'b010001000100111101001110010101000101111101000011010000010101001001000101
Generated name = altsyncram_Z2
@N: : <a href="f:\a\rtl\verilog\altera\ram2048x8_3.v:42:7:42:18:@N::@XP_MSG">ram2048x8_3.v(42)</a><!@TM:1190250740> | Synthesizing module ram2048x8_3
@N: : <a href="c:\program files\synplicity\fpga_81\lib\altera\altera_mf.v:3199:7:3199:17:@N::@XP_MSG">altera_mf.v(3199)</a><!@TM:1190250740> | Synthesizing module altsyncram
width_a=32'b00000000000000000000000000001000
widthad_a=32'b00000000000000000000000000001011
numwords_a=32'b00000000000000000000100000000000
outdata_reg_a=96'b010101010100111001010010010001010100011101001001010100110101010001000101010100100100010101000100
address_aclr_a=32'b01001110010011110100111001000101
outdata_aclr_a=32'b01001110010011110100111001000101
indata_aclr_a=32'b01001110010011110100111001000101
wrcontrol_aclr_a=32'b01001110010011110100111001000101
byteena_aclr_a=32'b01001110010011110100111001000101
width_byteena_a=32'b00000000000000000000000000000001
width_b=32'b00000000000000000000000000001000
widthad_b=32'b00000000000000000000000000001011
numwords_b=32'b00000000000000000000100000000000
rdcontrol_reg_b=48'b010000110100110001001111010000110100101100110001
address_reg_b=48'b010000110100110001001111010000110100101100110000
outdata_reg_b=96'b010101010100111001010010010001010100011101001001010100110101010001000101010100100100010101000100
outdata_aclr_b=32'b01001110010011110100111001000101
rdcontrol_aclr_b=32'b01001110010011110100111001000101
indata_reg_b=48'b010000110100110001001111010000110100101100110000
wrcontrol_wraddress_reg_b=48'b010000110100110001001111010000110100101100110000
byteena_reg_b=48'b010000110100110001001111010000110100101100110001
indata_aclr_b=32'b01001110010011110100111001000101
wrcontrol_aclr_b=32'b01001110010011110100111001000101
address_aclr_b=32'b01001110010011110100111001000101
byteena_aclr_b=32'b01001110010011110100111001000101
width_byteena_b=32'b00000000000000000000000000000001
clock_enable_input_a=48'b010011100100111101010010010011010100000101001100
clock_enable_output_a=48'b010011100100111101010010010011010100000101001100
clock_enable_input_b=48'b010011100100111101010010010011010100000101001100
clock_enable_output_b=48'b010011100100111101010010010011010100000101001100
operation_mode=120'b010000100100100101000100010010010101001001011111010001000101010101000001010011000101111101010000010011110101001001010100
byte_size=32'b00000000000000000000000000001000
read_during_write_mode_mixed_ports=72'b010001000100111101001110010101000101111101000011010000010101001001000101
ram_block_type=32'b01000001010101010101010001001111
init_file=96'b011100010111010100110010010111110111001001100001011011010011001000101110011011010110100101100110
init_file_layout=48'b010101010100111001010101010100110100010101000100
maximum_depth=32'b00000000000000000000000000000000
intended_device_family=56'b01000011011110010110001101101100011011110110111001100101
lpm_hint=48'b010101010100111001010101010100110100010101000100
lpm_type=80'b01100001011011000111010001110011011110010110111001100011011100100110000101101101
cread_during_write_mode_mixed_ports=72'b010001000100111101001110010101000101111101000011010000010101001001000101
Generated name = altsyncram_Z3
@N: : <a href="f:\a\rtl\verilog\altera\ram2048x8_2.v:42:7:42:18:@N::@XP_MSG">ram2048x8_2.v(42)</a><!@TM:1190250740> | Synthesizing module ram2048x8_2
@N: : <a href="c:\program files\synplicity\fpga_81\lib\altera\altera_mf.v:3199:7:3199:17:@N::@XP_MSG">altera_mf.v(3199)</a><!@TM:1190250740> | Synthesizing module altsyncram
width_a=32'b00000000000000000000000000001000
widthad_a=32'b00000000000000000000000000001011
numwords_a=32'b00000000000000000000100000000000
outdata_reg_a=96'b010101010100111001010010010001010100011101001001010100110101010001000101010100100100010101000100
address_aclr_a=32'b01001110010011110100111001000101
outdata_aclr_a=32'b01001110010011110100111001000101
indata_aclr_a=32'b01001110010011110100111001000101
wrcontrol_aclr_a=32'b01001110010011110100111001000101
byteena_aclr_a=32'b01001110010011110100111001000101
width_byteena_a=32'b00000000000000000000000000000001
width_b=32'b00000000000000000000000000001000
widthad_b=32'b00000000000000000000000000001011
numwords_b=32'b00000000000000000000100000000000
rdcontrol_reg_b=48'b010000110100110001001111010000110100101100110001
address_reg_b=48'b010000110100110001001111010000110100101100110000
outdata_reg_b=96'b010101010100111001010010010001010100011101001001010100110101010001000101010100100100010101000100
outdata_aclr_b=32'b01001110010011110100111001000101
rdcontrol_aclr_b=32'b01001110010011110100111001000101
indata_reg_b=48'b010000110100110001001111010000110100101100110000
wrcontrol_wraddress_reg_b=48'b010000110100110001001111010000110100101100110000
byteena_reg_b=48'b010000110100110001001111010000110100101100110001
indata_aclr_b=32'b01001110010011110100111001000101
wrcontrol_aclr_b=32'b01001110010011110100111001000101
address_aclr_b=32'b01001110010011110100111001000101
byteena_aclr_b=32'b01001110010011110100111001000101
width_byteena_b=32'b00000000000000000000000000000001
clock_enable_input_a=48'b010011100100111101010010010011010100000101001100
clock_enable_output_a=48'b010011100100111101010010010011010100000101001100
clock_enable_input_b=48'b010011100100111101010010010011010100000101001100
clock_enable_output_b=48'b010011100100111101010010010011010100000101001100
operation_mode=120'b010000100100100101000100010010010101001001011111010001000101010101000001010011000101111101010000010011110101001001010100
byte_size=32'b00000000000000000000000000001000
read_during_write_mode_mixed_ports=72'b010001000100111101001110010101000101111101000011010000010101001001000101
ram_block_type=32'b01000001010101010101010001001111
init_file=96'b011100010111010100110010010111110111001001100001011011010011000100101110011011010110100101100110
init_file_layout=48'b010101010100111001010101010100110100010101000100
maximum_depth=32'b00000000000000000000000000000000
intended_device_family=56'b01000011011110010110001101101100011011110110111001100101
lpm_hint=48'b010101010100111001010101010100110100010101000100
lpm_type=80'b01100001011011000111010001110011011110010110111001100011011100100110000101101101
cread_during_write_mode_mixed_ports=72'b010001000100111101001110010101000101111101000011010000010101001001000101
Generated name = altsyncram_Z4
@N: : <a href="f:\a\rtl\verilog\altera\ram2048x8_1.v:42:7:42:18:@N::@XP_MSG">ram2048x8_1.v(42)</a><!@TM:1190250740> | Synthesizing module ram2048x8_1
@N: : <a href="c:\program files\synplicity\fpga_81\lib\altera\altera_mf.v:3199:7:3199:17:@N::@XP_MSG">altera_mf.v(3199)</a><!@TM:1190250740> | Synthesizing module altsyncram
width_a=32'b00000000000000000000000000001000
widthad_a=32'b00000000000000000000000000001011
numwords_a=32'b00000000000000000000100000000000
outdata_reg_a=96'b010101010100111001010010010001010100011101001001010100110101010001000101010100100100010101000100
address_aclr_a=32'b01001110010011110100111001000101
outdata_aclr_a=32'b01001110010011110100111001000101
indata_aclr_a=32'b01001110010011110100111001000101
wrcontrol_aclr_a=32'b01001110010011110100111001000101
byteena_aclr_a=32'b01001110010011110100111001000101
width_byteena_a=32'b00000000000000000000000000000001
width_b=32'b00000000000000000000000000001000
widthad_b=32'b00000000000000000000000000001011
numwords_b=32'b00000000000000000000100000000000
rdcontrol_reg_b=48'b010000110100110001001111010000110100101100110001
address_reg_b=48'b010000110100110001001111010000110100101100110000
outdata_reg_b=96'b010101010100111001010010010001010100011101001001010100110101010001000101010100100100010101000100
outdata_aclr_b=32'b01001110010011110100111001000101
rdcontrol_aclr_b=32'b01001110010011110100111001000101
indata_reg_b=48'b010000110100110001001111010000110100101100110000
wrcontrol_wraddress_reg_b=48'b010000110100110001001111010000110100101100110000
byteena_reg_b=48'b010000110100110001001111010000110100101100110001
indata_aclr_b=32'b01001110010011110100111001000101
wrcontrol_aclr_b=32'b01001110010011110100111001000101
address_aclr_b=32'b01001110010011110100111001000101
byteena_aclr_b=32'b01001110010011110100111001000101
width_byteena_b=32'b00000000000000000000000000000001
clock_enable_input_a=48'b010011100100111101010010010011010100000101001100
clock_enable_output_a=48'b010011100100111101010010010011010100000101001100
clock_enable_input_b=48'b010011100100111101010010010011010100000101001100
clock_enable_output_b=48'b010011100100111101010010010011010100000101001100
operation_mode=120'b010000100100100101000100010010010101001001011111010001000101010101000001010011000101111101010000010011110101001001010100
byte_size=32'b00000000000000000000000000001000
read_during_write_mode_mixed_ports=72'b010001000100111101001110010101000101111101000011010000010101001001000101
ram_block_type=32'b01000001010101010101010001001111
init_file=96'b011100010111010100110010010111110111001001100001011011010011000000101110011011010110100101100110
init_file_layout=48'b010101010100111001010101010100110100010101000100
maximum_depth=32'b00000000000000000000000000000000
intended_device_family=56'b01000011011110010110001101101100011011110110111001100101
lpm_hint=48'b010101010100111001010101010100110100010101000100
lpm_type=80'b01100001011011000111010001110011011110010110111001100011011100100110000101101101
cread_during_write_mode_mixed_ports=72'b010001000100111101001110010101000101111101000011010000010101001001000101
Generated name = altsyncram_Z5
@N: : <a href="f:\a\rtl\verilog\altera\ram2048x8_0.v:42:7:42:18:@N::@XP_MSG">ram2048x8_0.v(42)</a><!@TM:1190250740> | Synthesizing module ram2048x8_0
@N: : <a href="f:\a\rtl\verilog\altera\ram_module.v:2:7:2:16:@N::@XP_MSG">ram_module.v(2)</a><!@TM:1190250740> | Synthesizing module mem_array
<font color=#A52A2A>@W:<a href="@W:CS149:@XP_HELP">CS149</a> : <a href="f:\a\rtl\verilog\altera\ram_module.v:21:28:21:33:@W:CS149:@XP_MSG">ram_module.v(21)</a><!@TM:1190250740> | Port width mismatch for port data_a. Formal has width 8, Actual 32</font>
<font color=#A52A2A>@W:<a href="@W:CS149:@XP_HELP">CS149</a> : <a href="f:\a\rtl\verilog\altera\ram_module.v:23:31:23:33:@W:CS149:@XP_MSG">ram_module.v(23)</a><!@TM:1190250740> | Port width mismatch for port address_a. Formal has width 11, Actual 32</font>
<font color=#A52A2A>@W:<a href="@W:CS149:@XP_HELP">CS149</a> : <a href="f:\a\rtl\verilog\altera\ram_module.v:25:31:25:38:@W:CS149:@XP_MSG">ram_module.v(25)</a><!@TM:1190250740> | Port width mismatch for port address_b. Formal has width 11, Actual 32</font>
<font color=#A52A2A>@W:<a href="@W:CS149:@XP_HELP">CS149</a> : <a href="f:\a\rtl\verilog\altera\ram_module.v:33:28:33:33:@W:CS149:@XP_MSG">ram_module.v(33)</a><!@TM:1190250740> | Port width mismatch for port data_a. Formal has width 8, Actual 32</font>
<font color=#A52A2A>@W:<a href="@W:CS149:@XP_HELP">CS149</a> : <a href="f:\a\rtl\verilog\altera\ram_module.v:35:31:35:33:@W:CS149:@XP_MSG">ram_module.v(35)</a><!@TM:1190250740> | Port width mismatch for port address_a. Formal has width 11, Actual 32</font>
<font color=#A52A2A>@W:<a href="@W:CS149:@XP_HELP">CS149</a> : <a href="f:\a\rtl\verilog\altera\ram_module.v:37:31:37:38:@W:CS149:@XP_MSG">ram_module.v(37)</a><!@TM:1190250740> | Port width mismatch for port address_b. Formal has width 11, Actual 32</font>
<font color=#A52A2A>@W:<a href="@W:CS149:@XP_HELP">CS149</a> : <a href="f:\a\rtl\verilog\altera\ram_module.v:45:28:45:33:@W:CS149:@XP_MSG">ram_module.v(45)</a><!@TM:1190250740> | Port width mismatch for port data_a. Formal has width 8, Actual 32</font>
<font color=#A52A2A>@W:<a href="@W:CS149:@XP_HELP">CS149</a> : <a href="f:\a\rtl\verilog\altera\ram_module.v:47:31:47:33:@W:CS149:@XP_MSG">ram_module.v(47)</a><!@TM:1190250740> | Port width mismatch for port address_a. Formal has width 11, Actual 32</font>
<font color=#A52A2A>@W:<a href="@W:CS149:@XP_HELP">CS149</a> : <a href="f:\a\rtl\verilog\altera\ram_module.v:49:31:49:38:@W:CS149:@XP_MSG">ram_module.v(49)</a><!@TM:1190250740> | Port width mismatch for port address_b. Formal has width 11, Actual 32</font>
<font color=#A52A2A>@W:<a href="@W:CS149:@XP_HELP">CS149</a> : <a href="f:\a\rtl\verilog\altera\ram_module.v:57:28:57:33:@W:CS149:@XP_MSG">ram_module.v(57)</a><!@TM:1190250740> | Port width mismatch for port data_a. Formal has width 8, Actual 32</font>
<font color=#A52A2A>@W:<a href="@W:CS149:@XP_HELP">CS149</a> : <a href="f:\a\rtl\verilog\altera\ram_module.v:59:31:59:33:@W:CS149:@XP_MSG">ram_module.v(59)</a><!@TM:1190250740> | Port width mismatch for port address_a. Formal has width 11, Actual 32</font>
<font color=#A52A2A>@W:<a href="@W:CS149:@XP_HELP">CS149</a> : <a href="f:\a\rtl\verilog\altera\ram_module.v:61:31:61:38:@W:CS149:@XP_MSG">ram_module.v(61)</a><!@TM:1190250740> | Port width mismatch for port address_b. Formal has width 11, Actual 32</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\altera\ram_module.v:5:21:5:25:@W::@XP_MSG">ram_module.v(5)</a><!@TM:1190250740> | Input port bit <31> of pc_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\altera\ram_module.v:5:21:5:25:@W::@XP_MSG">ram_module.v(5)</a><!@TM:1190250740> | Input port bit <30> of pc_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\altera\ram_module.v:5:21:5:25:@W::@XP_MSG">ram_module.v(5)</a><!@TM:1190250740> | Input port bit <29> of pc_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\altera\ram_module.v:5:21:5:25:@W::@XP_MSG">ram_module.v(5)</a><!@TM:1190250740> | Input port bit <28> of pc_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\altera\ram_module.v:5:21:5:25:@W::@XP_MSG">ram_module.v(5)</a><!@TM:1190250740> | Input port bit <27> of pc_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\altera\ram_module.v:5:21:5:25:@W::@XP_MSG">ram_module.v(5)</a><!@TM:1190250740> | Input port bit <26> of pc_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\altera\ram_module.v:5:21:5:25:@W::@XP_MSG">ram_module.v(5)</a><!@TM:1190250740> | Input port bit <25> of pc_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\altera\ram_module.v:5:21:5:25:@W::@XP_MSG">ram_module.v(5)</a><!@TM:1190250740> | Input port bit <24> of pc_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\altera\ram_module.v:5:21:5:25:@W::@XP_MSG">ram_module.v(5)</a><!@TM:1190250740> | Input port bit <23> of pc_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\altera\ram_module.v:5:21:5:25:@W::@XP_MSG">ram_module.v(5)</a><!@TM:1190250740> | Input port bit <22> of pc_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\altera\ram_module.v:5:21:5:25:@W::@XP_MSG">ram_module.v(5)</a><!@TM:1190250740> | Input port bit <21> of pc_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\altera\ram_module.v:5:21:5:25:@W::@XP_MSG">ram_module.v(5)</a><!@TM:1190250740> | Input port bit <20> of pc_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\altera\ram_module.v:5:21:5:25:@W::@XP_MSG">ram_module.v(5)</a><!@TM:1190250740> | Input port bit <19> of pc_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\altera\ram_module.v:5:21:5:25:@W::@XP_MSG">ram_module.v(5)</a><!@TM:1190250740> | Input port bit <18> of pc_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\altera\ram_module.v:5:21:5:25:@W::@XP_MSG">ram_module.v(5)</a><!@TM:1190250740> | Input port bit <17> of pc_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\altera\ram_module.v:5:21:5:25:@W::@XP_MSG">ram_module.v(5)</a><!@TM:1190250740> | Input port bit <16> of pc_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\altera\ram_module.v:5:21:5:25:@W::@XP_MSG">ram_module.v(5)</a><!@TM:1190250740> | Input port bit <15> of pc_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\altera\ram_module.v:5:21:5:25:@W::@XP_MSG">ram_module.v(5)</a><!@TM:1190250740> | Input port bit <14> of pc_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\altera\ram_module.v:5:21:5:25:@W::@XP_MSG">ram_module.v(5)</a><!@TM:1190250740> | Input port bit <13> of pc_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\altera\ram_module.v:5:21:5:25:@W::@XP_MSG">ram_module.v(5)</a><!@TM:1190250740> | Input port bit <1> of pc_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\altera\ram_module.v:5:21:5:25:@W::@XP_MSG">ram_module.v(5)</a><!@TM:1190250740> | Input port bit <0> of pc_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\altera\ram_module.v:9:20:9:29:@W::@XP_MSG">ram_module.v(9)</a><!@TM:1190250740> | Input port bit <31> of wr_addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\altera\ram_module.v:9:20:9:29:@W::@XP_MSG">ram_module.v(9)</a><!@TM:1190250740> | Input port bit <30> of wr_addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\altera\ram_module.v:9:20:9:29:@W::@XP_MSG">ram_module.v(9)</a><!@TM:1190250740> | Input port bit <29> of wr_addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\altera\ram_module.v:9:20:9:29:@W::@XP_MSG">ram_module.v(9)</a><!@TM:1190250740> | Input port bit <28> of wr_addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\altera\ram_module.v:9:20:9:29:@W::@XP_MSG">ram_module.v(9)</a><!@TM:1190250740> | Input port bit <27> of wr_addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\altera\ram_module.v:9:20:9:29:@W::@XP_MSG">ram_module.v(9)</a><!@TM:1190250740> | Input port bit <26> of wr_addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\altera\ram_module.v:9:20:9:29:@W::@XP_MSG">ram_module.v(9)</a><!@TM:1190250740> | Input port bit <25> of wr_addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\altera\ram_module.v:9:20:9:29:@W::@XP_MSG">ram_module.v(9)</a><!@TM:1190250740> | Input port bit <24> of wr_addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\altera\ram_module.v:9:20:9:29:@W::@XP_MSG">ram_module.v(9)</a><!@TM:1190250740> | Input port bit <23> of wr_addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\altera\ram_module.v:9:20:9:29:@W::@XP_MSG">ram_module.v(9)</a><!@TM:1190250740> | Input port bit <22> of wr_addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\altera\ram_module.v:9:20:9:29:@W::@XP_MSG">ram_module.v(9)</a><!@TM:1190250740> | Input port bit <21> of wr_addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\altera\ram_module.v:9:20:9:29:@W::@XP_MSG">ram_module.v(9)</a><!@TM:1190250740> | Input port bit <20> of wr_addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\altera\ram_module.v:9:20:9:29:@W::@XP_MSG">ram_module.v(9)</a><!@TM:1190250740> | Input port bit <19> of wr_addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\altera\ram_module.v:9:20:9:29:@W::@XP_MSG">ram_module.v(9)</a><!@TM:1190250740> | Input port bit <18> of wr_addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\altera\ram_module.v:9:20:9:29:@W::@XP_MSG">ram_module.v(9)</a><!@TM:1190250740> | Input port bit <17> of wr_addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\altera\ram_module.v:9:20:9:29:@W::@XP_MSG">ram_module.v(9)</a><!@TM:1190250740> | Input port bit <16> of wr_addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\altera\ram_module.v:9:20:9:29:@W::@XP_MSG">ram_module.v(9)</a><!@TM:1190250740> | Input port bit <15> of wr_addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\altera\ram_module.v:9:20:9:29:@W::@XP_MSG">ram_module.v(9)</a><!@TM:1190250740> | Input port bit <14> of wr_addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\altera\ram_module.v:9:20:9:29:@W::@XP_MSG">ram_module.v(9)</a><!@TM:1190250740> | Input port bit <13> of wr_addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\altera\ram_module.v:9:20:9:29:@W::@XP_MSG">ram_module.v(9)</a><!@TM:1190250740> | Input port bit <1> of wr_addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\altera\ram_module.v:9:20:9:29:@W::@XP_MSG">ram_module.v(9)</a><!@TM:1190250740> | Input port bit <0> of wr_addr_i[31:0] is unused</font>
<font color=#A52A2A>@W:<a href="@W:CL159:@XP_HELP">CL159</a> : <a href="f:\a\rtl\verilog\altera\ram_module.v:10:20:10:29:@W:CL159:@XP_MSG">ram_module.v(10)</a><!@TM:1190250740> | Input rd_addr_i is unused</font>
@N: : <a href="f:\a\rtl\verilog\mem_module.v:78:7:78:26:@N::@XP_MSG">mem_module.v(78)</a><!@TM:1190250740> | Synthesizing module infile_dmem_ctl_reg
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1190250740> | Input port bit <30> of dmem_addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1190250740> | Input port bit <29> of dmem_addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1190250740> | Input port bit <28> of dmem_addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1190250740> | Input port bit <27> of dmem_addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1190250740> | Input port bit <26> of dmem_addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1190250740> | Input port bit <25> of dmem_addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1190250740> | Input port bit <24> of dmem_addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1190250740> | Input port bit <23> of dmem_addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1190250740> | Input port bit <22> of dmem_addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1190250740> | Input port bit <21> of dmem_addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1190250740> | Input port bit <20> of dmem_addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1190250740> | Input port bit <19> of dmem_addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1190250740> | Input port bit <18> of dmem_addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1190250740> | Input port bit <17> of dmem_addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1190250740> | Input port bit <16> of dmem_addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1190250740> | Input port bit <15> of dmem_addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1190250740> | Input port bit <14> of dmem_addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1190250740> | Input port bit <13> of dmem_addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1190250740> | Input port bit <12> of dmem_addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1190250740> | Input port bit <11> of dmem_addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1190250740> | Input port bit <10> of dmem_addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1190250740> | Input port bit <9> of dmem_addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1190250740> | Input port bit <8> of dmem_addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1190250740> | Input port bit <7> of dmem_addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1190250740> | Input port bit <6> of dmem_addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1190250740> | Input port bit <5> of dmem_addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1190250740> | Input port bit <4> of dmem_addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1190250740> | Input port bit <3> of dmem_addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1190250740> | Input port bit <2> of dmem_addr_i[31:0] is unused</font>
@N: : <a href="f:\a\rtl\verilog\mem_module.v:96:7:96:19:@N::@XP_MSG">mem_module.v(96)</a><!@TM:1190250740> | Synthesizing module mem_addr_ctl
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="f:\a\rtl\verilog\mem_module.v:102:4:102:8:@W:CL118:@XP_MSG">mem_module.v(102)</a><!@TM:1190250740> | Latch generated from always block for signal wr_en[3:0], probably caused by a missing assignment in an if or case stmt</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1190250740> | Input port bit <31> of addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1190250740> | Input port bit <30> of addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1190250740> | Input port bit <29> of addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1190250740> | Input port bit <28> of addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1190250740> | Input port bit <27> of addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1190250740> | Input port bit <26> of addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1190250740> | Input port bit <25> of addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1190250740> | Input port bit <24> of addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1190250740> | Input port bit <23> of addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1190250740> | Input port bit <22> of addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1190250740> | Input port bit <21> of addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1190250740> | Input port bit <20> of addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1190250740> | Input port bit <19> of addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1190250740> | Input port bit <18> of addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1190250740> | Input port bit <17> of addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1190250740> | Input port bit <16> of addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1190250740> | Input port bit <15> of addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1190250740> | Input port bit <14> of addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1190250740> | Input port bit <13> of addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1190250740> | Input port bit <12> of addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1190250740> | Input port bit <11> of addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1190250740> | Input port bit <10> of addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1190250740> | Input port bit <9> of addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1190250740> | Input port bit <8> of addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1190250740> | Input port bit <7> of addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1190250740> | Input port bit <6> of addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1190250740> | Input port bit <5> of addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1190250740> | Input port bit <4> of addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1190250740> | Input port bit <3> of addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1190250740> | Input port bit <2> of addr_i[31:0] is unused</font>
@N: : <a href="f:\a\rtl\verilog\mem_module.v:199:7:199:18:@N::@XP_MSG">mem_module.v(199)</a><!@TM:1190250740> | Synthesizing module mem_din_ctl
@N: : <a href="f:\a\rtl\verilog\mem_module.v:130:7:130:19:@N::@XP_MSG">mem_module.v(130)</a><!@TM:1190250740> | Synthesizing module mem_dout_ctl
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="f:\a\rtl\verilog\mem_module.v:161:4:161:8:@W:CL118:@XP_MSG">mem_module.v(161)</a><!@TM:1190250740> | Latch generated from always block for signal dout[31:0], probably caused by a missing assignment in an if or case stmt</font>
@N: : <a href="f:\a\rtl\verilog\mem_module.v:4:7:4:17:@N::@XP_MSG">mem_module.v(4)</a><!@TM:1190250740> | Synthesizing module mem_module
@N: : <a href="f:\a\rtl\verilog\tools.v:3:7:3:14:@N::@XP_MSG">tools.v(3)</a><!@TM:1190250740> | Synthesizing module cal_cpi
@N: : <a href="f:\a\rtl\verilog\ctl_fsm.v:2:7:2:14:@N::@XP_MSG">ctl_fsm.v(2)</a><!@TM:1190250740> | Synthesizing module ctl_FSM
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="f:\a\rtl\verilog\ctl_fsm.v:58:8:58:12:@W:CL118:@XP_MSG">ctl_fsm.v(58)</a><!@TM:1190250740> | Latch generated from always block for signal zz_is_nop, probably caused by a missing assignment in an if or case stmt</font>
<font color=#A52A2A>@W:<a href="@W:CL113:@XP_HELP">CL113</a> : <a href="f:\a\rtl\verilog\ctl_fsm.v:58:8:58:12:@W:CL113:@XP_MSG">ctl_fsm.v(58)</a><!@TM:1190250740> | Feedback mux created for signal iack.</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="f:\a\rtl\verilog\ctl_fsm.v:58:8:58:12:@W:CL118:@XP_MSG">ctl_fsm.v(58)</a><!@TM:1190250740> | Latch generated from always block for signal iack, probably caused by a missing assignment in an if or case stmt</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="f:\a\rtl\verilog\ctl_fsm.v:58:8:58:12:@W:CL118:@XP_MSG">ctl_fsm.v(58)</a><!@TM:1190250740> | Latch generated from always block for signal next_delay_counter_Sreg0[5:0], probably caused by a missing assignment in an if or case stmt</font>
@N:<a href="@N:CL201:@XP_HELP">CL201</a> : <a href="f:\a\rtl\verilog\ctl_fsm.v:224:4:224:10:@N:CL201:@XP_MSG">ctl_fsm.v(224)</a><!@TM:1190250740> | Trying to extract state machine for register CurrState_Sreg0
Extracted state machine for register CurrState_Sreg0
State machine has 9 reachable states with original encodings of:
0000
0001
0010
0011
0100
0101
0110
0111
1000
@N: : <a href="f:\a\rtl\verilog\rf_components.v:50:7:50:13:@N::@XP_MSG">rf_components.v(50)</a><!@TM:1190250740> | Synthesizing module pc_gen
@N: : <a href="f:\a\rtl\verilog\rf_components.v:30:7:30:14:@N::@XP_MSG">rf_components.v(30)</a><!@TM:1190250740> | Synthesizing module compare
<font color=#A52A2A>@W:<a href="@W:CG133:@XP_HELP">CG133</a> : <a href="f:\a\rtl\verilog\rf_components.v:36:14:36:17:@W:CG133:@XP_MSG">rf_components.v(36)</a><!@TM:1190250740> | No assignment to sum</font>
@N: : <a href="f:\a\rtl\verilog\rf_components.v:2:7:2:10:@N::@XP_MSG">rf_components.v(2)</a><!@TM:1190250740> | Synthesizing module ext
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\rf_components.v:3:21:3:26:@W::@XP_MSG">rf_components.v(3)</a><!@TM:1190250740> | Input port bit <31> of ins_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\rf_components.v:3:21:3:26:@W::@XP_MSG">rf_components.v(3)</a><!@TM:1190250740> | Input port bit <30> of ins_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\rf_components.v:3:21:3:26:@W::@XP_MSG">rf_components.v(3)</a><!@TM:1190250740> | Input port bit <29> of ins_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\rf_components.v:3:21:3:26:@W::@XP_MSG">rf_components.v(3)</a><!@TM:1190250740> | Input port bit <28> of ins_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\rf_components.v:3:21:3:26:@W::@XP_MSG">rf_components.v(3)</a><!@TM:1190250740> | Input port bit <27> of ins_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\rf_components.v:3:21:3:26:@W::@XP_MSG">rf_components.v(3)</a><!@TM:1190250740> | Input port bit <26> of ins_i[31:0] is unused</font>
@N: : <a href="f:\a\rtl\verilog\tools.v:104:7:104:22:@N::@XP_MSG">tools.v(104)</a><!@TM:1190250740> | Synthesizing module r32_reg_clr_cls
@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="f:\a\rtl\verilog\tools.v:104:167:104:172:@N:CG179:@XP_MSG">tools.v(104)</a><!@TM:1190250740> | Removing redundant assignment
@N: : <a href="f:\a\rtl\verilog\tools.v:30:7:30:11:@N::@XP_MSG">tools.v(30)</a><!@TM:1190250740> | Synthesizing module jack
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\tools.v:31:21:31:26:@W::@XP_MSG">tools.v(31)</a><!@TM:1190250740> | Input port bit <31> of ins_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\tools.v:31:21:31:26:@W::@XP_MSG">tools.v(31)</a><!@TM:1190250740> | Input port bit <30> of ins_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\tools.v:31:21:31:26:@W::@XP_MSG">tools.v(31)</a><!@TM:1190250740> | Input port bit <29> of ins_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\tools.v:31:21:31:26:@W::@XP_MSG">tools.v(31)</a><!@TM:1190250740> | Input port bit <28> of ins_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\tools.v:31:21:31:26:@W::@XP_MSG">tools.v(31)</a><!@TM:1190250740> | Input port bit <27> of ins_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\tools.v:31:21:31:26:@W::@XP_MSG">tools.v(31)</a><!@TM:1190250740> | Input port bit <26> of ins_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\tools.v:31:21:31:26:@W::@XP_MSG">tools.v(31)</a><!@TM:1190250740> | Input port bit <10> of ins_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\tools.v:31:21:31:26:@W::@XP_MSG">tools.v(31)</a><!@TM:1190250740> | Input port bit <9> of ins_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\tools.v:31:21:31:26:@W::@XP_MSG">tools.v(31)</a><!@TM:1190250740> | Input port bit <8> of ins_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\tools.v:31:21:31:26:@W::@XP_MSG">tools.v(31)</a><!@TM:1190250740> | Input port bit <7> of ins_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\tools.v:31:21:31:26:@W::@XP_MSG">tools.v(31)</a><!@TM:1190250740> | Input port bit <6> of ins_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\tools.v:31:21:31:26:@W::@XP_MSG">tools.v(31)</a><!@TM:1190250740> | Input port bit <5> of ins_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\tools.v:31:21:31:26:@W::@XP_MSG">tools.v(31)</a><!@TM:1190250740> | Input port bit <4> of ins_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\tools.v:31:21:31:26:@W::@XP_MSG">tools.v(31)</a><!@TM:1190250740> | Input port bit <3> of ins_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\tools.v:31:21:31:26:@W::@XP_MSG">tools.v(31)</a><!@TM:1190250740> | Input port bit <2> of ins_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\tools.v:31:21:31:26:@W::@XP_MSG">tools.v(31)</a><!@TM:1190250740> | Input port bit <1> of ins_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\tools.v:31:21:31:26:@W::@XP_MSG">tools.v(31)</a><!@TM:1190250740> | Input port bit <0> of ins_i[31:0] is unused</font>
@N: : <a href="f:\a\rtl\verilog\tools.v:64:7:64:13:@N::@XP_MSG">tools.v(64)</a><!@TM:1190250740> | Synthesizing module rd_sel
@N: : <a href="f:\a\rtl\verilog\rf_components.v:90:7:90:16:@N::@XP_MSG">rf_components.v(90)</a><!@TM:1190250740> | Synthesizing module reg_array
@N:<a href="@N:CL134:@XP_HELP">CL134</a> : <a href="f:\a\rtl\verilog\rf_components.v:140:4:140:10:@N:CL134:@XP_MSG">rf_components.v(140)</a><!@TM:1190250740> | Found RAM reg_bank, depth=32, width=32
@N:<a href="@N:CL134:@XP_HELP">CL134</a> : <a href="f:\a\rtl\verilog\rf_components.v:140:4:140:10:@N:CL134:@XP_MSG">rf_components.v(140)</a><!@TM:1190250740> | Found RAM reg_bank, depth=32, width=32
@N: : <a href="f:\a\rtl\verilog\forward.v:25:7:25:14:@N::@XP_MSG">forward.v(25)</a><!@TM:1190250740> | Synthesizing module fwd_mux
@N: : <a href="f:\a\rtl\verilog\rf_stage.v:3:7:3:15:@N::@XP_MSG">rf_stage.v(3)</a><!@TM:1190250740> | Synthesizing module rf_stage
<font color=#A52A2A>@W:<a href="@W:CS149:@XP_HELP">CS149</a> : <a href="f:\a\rtl\verilog\rf_stage.v:91:24:91:30:@W:CS149:@XP_MSG">rf_stage.v(91)</a><!@TM:1190250740> | Port width mismatch for port ins_no. Formal has width 101, Actual 1</font>
<font color=#A52A2A>@W:<a href="@W:CS149:@XP_HELP">CS149</a> : <a href="f:\a\rtl\verilog\rf_stage.v:90:24:90:30:@W:CS149:@XP_MSG">rf_stage.v(90)</a><!@TM:1190250740> | Port width mismatch for port clk_no. Formal has width 101, Actual 1</font>
<font color=#A52A2A>@W:<a href="@W:CL168:@XP_HELP">CL168</a> : <a href="f:\a\rtl\verilog\rf_stage.v:87:12:87:19:@W:CL168:@XP_MSG">rf_stage.v(87)</a><!@TM:1190250740> | Pruning instance CAL_CPI - not in use ...</font>
@N: : <a href="f:\a\rtl\verilog\exec_stage.v:521:7:521:16:@N::@XP_MSG">exec_stage.v(521)</a><!@TM:1190250740> | Synthesizing module muldiv_ff
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="f:\a\rtl\verilog\exec_stage.v:572:4:572:10:@W:CL169:@XP_MSG">exec_stage.v(572)</a><!@TM:1190250740> | Pruning Register LAST_CYCLE_DEAL_SECTION.eqnop2 </font>
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="f:\a\rtl\verilog\exec_stage.v:572:4:572:10:@W:CL169:@XP_MSG">exec_stage.v(572)</a><!@TM:1190250740> | Pruning Register START_SECTION.over[32:0] </font>
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="f:\a\rtl\verilog\exec_stage.v:572:4:572:10:@W:CL169:@XP_MSG">exec_stage.v(572)</a><!@TM:1190250740> | Pruning Register LAST_CYCLE_DEAL_SECTION.LAST_CYCLE_DEAL_SECTION_DEFAULT.op1s_eq_op2s </font>
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="f:\a\rtl\verilog\exec_stage.v:572:4:572:10:@W:CL169:@XP_MSG">exec_stage.v(572)</a><!@TM:1190250740> | Pruning Register LAST_CYCLE_DEAL_SECTION.eqz </font>
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="f:\a\rtl\verilog\exec_stage.v:572:4:572:10:@W:CL169:@XP_MSG">exec_stage.v(572)</a><!@TM:1190250740> | Pruning Register LAST_CYCLE_DEAL_SECTION.LAST_CYCLE_DEAL_SECTION_DEFAULT.op1s_eq_h64 </font>
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="f:\a\rtl\verilog\exec_stage.v:572:4:572:10:@W:CL169:@XP_MSG">exec_stage.v(572)</a><!@TM:1190250740> | Pruning Register LAST_CYCLE_DEAL_SECTION.eqop2 </font>
@N: : <a href="f:\a\rtl\verilog\exec_stage.v:233:7:233:10:@N::@XP_MSG">exec_stage.v(233)</a><!@TM:1190250740> | Synthesizing module alu
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\exec_stage.v:238:16:238:17:@W::@XP_MSG">exec_stage.v(238)</a><!@TM:1190250740> | No assignment to wire c</font>
@N: : <a href="f:\a\rtl\verilog\exec_stage.v:266:4:266:15:@N::@XP_MSG">exec_stage.v(266)</a><!@TM:1190250740> | Synthesizing module shifter_tak
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\exec_stage.v:270:25:270:52:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1190250740> | Input port bit <31> of shift_amount[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\exec_stage.v:270:25:270:52:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1190250740> | Input port bit <30> of shift_amount[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\exec_stage.v:270:25:270:52:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1190250740> | Input port bit <29> of shift_amount[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\exec_stage.v:270:25:270:52:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1190250740> | Input port bit <28> of shift_amount[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\exec_stage.v:270:25:270:52:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1190250740> | Input port bit <27> of shift_amount[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\exec_stage.v:270:25:270:52:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1190250740> | Input port bit <26> of shift_amount[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\exec_stage.v:270:25:270:52:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1190250740> | Input port bit <25> of shift_amount[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\exec_stage.v:270:25:270:52:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1190250740> | Input port bit <24> of shift_amount[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\exec_stage.v:270:25:270:52:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1190250740> | Input port bit <23> of shift_amount[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\exec_stage.v:270:25:270:52:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1190250740> | Input port bit <22> of shift_amount[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\exec_stage.v:270:25:270:52:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1190250740> | Input port bit <21> of shift_amount[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\exec_stage.v:270:25:270:52:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1190250740> | Input port bit <20> of shift_amount[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\exec_stage.v:270:25:270:52:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1190250740> | Input port bit <19> of shift_amount[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\exec_stage.v:270:25:270:52:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1190250740> | Input port bit <18> of shift_amount[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\exec_stage.v:270:25:270:52:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1190250740> | Input port bit <17> of shift_amount[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\exec_stage.v:270:25:270:52:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1190250740> | Input port bit <16> of shift_amount[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\exec_stage.v:270:25:270:52:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1190250740> | Input port bit <15> of shift_amount[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\exec_stage.v:270:25:270:52:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1190250740> | Input port bit <14> of shift_amount[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\exec_stage.v:270:25:270:52:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1190250740> | Input port bit <13> of shift_amount[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\exec_stage.v:270:25:270:52:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1190250740> | Input port bit <12> of shift_amount[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\exec_stage.v:270:25:270:52:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1190250740> | Input port bit <11> of shift_amount[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\exec_stage.v:270:25:270:52:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1190250740> | Input port bit <10> of shift_amount[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\exec_stage.v:270:25:270:52:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1190250740> | Input port bit <9> of shift_amount[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\exec_stage.v:270:25:270:52:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1190250740> | Input port bit <8> of shift_amount[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\exec_stage.v:270:25:270:52:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1190250740> | Input port bit <7> of shift_amount[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\exec_stage.v:270:25:270:52:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1190250740> | Input port bit <6> of shift_amount[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\exec_stage.v:270:25:270:52:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1190250740> | Input port bit <5> of shift_amount[31:0] is unused</font>
@N: : <a href="f:\a\rtl\verilog\exec_stage.v:138:7:138:14:@N::@XP_MSG">exec_stage.v(138)</a><!@TM:1190250740> | Synthesizing module big_alu
@N: : <a href="f:\a\rtl\verilog\tools.v:22:7:22:12:@N::@XP_MSG">tools.v(22)</a><!@TM:1190250740> | Synthesizing module add32
@N: : <a href="f:\a\rtl\verilog\exec_stage.v:188:7:188:15:@N::@XP_MSG">exec_stage.v(188)</a><!@TM:1190250740> | Synthesizing module alu_muxa
@N: : <a href="f:\a\rtl\verilog\exec_stage.v:212:7:212:15:@N::@XP_MSG">exec_stage.v(212)</a><!@TM:1190250740> | Synthesizing module alu_muxb
@N: : <a href="f:\a\rtl\verilog\tools.v:150:7:150:14:@N::@XP_MSG">tools.v(150)</a><!@TM:1190250740> | Synthesizing module r32_reg
@N: : <a href="f:\a\rtl\verilog\tools.v:173:7:173:18:@N::@XP_MSG">tools.v(173)</a><!@TM:1190250740> | Synthesizing module r32_reg_cls
@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="f:\a\rtl\verilog\tools.v:173:132:173:137:@N:CG179:@XP_MSG">tools.v(173)</a><!@TM:1190250740> | Removing redundant assignment
@N: : <a href="f:\a\rtl\verilog\exec_stage.v:3:7:3:17:@N::@XP_MSG">exec_stage.v(3)</a><!@TM:1190250740> | Synthesizing module exec_stage
@N: : <a href="f:\a\rtl\verilog\tools.v:54:7:54:11:@N::@XP_MSG">tools.v(54)</a><!@TM:1190250740> | Synthesizing module or32
@N: : <a href="f:\a\rtl\verilog\decode_pipe.v:2:7:2:14:@N::@XP_MSG">decode_pipe.v(2)</a><!@TM:1190250740> | Synthesizing module decoder
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:CL118:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Latch generated from always block for signal alu_func[4:0], probably caused by a missing assignment in an if or case stmt</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:CL118:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Latch generated from always block for signal pc_gen_ctl[2:0], probably caused by a missing assignment in an if or case stmt</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:CL118:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Latch generated from always block for signal fsm_dly[2:0], probably caused by a missing assignment in an if or case stmt</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:CL118:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Latch generated from always block for signal ext_ctl[2:0], probably caused by a missing assignment in an if or case stmt</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:CL118:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Latch generated from always block for signal rd_sel[1:0], probably caused by a missing assignment in an if or case stmt</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:CL118:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Latch generated from always block for signal muxb_ctl[1:0], probably caused by a missing assignment in an if or case stmt</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:CL118:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Latch generated from always block for signal muxa_ctl[1:0], probably caused by a missing assignment in an if or case stmt</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:CL118:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Latch generated from always block for signal alu_we[0], probably caused by a missing assignment in an if or case stmt</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:CL118:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Latch generated from always block for signal dmem_ctl[3:0], probably caused by a missing assignment in an if or case stmt</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:CL118:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Latch generated from always block for signal cmp_ctl[2:0], probably caused by a missing assignment in an if or case stmt</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:CL118:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Latch generated from always block for signal wb_we[0], probably caused by a missing assignment in an if or case stmt</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:CL118:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Latch generated from always block for signal wb_mux[0], probably caused by a missing assignment in an if or case stmt</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\decode_pipe.v:3:20:3:25:@W::@XP_MSG">decode_pipe.v(3)</a><!@TM:1190250740> | Input port bit <15> of ins_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\decode_pipe.v:3:20:3:25:@W::@XP_MSG">decode_pipe.v(3)</a><!@TM:1190250740> | Input port bit <14> of ins_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\decode_pipe.v:3:20:3:25:@W::@XP_MSG">decode_pipe.v(3)</a><!@TM:1190250740> | Input port bit <13> of ins_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\decode_pipe.v:3:20:3:25:@W::@XP_MSG">decode_pipe.v(3)</a><!@TM:1190250740> | Input port bit <12> of ins_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\decode_pipe.v:3:20:3:25:@W::@XP_MSG">decode_pipe.v(3)</a><!@TM:1190250740> | Input port bit <11> of ins_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\decode_pipe.v:3:20:3:25:@W::@XP_MSG">decode_pipe.v(3)</a><!@TM:1190250740> | Input port bit <10> of ins_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\decode_pipe.v:3:20:3:25:@W::@XP_MSG">decode_pipe.v(3)</a><!@TM:1190250740> | Input port bit <9> of ins_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\decode_pipe.v:3:20:3:25:@W::@XP_MSG">decode_pipe.v(3)</a><!@TM:1190250740> | Input port bit <8> of ins_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\decode_pipe.v:3:20:3:25:@W::@XP_MSG">decode_pipe.v(3)</a><!@TM:1190250740> | Input port bit <7> of ins_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\decode_pipe.v:3:20:3:25:@W::@XP_MSG">decode_pipe.v(3)</a><!@TM:1190250740> | Input port bit <6> of ins_i[31:0] is unused</font>
@N: : <a href="f:\a\rtl\verilog\tools.v:90:7:90:27:@N::@XP_MSG">tools.v(90)</a><!@TM:1190250740> | Synthesizing module muxb_ctl_reg_clr_cls
@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="f:\a\rtl\verilog\tools.v:90:202:90:212:@N:CG179:@XP_MSG">tools.v(90)</a><!@TM:1190250740> | Removing redundant assignment
@N: : <a href="f:\a\rtl\verilog\tools.v:94:7:94:29:@N::@XP_MSG">tools.v(94)</a><!@TM:1190250740> | Synthesizing module wb_mux_ctl_reg_clr_cls
@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="f:\a\rtl\verilog\tools.v:94:216:94:228:@N:CG179:@XP_MSG">tools.v(94)</a><!@TM:1190250740> | Removing redundant assignment
@N: : <a href="f:\a\rtl\verilog\tools.v:95:7:95:24:@N::@XP_MSG">tools.v(95)</a><!@TM:1190250740> | Synthesizing module wb_we_reg_clr_cls
@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="f:\a\rtl\verilog\tools.v:95:181:95:188:@N:CG179:@XP_MSG">tools.v(95)</a><!@TM:1190250740> | Removing redundant assignment
@N: : <a href="f:\a\rtl\verilog\tools.v:141:7:141:16:@N::@XP_MSG">tools.v(141)</a><!@TM:1190250740> | Synthesizing module wb_we_reg
@N: : <a href="f:\a\rtl\verilog\tools.v:117:7:117:25:@N::@XP_MSG">tools.v(117)</a><!@TM:1190250740> | Synthesizing module wb_mux_ctl_reg_clr
@N: : <a href="f:\a\rtl\verilog\tools.v:113:7:113:23:@N::@XP_MSG">tools.v(113)</a><!@TM:1190250740> | Synthesizing module muxb_ctl_reg_clr
@N: : <a href="f:\a\rtl\verilog\tools.v:116:7:116:23:@N::@XP_MSG">tools.v(116)</a><!@TM:1190250740> | Synthesizing module dmem_ctl_reg_clr
@N: : <a href="f:\a\rtl\verilog\tools.v:114:7:114:23:@N::@XP_MSG">tools.v(114)</a><!@TM:1190250740> | Synthesizing module alu_func_reg_clr
@N: : <a href="f:\a\rtl\verilog\tools.v:112:7:112:23:@N::@XP_MSG">tools.v(112)</a><!@TM:1190250740> | Synthesizing module muxa_ctl_reg_clr
@N: : <a href="f:\a\rtl\verilog\tools.v:140:7:140:21:@N::@XP_MSG">tools.v(140)</a><!@TM:1190250740> | Synthesizing module wb_mux_ctl_reg
@N: : <a href="f:\a\rtl\verilog\tools.v:118:7:118:20:@N::@XP_MSG">tools.v(118)</a><!@TM:1190250740> | Synthesizing module wb_we_reg_clr
@N: : <a href="f:\a\rtl\verilog\tools.v:86:7:86:26:@N::@XP_MSG">tools.v(86)</a><!@TM:1190250740> | Synthesizing module cmp_ctl_reg_clr_cls
@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="f:\a\rtl\verilog\tools.v:86:195:86:204:@N:CG179:@XP_MSG">tools.v(86)</a><!@TM:1190250740> | Removing redundant assignment
@N: : <a href="f:\a\rtl\verilog\tools.v:115:7:115:21:@N::@XP_MSG">tools.v(115)</a><!@TM:1190250740> | Synthesizing module alu_we_reg_clr
@N: : <a href="f:\a\rtl\verilog\tools.v:91:7:91:27:@N::@XP_MSG">tools.v(91)</a><!@TM:1190250740> | Synthesizing module alu_func_reg_clr_cls
@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="f:\a\rtl\verilog\tools.v:91:202:91:212:@N:CG179:@XP_MSG">tools.v(91)</a><!@TM:1190250740> | Removing redundant assignment
@N: : <a href="f:\a\rtl\verilog\tools.v:93:7:93:27:@N::@XP_MSG">tools.v(93)</a><!@TM:1190250740> | Synthesizing module dmem_ctl_reg_clr_cls
@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="f:\a\rtl\verilog\tools.v:93:202:93:212:@N:CG179:@XP_MSG">tools.v(93)</a><!@TM:1190250740> | Removing redundant assignment
@N: : <a href="f:\a\rtl\verilog\tools.v:84:7:84:26:@N::@XP_MSG">tools.v(84)</a><!@TM:1190250740> | Synthesizing module ext_ctl_reg_clr_cls
@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="f:\a\rtl\verilog\tools.v:84:195:84:204:@N:CG179:@XP_MSG">tools.v(84)</a><!@TM:1190250740> | Removing redundant assignment
@N: : <a href="f:\a\rtl\verilog\tools.v:85:7:85:25:@N::@XP_MSG">tools.v(85)</a><!@TM:1190250740> | Synthesizing module rd_sel_reg_clr_cls
@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="f:\a\rtl\verilog\tools.v:85:188:85:196:@N:CG179:@XP_MSG">tools.v(85)</a><!@TM:1190250740> | Removing redundant assignment
@N: : <a href="f:\a\rtl\verilog\tools.v:92:7:92:25:@N::@XP_MSG">tools.v(92)</a><!@TM:1190250740> | Synthesizing module alu_we_reg_clr_cls
@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="f:\a\rtl\verilog\tools.v:92:188:92:196:@N:CG179:@XP_MSG">tools.v(92)</a><!@TM:1190250740> | Removing redundant assignment
@N: : <a href="f:\a\rtl\verilog\tools.v:89:7:89:27:@N::@XP_MSG">tools.v(89)</a><!@TM:1190250740> | Synthesizing module muxa_ctl_reg_clr_cls
@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="f:\a\rtl\verilog\tools.v:89:202:89:212:@N:CG179:@XP_MSG">tools.v(89)</a><!@TM:1190250740> | Removing redundant assignment
@N: : <a href="f:\a\rtl\verilog\tools.v:87:7:87:29:@N::@XP_MSG">tools.v(87)</a><!@TM:1190250740> | Synthesizing module pc_gen_ctl_reg_clr_cls
@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="f:\a\rtl\verilog\tools.v:87:216:87:228:@N:CG179:@XP_MSG">tools.v(87)</a><!@TM:1190250740> | Removing redundant assignment
@N: : <a href="f:\a\rtl\verilog\tools.v:139:7:139:19:@N::@XP_MSG">tools.v(139)</a><!@TM:1190250740> | Synthesizing module dmem_ctl_reg
@N: : <a href="f:\a\rtl\verilog\decode_pipe.v:1090:7:1090:20:@N::@XP_MSG">decode_pipe.v(1090)</a><!@TM:1190250740> | Synthesizing module pipelinedregs
@N: : <a href="f:\a\rtl\verilog\decode_pipe.v:1419:7:1419:18:@N::@XP_MSG">decode_pipe.v(1419)</a><!@TM:1190250740> | Synthesizing module decode_pipe
@N: : <a href="f:\a\rtl\verilog\forward.v:12:7:12:19:@N::@XP_MSG">forward.v(12)</a><!@TM:1190250740> | Synthesizing module forward_node
@N: : <a href="f:\a\rtl\verilog\forward.v:4:7:4:16:@N::@XP_MSG">forward.v(4)</a><!@TM:1190250740> | Synthesizing module fw_latch5
@N: : <a href="f:\a\rtl\verilog\forward.v:41:7:41:14:@N::@XP_MSG">forward.v(41)</a><!@TM:1190250740> | Synthesizing module forward
@N: : <a href="f:\a\rtl\verilog\tools.v:149:7:149:13:@N::@XP_MSG">tools.v(149)</a><!@TM:1190250740> | Synthesizing module r5_reg
@N: : <a href="f:\a\rtl\verilog\tools.v:43:7:43:13:@N::@XP_MSG">tools.v(43)</a><!@TM:1190250740> | Synthesizing module wb_mux
@N: : <a href="f:\a\rtl\verilog\mips_core.v:3:7:3:16:@N::@XP_MSG">mips_core.v(3)</a><!@TM:1190250740> | Synthesizing module mips_core
@N: : <a href="f:\a\rtl\verilog\mips_uart.v:210:7:210:16:@N::@XP_MSG">mips_uart.v(210)</a><!@TM:1190250740> | Synthesizing module uart_read
@N:<a href="@N:CL201:@XP_HELP">CL201</a> : <a href="f:\a\rtl\verilog\mips_uart.v:274:4:274:10:@N:CL201:@XP_MSG">mips_uart.v(274)</a><!@TM:1190250740> | Trying to extract state machine for register ua_state
Extracted state machine for register ua_state
State machine has 5 reachable states with original encodings of:
000
001
010
011
100
@N: : <a href="f:\a\rtl\verilog\mips_uart.v:3:7:3:12:@N::@XP_MSG">mips_uart.v(3)</a><!@TM:1190250740> | Synthesizing module rxd_d
@N: : <a href="c:\program files\synplicity\fpga_81\lib\altera\altera_mf.v:3709:7:3709:13:@N::@XP_MSG">altera_mf.v(3709)</a><!@TM:1190250740> | Synthesizing module scfifo
lpm_width=32'b00000000000000000000000000001000
lpm_widthu=32'b00000000000000000000000000001001
lpm_numwords=32'b00000000000000000000001000000000
lpm_showahead=24'b010011110100011001000110
intended_device_family=56'b01000011011110010110001101101100011011110110111001100101
almost_full_value=32'b00000000000000000000000000000000
almost_empty_value=32'b00000000000000000000000000000000
underflow_checking=16'b0100111101001110
overflow_checking=16'b0100111101001110
allow_rwcycle_when_full=24'b010011110100011001000110
lpm_hint=152'b01010010010000010100110101011111010000100100110001001111010000110100101101011111010101000101100101010000010001010011110101000001010101010101010001001111
use_eab=16'b0100111101001110
add_ram_output_register=24'b010011110100011001000110
maximum_depth=32'b00000000000000000000000000000000
lpm_type=48'b011100110110001101100110011010010110011001101111
Generated name = scfifo_Z6
@N: : <a href="f:\a\rtl\verilog\altera\fifo512_cyclone.v:42:7:42:22:@N::@XP_MSG">fifo512_cyclone.v(42)</a><!@TM:1190250740> | Synthesizing module fifo512_cyclone
@N: : <a href="f:\a\rtl\verilog\mips_uart.v:70:7:70:17:@N::@XP_MSG">mips_uart.v(70)</a><!@TM:1190250740> | Synthesizing module uart_write
<font color=#A52A2A>@W:<a href="@W:CG133:@XP_HELP">CG133</a> : <a href="f:\a\rtl\verilog\mips_uart.v:94:9:94:21:@W:CG133:@XP_MSG">mips_uart.v(94)</a><!@TM:1190250740> | No assignment to write_done_n</font>
@N:<a href="@N:CL201:@XP_HELP">CL201</a> : <a href="f:\a\rtl\verilog\mips_uart.v:168:4:168:10:@N:CL201:@XP_MSG">mips_uart.v(168)</a><!@TM:1190250740> | Trying to extract state machine for register ua_state
Extracted state machine for register ua_state
State machine has 8 reachable states with original encodings of:
000
001
010
011
100
101
110
111
@N: : <a href="f:\a\rtl\verilog\mips_uart.v:12:7:12:12:@N::@XP_MSG">mips_uart.v(12)</a><!@TM:1190250740> | Synthesizing module uart0
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mips_uart.v:38:9:38:18:@W::@XP_MSG">mips_uart.v(38)</a><!@TM:1190250740> | No assignment to wire w_rxd_clr</font>
@N: : <a href="f:\a\rtl\verilog\dvc.v:52:7:52:17:@N::@XP_MSG">dvc.v(52)</a><!@TM:1190250740> | Synthesizing module seg7led_cv
@N: : <a href="f:\a\rtl\verilog\dvc.v:43:7:43:12:@N::@XP_MSG">dvc.v(43)</a><!@TM:1190250740> | Synthesizing module tmr_d
@N: : <a href="f:\a\rtl\verilog\dvc.v:3:7:3:11:@N::@XP_MSG">dvc.v(3)</a><!@TM:1190250740> | Synthesizing module tmr0
@N: : <a href="f:\a\rtl\verilog\mips_dvc.v:3:7:3:15:@N::@XP_MSG">mips_dvc.v(3)</a><!@TM:1190250740> | Synthesizing module mips_dvc
@N: : <a href="f:\a\rtl\verilog\mips_sys.v:4:7:4:15:@N::@XP_MSG">mips_sys.v(4)</a><!@TM:1190250740> | Synthesizing module mips_sys
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mips_sys.v:78:16:78:25:@W::@XP_MSG">mips_sys.v(78)</a><!@TM:1190250740> | No assignment to wire data2core</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mips_sys.v:79:16:79:24:@W::@XP_MSG">mips_sys.v(79)</a><!@TM:1190250740> | No assignment to wire data2mem</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mips_sys.v:80:16:80:24:@W::@XP_MSG">mips_sys.v(80)</a><!@TM:1190250740> | No assignment to wire ins2core</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mips_sys.v:81:16:81:24:@W::@XP_MSG">mips_sys.v(81)</a><!@TM:1190250740> | No assignment to wire mem_Addr</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mips_sys.v:82:16:82:18:@W::@XP_MSG">mips_sys.v(82)</a><!@TM:1190250740> | No assignment to wire pc</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mips_sys.v:83:15:83:20:@W::@XP_MSG">mips_sys.v(83)</a><!@TM:1190250740> | No assignment to wire wr_en</font>
@N: : <a href="f:\a\rtl\verilog\altera\mips_top.v:2:7:2:15:@N::@XP_MSG">mips_top.v(2)</a><!@TM:1190250740> | Synthesizing module mips_top
@END
Process took 0h:00m:33s realtime, 0h:00m:33s cputime
# Thu Sep 20 09:10:32 2007
###########################################################[
Version 8.1
<a name=mapperReport8>Synplicity Altera Technology Mapper, Version 8.1.0, Build 539R, Built May 6 2005
Copyright (C) 1994-2005, Synplicity Inc. All Rights Reserved
Automatic dissolve at startup in view:work.mem_array(verilog) of ram0(ram2048x8_0)
Automatic dissolve at startup in view:work.mem_array(verilog) of ram1(ram2048x8_1)
Automatic dissolve at startup in view:work.mem_array(verilog) of ram2(ram2048x8_2)
Automatic dissolve at startup in view:work.mem_array(verilog) of ram3(ram2048x8_3)
Automatic dissolve at startup in view:work.mem_module(verilog) of i_mem_din_ctl(mem_din_ctl)
Automatic dissolve at startup in view:work.mem_module(verilog) of i_mem_addr_ctl(mem_addr_ctl)
Automatic dissolve at startup in view:work.mem_module(verilog) of dmem_ctl_post(infile_dmem_ctl_reg)
Automatic dissolve at startup in view:work.rf_stage(verilog) of rs_fwd_rs(fwd_mux)
Automatic dissolve at startup in view:work.rf_stage(verilog) of rf_fwd_rt(fwd_mux)
Automatic dissolve at startup in view:work.rf_stage(verilog) of jack2(jack)
Automatic dissolve at startup in view:work.rf_stage(verilog) of jack1(jack)
Automatic dissolve at startup in view:work.rf_stage(verilog) of ins_reg(r32_reg_clr_cls)
Automatic dissolve at startup in view:work.rf_stage(verilog) of i_pc_gen(pc_gen)
Automatic dissolve at startup in view:work.exec_stage(verilog) of spc(r32_reg_cls)
Automatic dissolve at startup in view:work.exec_stage(verilog) of pc_nxt(r32_reg)
Automatic dissolve at startup in view:work.exec_stage(verilog) of i_alu_muxb(alu_muxb)
Automatic dissolve at startup in view:work.exec_stage(verilog) of i_alu_muxa(alu_muxa)
Automatic dissolve at startup in view:work.exec_stage(verilog) of dmem_fw_mux(fwd_mux)
Automatic dissolve at startup in view:work.exec_stage(verilog) of add4(add32)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U9(dmem_ctl_reg)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U8(pc_gen_ctl_reg_clr_cls)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U7(muxa_ctl_reg_clr_cls)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U6(alu_we_reg_clr_cls)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U5(rd_sel_reg_clr_cls)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U4(ext_ctl_reg_clr_cls)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U3(dmem_ctl_reg_clr_cls)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U26(alu_func_reg_clr_cls)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U24(alu_we_reg_clr)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U22(wb_we_reg)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U21(wb_mux_ctl_reg)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U20(wb_we_reg)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U2(cmp_ctl_reg_clr_cls)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U19(wb_we_reg_clr)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U18(wb_mux_ctl_reg)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U17(muxa_ctl_reg_clr)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U16(alu_func_reg_clr)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U15(dmem_ctl_reg_clr)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U14(muxb_ctl_reg_clr)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U13(wb_mux_ctl_reg_clr)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U12(wb_we_reg)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U11(wb_we_reg_clr_cls)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U10(wb_mux_ctl_reg_clr_cls)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U1(muxb_ctl_reg_clr_cls)
Automatic dissolve at startup in view:work.decode_pipe(verilog) of pipereg(pipelinedregs)
Automatic dissolve at startup in view:work.forward(verilog) of fw_reg_rnt(fw_latch5)
Automatic dissolve at startup in view:work.forward(verilog) of fw_reg_rns(fw_latch5)
Automatic dissolve at startup in view:work.mips_core(verilog) of wb_mux(wb_mux)
Automatic dissolve at startup in view:work.mips_core(verilog) of rt_reg(r32_reg)
Automatic dissolve at startup in view:work.mips_core(verilog) of rs_reg(r32_reg)
Automatic dissolve at startup in view:work.mips_core(verilog) of rnd_pass2(r5_reg)
Automatic dissolve at startup in view:work.mips_core(verilog) of rnd_pass1(r5_reg)
Automatic dissolve at startup in view:work.mips_core(verilog) of rnd_pass0(r5_reg)
Automatic dissolve at startup in view:work.mips_core(verilog) of pc(r32_reg)
Automatic dissolve at startup in view:work.mips_core(verilog) of ext_reg(r32_reg)
Automatic dissolve at startup in view:work.mips_core(verilog) of cop_dout_reg(r32_reg)
Automatic dissolve at startup in view:work.mips_core(verilog) of cop_data_reg(r32_reg)
Automatic dissolve at startup in view:work.mips_core(verilog) of cop_data_or(or32)
Automatic dissolve at startup in view:work.mips_core(verilog) of alu_pass1(r32_reg)
Automatic dissolve at startup in view:work.mips_core(verilog) of alu_pass0(r32_reg)
Automatic dissolve at startup in view:work.mips_core(verilog) of iexec_stage(exec_stage)
Automatic dissolve at startup in view:work.mips_core(verilog) of iRF_stage(rf_stage)
Automatic dissolve at startup in view:work.mips_core(verilog) of MEM_CTL(mem_module)
Automatic dissolve at startup in view:work.uart_write(verilog) of fifo(fifo512_cyclone)
Automatic dissolve at startup in view:work.uart0(verilog) of rxd_rdy_hold_lw(rxd_d)
Automatic dissolve at startup in view:work.tmr0(verilog) of itmr_d(tmr_d)
Automatic dissolve at startup in view:work.mips_top(verilog) of ram_8k(mem_array)
Automatic dissolve at startup in view:work.mips_top(verilog) of Ipll(mips_pll)
Warning: Found 30 combinational loops!
Each loop is reported with an instance in the loop
and nets connected to that instance.
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping at net fsm_dly_1[0]</font>
1) instance work.decoder(verilog)-fsm_dly_1[0], output net "fsm_dly_1[0]" in work.decoder(verilog)
input nets to instance:
net "fsm_dly_2[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping at net fsm_dly_1[1]</font>
2) instance work.decoder(verilog)-fsm_dly_1[2:1], output net "fsm_dly_1[1]" in work.decoder(verilog)
input nets to instance:
net "fsm_dly_2[1]" in work.decoder(verilog)
net "fsm_dly_2[2]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping at net fsm_dly_1[2]</font>
3) instance work.decoder(verilog)-fsm_dly_1[2:1], output net "fsm_dly_1[2]" in work.decoder(verilog)
input nets to instance:
net "fsm_dly_2[1]" in work.decoder(verilog)
net "fsm_dly_2[2]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping at net ext_ctl_1[0]</font>
4) instance work.decoder(verilog)-ext_ctl_1[0], output net "ext_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "ext_ctl_2[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping at net ext_ctl_1[1]</font>
5) instance work.decoder(verilog)-ext_ctl_1[1], output net "ext_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "ext_ctl_2[1]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping at net ext_ctl_1[2]</font>
6) instance work.decoder(verilog)-ext_ctl_1[2], output net "ext_ctl_1[2]" in work.decoder(verilog)
input nets to instance:
net "ext_ctl_2[2]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping at net rd_sel_1[0]</font>
7) instance work.decoder(verilog)-rd_sel_1[0], output net "rd_sel_1[0]" in work.decoder(verilog)
input nets to instance:
net "rd_sel_2[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping at net rd_sel_1[1]</font>
8) instance work.decoder(verilog)-rd_sel_1[1], output net "rd_sel_1[1]" in work.decoder(verilog)
input nets to instance:
net "rd_sel_2[1]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_22" in work.decoder(verilog)
net "wb_we315" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping at net cmp_ctl_1[0]</font>
9) instance work.decoder(verilog)-cmp_ctl_1[0], output net "cmp_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "cmp_ctl_2[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping at net cmp_ctl_1[1]</font>
10) instance work.decoder(verilog)-cmp_ctl_1[1], output net "cmp_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "cmp_ctl_2[1]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping at net cmp_ctl_1[2]</font>
11) instance work.decoder(verilog)-cmp_ctl_1[2], output net "cmp_ctl_1[2]" in work.decoder(verilog)
input nets to instance:
net "cmp_ctl_2[2]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping at net pc_gen_ctl_1[0]</font>
12) instance work.decoder(verilog)-pc_gen_ctl_1[0], output net "pc_gen_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "pc_gen_ctl_2[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping at net pc_gen_ctl_1[1]</font>
13) instance work.decoder(verilog)-pc_gen_ctl_1[1], output net "pc_gen_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "pc_gen_ctl_2[1]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping at net pc_gen_ctl_1[2]</font>
14) instance work.decoder(verilog)-pc_gen_ctl_1[2], output net "pc_gen_ctl_1[2]" in work.decoder(verilog)
input nets to instance:
net "pc_gen_ctl_2[2]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping at net muxa_ctl_1[0]</font>
15) instance work.decoder(verilog)-muxa_ctl_1[0], output net "muxa_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "muxa_ctl_2[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping at net muxa_ctl_1[1]</font>
16) instance work.decoder(verilog)-muxa_ctl_1[1], output net "muxa_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "muxa_ctl_2[1]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping at net muxb_ctl_1[0]</font>
17) instance work.decoder(verilog)-muxb_ctl_1[0], output net "muxb_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "muxb_ctl_2[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping at net muxb_ctl_1[1]</font>
18) instance work.decoder(verilog)-muxb_ctl_1[1], output net "muxb_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "muxb_ctl_2[1]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping at net alu_func_1[0]</font>
19) instance work.decoder(verilog)-alu_func_1[0], output net "alu_func_1[0]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping at net alu_func_1[1]</font>
20) instance work.decoder(verilog)-alu_func_1[1], output net "alu_func_1[1]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[1]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping at net alu_func_1[2]</font>
21) instance work.decoder(verilog)-alu_func_1[2], output net "alu_func_1[2]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[2]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping at net alu_func_1[3]</font>
22) instance work.decoder(verilog)-alu_func_1[3], output net "alu_func_1[3]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[3]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping at net alu_func_1[4]</font>
23) instance work.decoder(verilog)-alu_func_1[4], output net "alu_func_1[4]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[4]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping at net dmem_ctl_1[0]</font>
24) instance work.decoder(verilog)-dmem_ctl_1[0], output net "dmem_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "dmem_ctl_2[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping at net dmem_ctl_1[1]</font>
25) instance work.decoder(verilog)-dmem_ctl_1[1], output net "dmem_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "dmem_ctl_2[1]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_22" in work.decoder(verilog)
net "wb_we315" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping at net dmem_ctl_1[2]</font>
26) instance work.decoder(verilog)-dmem_ctl_1[2], output net "dmem_ctl_1[2]" in work.decoder(verilog)
input nets to instance:
net "dmem_ctl_2[2]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_24" in work.decoder(verilog)
net "un1_ins_i_15" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping at net dmem_ctl_1[3]</font>
27) instance work.decoder(verilog)-dmem_ctl_1[3], output net "dmem_ctl_1[3]" in work.decoder(verilog)
input nets to instance:
net "dmem_ctl_2[3]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping at net alu_we[0]</font>
28) instance work.decoder(verilog)-alu_we[0], output net "alu_we[0]" in work.decoder(verilog)
input nets to instance:
net "alu_we_1[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping at net wb_mux[0]</font>
29) instance work.decoder(verilog)-wb_mux[0], output net "wb_mux[0]" in work.decoder(verilog)
input nets to instance:
net "wb_mux_1[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping at net wb_we[0]</font>
30) instance work.decoder(verilog)-wb_we[0], output net "wb_we[0]" in work.decoder(verilog)
input nets to instance:
net "wb_we_1[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
End of loops
@N:<a href="@N:MT204:@XP_HELP">MT204</a> : <!@TM:1190250740> | Autoconstrain Mode is ON
RTL optimization done.
Warning: Found 30 combinational loops!
Each loop is reported with an instance in the loop
and nets connected to that instance.
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping at net fsm_dly_1[0]</font>
1) instance work.decoder(verilog)-fsm_dly_1[0], output net "fsm_dly_1[0]" in work.decoder(verilog)
input nets to instance:
net "fsm_dly_2[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping at net fsm_dly_1[1]</font>
2) instance work.decoder(verilog)-fsm_dly_1[2:1], output net "fsm_dly_1[1]" in work.decoder(verilog)
input nets to instance:
net "fsm_dly_2[1]" in work.decoder(verilog)
net "fsm_dly_2[2]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping at net fsm_dly_1[2]</font>
3) instance work.decoder(verilog)-fsm_dly_1[2:1], output net "fsm_dly_1[2]" in work.decoder(verilog)
input nets to instance:
net "fsm_dly_2[1]" in work.decoder(verilog)
net "fsm_dly_2[2]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping at net wb_mux_1[0]</font>
4) instance work.decoder(verilog)-wb_mux_1[0], output net "wb_mux_1[0]" in work.decoder(verilog)
input nets to instance:
net "un1_alu_we_3_sqmuxa_4" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "un1_alu_we_3_sqmuxa" in work.decoder(verilog)
net "wb_mux[0]" in work.decoder(verilog)
net "un1_wb_we307" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping at net wb_we_1[0]</font>
5) instance work.decoder(verilog)-wb_we_1[0], output net "wb_we_1[0]" in work.decoder(verilog)
input nets to instance:
net "un1_alu_we_3_sqmuxa_3" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "un1_alu_we_3_sqmuxa" in work.decoder(verilog)
net "wb_we[0]" in work.decoder(verilog)
net "un1_wb_we304" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping at net alu_func_2[0]</font>
6) instance work.decoder(verilog)-alu_func_2[4:0], output net "alu_func_2[0]" in work.decoder(verilog)
input nets to instance:
net "alu_func_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_1_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_3_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_4_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_5_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_6_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_7_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_8_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_9_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_10_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_11_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_12_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_13_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_14_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_15_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_16_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_17_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_18_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_19_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_20_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_21_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_22_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_23_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_24_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_25_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_26_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_27_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_28_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_3_sqmuxa" in work.decoder(verilog)
net "alu_func_1[0]" in work.decoder(verilog)
net "alu_func_1[1]" in work.decoder(verilog)
net "alu_func_1[2]" in work.decoder(verilog)
net "alu_func_1[3]" in work.decoder(verilog)
net "alu_func_1[4]" in work.decoder(verilog)
net "alu_we_4_sqmuxa" in work.decoder(verilog)
net "alu_func_1[0]" in work.decoder(verilog)
net "alu_func_1[1]" in work.decoder(verilog)
net "alu_func_1[2]" in work.decoder(verilog)
net "alu_func_1[3]" in work.decoder(verilog)
net "alu_func_1[4]" in work.decoder(verilog)
net "wb_we292" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we293" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we294" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we295" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we296" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we297" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we298" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we299" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we300" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we301" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we302" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we303" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we304" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we305" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
net "alu_func_1[0]" in work.decoder(verilog)
net "alu_func_1[1]" in work.decoder(verilog)
net "alu_func_1[2]" in work.decoder(verilog)
net "alu_func_1[3]" in work.decoder(verilog)
net "alu_func_1[4]" in work.decoder(verilog)
net "wb_we307" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we308" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we309" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we310" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we311" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we312" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping at net alu_func_2[1]</font>
7) instance work.decoder(verilog)-alu_func_2[4:0], output net "alu_func_2[1]" in work.decoder(verilog)
input nets to instance:
net "alu_func_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_1_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_3_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_4_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_5_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_6_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_7_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_8_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_9_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_10_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_11_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_12_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_13_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_14_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_15_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_16_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_17_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_18_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_19_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_20_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_21_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_22_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_23_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_24_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_25_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_26_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_27_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_28_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_3_sqmuxa" in work.decoder(verilog)
net "alu_func_1[0]" in work.decoder(verilog)
net "alu_func_1[1]" in work.decoder(verilog)
net "alu_func_1[2]" in work.decoder(verilog)
net "alu_func_1[3]" in work.decoder(verilog)
net "alu_func_1[4]" in work.decoder(verilog)
net "alu_we_4_sqmuxa" in work.decoder(verilog)
net "alu_func_1[0]" in work.decoder(verilog)
net "alu_func_1[1]" in work.decoder(verilog)
net "alu_func_1[2]" in work.decoder(verilog)
net "alu_func_1[3]" in work.decoder(verilog)
net "alu_func_1[4]" in work.decoder(verilog)
net "wb_we292" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we293" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we294" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we295" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we296" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we297" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we298" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we299" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we300" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we301" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we302" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we303" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we304" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we305" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
net "alu_func_1[0]" in work.decoder(verilog)
net "alu_func_1[1]" in work.decoder(verilog)
net "alu_func_1[2]" in work.decoder(verilog)
net "alu_func_1[3]" in work.decoder(verilog)
net "alu_func_1[4]" in work.decoder(verilog)
net "wb_we307" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we308" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we309" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we310" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we311" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we312" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping at net alu_func_2[2]</font>
8) instance work.decoder(verilog)-alu_func_2[4:0], output net "alu_func_2[2]" in work.decoder(verilog)
input nets to instance:
net "alu_func_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_1_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_3_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_4_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_5_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_6_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_7_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_8_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_9_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_10_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_11_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_12_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_13_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_14_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_15_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_16_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_17_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_18_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_19_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_20_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_21_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_22_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_23_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_24_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_25_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_26_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_27_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_28_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_3_sqmuxa" in work.decoder(verilog)
net "alu_func_1[0]" in work.decoder(verilog)
net "alu_func_1[1]" in work.decoder(verilog)
net "alu_func_1[2]" in work.decoder(verilog)
net "alu_func_1[3]" in work.decoder(verilog)
net "alu_func_1[4]" in work.decoder(verilog)
net "alu_we_4_sqmuxa" in work.decoder(verilog)
net "alu_func_1[0]" in work.decoder(verilog)
net "alu_func_1[1]" in work.decoder(verilog)
net "alu_func_1[2]" in work.decoder(verilog)
net "alu_func_1[3]" in work.decoder(verilog)
net "alu_func_1[4]" in work.decoder(verilog)
net "wb_we292" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we293" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we294" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we295" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we296" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we297" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we298" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we299" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we300" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we301" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we302" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we303" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we304" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we305" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
net "alu_func_1[0]" in work.decoder(verilog)
net "alu_func_1[1]" in work.decoder(verilog)
net "alu_func_1[2]" in work.decoder(verilog)
net "alu_func_1[3]" in work.decoder(verilog)
net "alu_func_1[4]" in work.decoder(verilog)
net "wb_we307" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we308" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we309" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we310" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we311" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we312" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping at net alu_func_2[3]</font>
9) instance work.decoder(verilog)-alu_func_2[4:0], output net "alu_func_2[3]" in work.decoder(verilog)
input nets to instance:
net "alu_func_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_1_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_3_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_4_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_5_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_6_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_7_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_8_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_9_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_10_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_11_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_12_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_13_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_14_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_15_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_16_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_17_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_18_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_19_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_20_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_21_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_22_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_23_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_24_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_25_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_26_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_27_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_28_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_3_sqmuxa" in work.decoder(verilog)
net "alu_func_1[0]" in work.decoder(verilog)
net "alu_func_1[1]" in work.decoder(verilog)
net "alu_func_1[2]" in work.decoder(verilog)
net "alu_func_1[3]" in work.decoder(verilog)
net "alu_func_1[4]" in work.decoder(verilog)
net "alu_we_4_sqmuxa" in work.decoder(verilog)
net "alu_func_1[0]" in work.decoder(verilog)
net "alu_func_1[1]" in work.decoder(verilog)
net "alu_func_1[2]" in work.decoder(verilog)
net "alu_func_1[3]" in work.decoder(verilog)
net "alu_func_1[4]" in work.decoder(verilog)
net "wb_we292" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we293" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we294" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we295" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we296" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we297" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we298" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we299" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we300" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we301" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we302" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we303" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we304" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we305" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
net "alu_func_1[0]" in work.decoder(verilog)
net "alu_func_1[1]" in work.decoder(verilog)
net "alu_func_1[2]" in work.decoder(verilog)
net "alu_func_1[3]" in work.decoder(verilog)
net "alu_func_1[4]" in work.decoder(verilog)
net "wb_we307" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we308" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we309" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we310" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we311" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we312" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping at net alu_func_2[4]</font>
10) instance work.decoder(verilog)-alu_func_2[4:0], output net "alu_func_2[4]" in work.decoder(verilog)
input nets to instance:
net "alu_func_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_1_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_3_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_4_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_5_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_6_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_7_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_8_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_9_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_10_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_11_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_12_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_13_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_14_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_15_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_16_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_17_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_18_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_19_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_20_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_21_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_22_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_23_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_24_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_25_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_26_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_27_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_28_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_3_sqmuxa" in work.decoder(verilog)
net "alu_func_1[0]" in work.decoder(verilog)
net "alu_func_1[1]" in work.decoder(verilog)
net "alu_func_1[2]" in work.decoder(verilog)
net "alu_func_1[3]" in work.decoder(verilog)
net "alu_func_1[4]" in work.decoder(verilog)
net "alu_we_4_sqmuxa" in work.decoder(verilog)
net "alu_func_1[0]" in work.decoder(verilog)
net "alu_func_1[1]" in work.decoder(verilog)
net "alu_func_1[2]" in work.decoder(verilog)
net "alu_func_1[3]" in work.decoder(verilog)
net "alu_func_1[4]" in work.decoder(verilog)
net "wb_we292" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we293" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we294" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we295" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we296" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we297" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we298" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we299" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we300" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we301" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we302" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we303" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we304" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we305" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
net "alu_func_1[0]" in work.decoder(verilog)
net "alu_func_1[1]" in work.decoder(verilog)
net "alu_func_1[2]" in work.decoder(verilog)
net "alu_func_1[3]" in work.decoder(verilog)
net "alu_func_1[4]" in work.decoder(verilog)
net "wb_we307" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we308" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we309" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we310" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we311" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we312" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping at net alu_we_1[0]</font>
11) instance work.decoder(verilog)-alu_we_1[0], output net "alu_we_1[0]" in work.decoder(verilog)
input nets to instance:
net "alu_func_0_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_1_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_2_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_3_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_4_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_5_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_6_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_7_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_8_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_9_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_10_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_11_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_12_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_13_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_14_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_15_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_16_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_17_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_18_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_19_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_20_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_21_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_22_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_23_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_24_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_25_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_26_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_27_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_28_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_3_sqmuxa" in work.decoder(verilog)
net "alu_we[0]" in work.decoder(verilog)
net "alu_we_4_sqmuxa" in work.decoder(verilog)
net "alu_we[0]" in work.decoder(verilog)
net "wb_we292" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we293" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we294" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we295" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we296" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we297" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we298" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we299" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we300" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we301" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we302" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we303" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we304" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we305" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
net "alu_we[0]" in work.decoder(verilog)
net "wb_we307" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we308" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we309" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we310" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we311" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we312" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping at net ext_ctl_2[0]</font>
12) instance work.decoder(verilog)-ext_ctl_2[2:0], output net "ext_ctl_2[0]" in work.decoder(verilog)
input nets to instance:
net "alu_func_0_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_1_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_2_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_3_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_4_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_5_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_6_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_7_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_8_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_9_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_10_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_11_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_12_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_13_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_14_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_15_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_16_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_17_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_18_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_19_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_20_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_21_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_22_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_23_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_24_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_25_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_26_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_27_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_28_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_1_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_3_sqmuxa" in work.decoder(verilog)
net "ext_ctl_1[0]" in work.decoder(verilog)
net "ext_ctl_1[1]" in work.decoder(verilog)
net "ext_ctl_1[2]" in work.decoder(verilog)
net "alu_we_4_sqmuxa" in work.decoder(verilog)
net "ext_ctl_1[0]" in work.decoder(verilog)
net "ext_ctl_1[1]" in work.decoder(verilog)
net "ext_ctl_1[2]" in work.decoder(verilog)
net "wb_we292" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we293" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we294" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we295" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we296" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we297" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we298" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we299" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we300" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we301" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we302" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we303" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we304" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we305" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
net "ext_ctl_1[0]" in work.decoder(verilog)
net "ext_ctl_1[1]" in work.decoder(verilog)
net "ext_ctl_1[2]" in work.decoder(verilog)
net "wb_we307" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we308" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we309" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we310" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we311" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we312" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping at net ext_ctl_2[1]</font>
13) instance work.decoder(verilog)-ext_ctl_2[2:0], output net "ext_ctl_2[1]" in work.decoder(verilog)
input nets to instance:
net "alu_func_0_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_1_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_2_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_3_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_4_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_5_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_6_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_7_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_8_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_9_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_10_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_11_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_12_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_13_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_14_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_15_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_16_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_17_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_18_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_19_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_20_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_21_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_22_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_23_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_24_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_25_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_26_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_27_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_28_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_1_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_3_sqmuxa" in work.decoder(verilog)
net "ext_ctl_1[0]" in work.decoder(verilog)
net "ext_ctl_1[1]" in work.decoder(verilog)
net "ext_ctl_1[2]" in work.decoder(verilog)
net "alu_we_4_sqmuxa" in work.decoder(verilog)
net "ext_ctl_1[0]" in work.decoder(verilog)
net "ext_ctl_1[1]" in work.decoder(verilog)
net "ext_ctl_1[2]" in work.decoder(verilog)
net "wb_we292" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we293" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we294" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we295" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we296" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we297" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we298" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we299" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we300" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we301" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we302" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we303" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we304" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we305" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
net "ext_ctl_1[0]" in work.decoder(verilog)
net "ext_ctl_1[1]" in work.decoder(verilog)
net "ext_ctl_1[2]" in work.decoder(verilog)
net "wb_we307" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we308" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we309" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we310" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we311" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we312" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping at net ext_ctl_2[2]</font>
14) instance work.decoder(verilog)-ext_ctl_2[2:0], output net "ext_ctl_2[2]" in work.decoder(verilog)
input nets to instance:
net "alu_func_0_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_1_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_2_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_3_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_4_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_5_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_6_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_7_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_8_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_9_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_10_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_11_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_12_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_13_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_14_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_15_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_16_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_17_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_18_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_19_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_20_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_21_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_22_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_23_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_24_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_25_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_26_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_27_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_28_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_1_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_3_sqmuxa" in work.decoder(verilog)
net "ext_ctl_1[0]" in work.decoder(verilog)
net "ext_ctl_1[1]" in work.decoder(verilog)
net "ext_ctl_1[2]" in work.decoder(verilog)
net "alu_we_4_sqmuxa" in work.decoder(verilog)
net "ext_ctl_1[0]" in work.decoder(verilog)
net "ext_ctl_1[1]" in work.decoder(verilog)
net "ext_ctl_1[2]" in work.decoder(verilog)
net "wb_we292" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we293" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we294" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we295" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we296" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we297" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we298" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we299" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we300" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we301" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we302" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we303" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we304" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we305" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
net "ext_ctl_1[0]" in work.decoder(verilog)
net "ext_ctl_1[1]" in work.decoder(verilog)
net "ext_ctl_1[2]" in work.decoder(verilog)
net "wb_we307" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we308" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we309" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we310" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we311" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we312" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping at net muxa_ctl_2[0]</font>
15) instance work.decoder(verilog)-muxa_ctl_2[1:0], output net "muxa_ctl_2[0]" in work.decoder(verilog)
input nets to instance:
net "alu_func_0_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_1_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_2_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_3_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_4_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_5_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_6_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_7_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_8_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_9_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_10_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_11_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_12_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_13_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_14_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_15_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_16_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_17_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_18_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_19_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_20_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_21_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_22_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_23_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_24_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_25_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_26_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_27_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_28_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_3_sqmuxa" in work.decoder(verilog)
net "muxa_ctl_1[0]" in work.decoder(verilog)
net "muxa_ctl_1[1]" in work.decoder(verilog)
net "alu_we_4_sqmuxa" in work.decoder(verilog)
net "muxa_ctl_1[0]" in work.decoder(verilog)
net "muxa_ctl_1[1]" in work.decoder(verilog)
net "wb_we292" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we293" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we294" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we295" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we296" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we297" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we298" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we299" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we300" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we301" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we302" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we303" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we304" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we305" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
net "muxa_ctl_1[0]" in work.decoder(verilog)
net "muxa_ctl_1[1]" in work.decoder(verilog)
net "wb_we307" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we308" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we309" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we310" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we311" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we312" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping at net muxa_ctl_2[1]</font>
16) instance work.decoder(verilog)-muxa_ctl_2[1:0], output net "muxa_ctl_2[1]" in work.decoder(verilog)
input nets to instance:
net "alu_func_0_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_1_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_2_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_3_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_4_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_5_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_6_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_7_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_8_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_9_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_10_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_11_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_12_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_13_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_14_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_15_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_16_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_17_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_18_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_19_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_20_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_21_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_22_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_23_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_24_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_25_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_26_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_27_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_28_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_3_sqmuxa" in work.decoder(verilog)
net "muxa_ctl_1[0]" in work.decoder(verilog)
net "muxa_ctl_1[1]" in work.decoder(verilog)
net "alu_we_4_sqmuxa" in work.decoder(verilog)
net "muxa_ctl_1[0]" in work.decoder(verilog)
net "muxa_ctl_1[1]" in work.decoder(verilog)
net "wb_we292" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we293" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we294" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we295" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we296" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we297" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we298" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we299" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we300" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we301" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we302" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we303" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we304" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we305" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
net "muxa_ctl_1[0]" in work.decoder(verilog)
net "muxa_ctl_1[1]" in work.decoder(verilog)
net "wb_we307" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we308" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we309" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we310" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we311" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we312" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping at net muxb_ctl_2[0]</font>
17) instance work.decoder(verilog)-muxb_ctl_2[1:0], output net "muxb_ctl_2[0]" in work.decoder(verilog)
input nets to instance:
net "alu_func_0_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_1_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_2_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_3_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_4_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_5_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_6_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_7_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_8_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_9_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_10_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_11_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_12_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_13_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_14_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_15_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_16_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_17_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_18_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_19_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_20_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_21_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_22_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_23_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_24_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_25_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_26_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_27_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_28_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_3_sqmuxa" in work.decoder(verilog)
net "muxb_ctl_1[0]" in work.decoder(verilog)
net "muxb_ctl_1[1]" in work.decoder(verilog)
net "alu_we_4_sqmuxa" in work.decoder(verilog)
net "muxb_ctl_1[0]" in work.decoder(verilog)
net "muxb_ctl_1[1]" in work.decoder(verilog)
net "wb_we292" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we293" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we294" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we295" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we296" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we297" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we298" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we299" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we300" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we301" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we302" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we303" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we304" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we305" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
net "muxb_ctl_1[0]" in work.decoder(verilog)
net "muxb_ctl_1[1]" in work.decoder(verilog)
net "wb_we307" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we308" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we309" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we310" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we311" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we312" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping at net muxb_ctl_2[1]</font>
18) instance work.decoder(verilog)-muxb_ctl_2[1:0], output net "muxb_ctl_2[1]" in work.decoder(verilog)
input nets to instance:
net "alu_func_0_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_1_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_2_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_3_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_4_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_5_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_6_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_7_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_8_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_9_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_10_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_11_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_12_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_13_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_14_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_15_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_16_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_17_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_18_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_19_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_20_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_21_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_22_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_23_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_24_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_25_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_26_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_27_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_28_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_3_sqmuxa" in work.decoder(verilog)
net "muxb_ctl_1[0]" in work.decoder(verilog)
net "muxb_ctl_1[1]" in work.decoder(verilog)
net "alu_we_4_sqmuxa" in work.decoder(verilog)
net "muxb_ctl_1[0]" in work.decoder(verilog)
net "muxb_ctl_1[1]" in work.decoder(verilog)
net "wb_we292" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we293" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we294" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we295" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we296" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we297" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we298" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we299" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we300" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we301" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we302" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we303" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we304" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we305" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
net "muxb_ctl_1[0]" in work.decoder(verilog)
net "muxb_ctl_1[1]" in work.decoder(verilog)
net "wb_we307" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we308" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we309" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we310" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we311" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we312" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping at net pc_gen_ctl_2[0]</font>
19) instance work.decoder(verilog)-pc_gen_ctl_2[2:0], output net "pc_gen_ctl_2[0]" in work.decoder(verilog)
input nets to instance:
net "alu_func_0_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_1_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_2_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_3_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_4_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_5_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_6_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_7_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_8_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_9_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_10_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_11_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_12_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_13_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_14_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_15_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_16_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_17_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_18_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_19_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_20_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_21_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_22_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_23_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_24_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_25_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_26_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_27_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_28_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_1_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_3_sqmuxa" in work.decoder(verilog)
net "pc_gen_ctl_1[0]" in work.decoder(verilog)
net "pc_gen_ctl_1[1]" in work.decoder(verilog)
net "pc_gen_ctl_1[2]" in work.decoder(verilog)
net "alu_we_4_sqmuxa" in work.decoder(verilog)
net "pc_gen_ctl_1[0]" in work.decoder(verilog)
net "pc_gen_ctl_1[1]" in work.decoder(verilog)
net "pc_gen_ctl_1[2]" in work.decoder(verilog)
net "wb_we292" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we293" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we294" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we295" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we296" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we297" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we298" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we299" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we300" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we301" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we302" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we303" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we304" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we305" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
net "pc_gen_ctl_1[0]" in work.decoder(verilog)
net "pc_gen_ctl_1[1]" in work.decoder(verilog)
net "pc_gen_ctl_1[2]" in work.decoder(verilog)
net "wb_we307" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we308" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we309" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we310" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we311" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we312" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping at net pc_gen_ctl_2[1]</font>
20) instance work.decoder(verilog)-pc_gen_ctl_2[2:0], output net "pc_gen_ctl_2[1]" in work.decoder(verilog)
input nets to instance:
net "alu_func_0_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_1_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_2_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_3_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_4_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_5_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_6_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_7_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_8_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_9_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_10_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_11_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_12_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_13_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_14_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_15_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_16_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_17_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_18_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_19_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_20_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_21_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_22_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_23_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_24_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_25_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_26_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_27_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_28_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_1_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_3_sqmuxa" in work.decoder(verilog)
net "pc_gen_ctl_1[0]" in work.decoder(verilog)
net "pc_gen_ctl_1[1]" in work.decoder(verilog)
net "pc_gen_ctl_1[2]" in work.decoder(verilog)
net "alu_we_4_sqmuxa" in work.decoder(verilog)
net "pc_gen_ctl_1[0]" in work.decoder(verilog)
net "pc_gen_ctl_1[1]" in work.decoder(verilog)
net "pc_gen_ctl_1[2]" in work.decoder(verilog)
net "wb_we292" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we293" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we294" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we295" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we296" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we297" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we298" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we299" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we300" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we301" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we302" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we303" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we304" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we305" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
net "pc_gen_ctl_1[0]" in work.decoder(verilog)
net "pc_gen_ctl_1[1]" in work.decoder(verilog)
net "pc_gen_ctl_1[2]" in work.decoder(verilog)
net "wb_we307" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we308" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we309" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we310" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we311" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we312" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping at net pc_gen_ctl_2[2]</font>
21) instance work.decoder(verilog)-pc_gen_ctl_2[2:0], output net "pc_gen_ctl_2[2]" in work.decoder(verilog)
input nets to instance:
net "alu_func_0_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_1_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_2_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_3_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_4_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_5_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_6_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_7_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_8_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_9_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_10_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_11_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_12_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_13_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_14_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_15_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_16_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_17_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_18_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_19_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_20_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_21_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_22_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_23_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_24_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_25_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_26_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_27_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_28_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_1_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_3_sqmuxa" in work.decoder(verilog)
net "pc_gen_ctl_1[0]" in work.decoder(verilog)
net "pc_gen_ctl_1[1]" in work.decoder(verilog)
net "pc_gen_ctl_1[2]" in work.decoder(verilog)
net "alu_we_4_sqmuxa" in work.decoder(verilog)
net "pc_gen_ctl_1[0]" in work.decoder(verilog)
net "pc_gen_ctl_1[1]" in work.decoder(verilog)
net "pc_gen_ctl_1[2]" in work.decoder(verilog)
net "wb_we292" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we293" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we294" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we295" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we296" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we297" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we298" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we299" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we300" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we301" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we302" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we303" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we304" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we305" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
net "pc_gen_ctl_1[0]" in work.decoder(verilog)
net "pc_gen_ctl_1[1]" in work.decoder(verilog)
net "pc_gen_ctl_1[2]" in work.decoder(verilog)
net "wb_we307" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we308" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we309" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we310" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we311" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we312" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping at net rd_sel_2[0]</font>
22) instance work.decoder(verilog)-rd_sel_2[1:0], output net "rd_sel_2[0]" in work.decoder(verilog)
input nets to instance:
net "alu_func_0_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_1_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_2_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_3_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_4_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_5_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_6_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_7_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_8_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_9_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_10_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_11_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_12_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_13_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_14_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_15_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_16_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_17_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_18_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_19_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_20_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_21_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_22_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_23_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_24_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_25_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_26_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_27_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_28_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_3_sqmuxa" in work.decoder(verilog)
net "rd_sel_1[0]" in work.decoder(verilog)
net "rd_sel_1[1]" in work.decoder(verilog)
net "alu_we_4_sqmuxa" in work.decoder(verilog)
net "rd_sel_1[0]" in work.decoder(verilog)
net "rd_sel_1[1]" in work.decoder(verilog)
net "wb_we292" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we293" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we294" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we295" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we296" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we297" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we298" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we299" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we300" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we301" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we302" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we303" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we304" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we305" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
net "rd_sel_1[0]" in work.decoder(verilog)
net "rd_sel_1[1]" in work.decoder(verilog)
net "wb_we307" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we308" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we309" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we310" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we311" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we312" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping at net rd_sel_2[1]</font>
23) instance work.decoder(verilog)-rd_sel_2[1:0], output net "rd_sel_2[1]" in work.decoder(verilog)
input nets to instance:
net "alu_func_0_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_1_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_2_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_3_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_4_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_5_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_6_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_7_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_8_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_9_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_10_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_11_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_12_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_13_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_14_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_15_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_16_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_17_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_18_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_19_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_20_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_21_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_22_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_23_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_24_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_25_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_26_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_27_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_28_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_3_sqmuxa" in work.decoder(verilog)
net "rd_sel_1[0]" in work.decoder(verilog)
net "rd_sel_1[1]" in work.decoder(verilog)
net "alu_we_4_sqmuxa" in work.decoder(verilog)
net "rd_sel_1[0]" in work.decoder(verilog)
net "rd_sel_1[1]" in work.decoder(verilog)
net "wb_we292" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we293" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we294" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we295" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we296" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we297" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we298" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we299" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we300" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we301" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we302" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we303" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we304" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we305" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
net "rd_sel_1[0]" in work.decoder(verilog)
net "rd_sel_1[1]" in work.decoder(verilog)
net "wb_we307" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we308" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we309" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we310" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we311" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we312" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping at net cmp_ctl_2[0]</font>
24) instance work.decoder(verilog)-cmp_ctl_2[2:0], output net "cmp_ctl_2[0]" in work.decoder(verilog)
input nets to instance:
net "un1_wb_we294_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_1_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "un1_alu_we_3_sqmuxa" in work.decoder(verilog)
net "cmp_ctl_1[0]" in work.decoder(verilog)
net "cmp_ctl_1[1]" in work.decoder(verilog)
net "cmp_ctl_1[2]" in work.decoder(verilog)
net "wb_we294" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we295" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we296" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we297" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping at net cmp_ctl_2[1]</font>
25) instance work.decoder(verilog)-cmp_ctl_2[2:0], output net "cmp_ctl_2[1]" in work.decoder(verilog)
input nets to instance:
net "un1_wb_we294_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_1_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "un1_alu_we_3_sqmuxa" in work.decoder(verilog)
net "cmp_ctl_1[0]" in work.decoder(verilog)
net "cmp_ctl_1[1]" in work.decoder(verilog)
net "cmp_ctl_1[2]" in work.decoder(verilog)
net "wb_we294" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we295" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we296" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we297" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping at net cmp_ctl_2[2]</font>
26) instance work.decoder(verilog)-cmp_ctl_2[2:0], output net "cmp_ctl_2[2]" in work.decoder(verilog)
input nets to instance:
net "un1_wb_we294_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_1_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "un1_alu_we_3_sqmuxa" in work.decoder(verilog)
net "cmp_ctl_1[0]" in work.decoder(verilog)
net "cmp_ctl_1[1]" in work.decoder(verilog)
net "cmp_ctl_1[2]" in work.decoder(verilog)
net "wb_we294" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we295" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we296" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we297" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping at net dmem_ctl_2[0]</font>
27) instance work.decoder(verilog)-dmem_ctl_2[3:0], output net "dmem_ctl_2[0]" in work.decoder(verilog)
input nets to instance:
net "un1_wb_we307_2" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "un1_alu_we_3_sqmuxa" in work.decoder(verilog)
net "dmem_ctl_1[0]" in work.decoder(verilog)
net "dmem_ctl_1[1]" in work.decoder(verilog)
net "dmem_ctl_1[2]" in work.decoder(verilog)
net "dmem_ctl_1[3]" in work.decoder(verilog)
net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we307" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we308" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we310" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we311" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we312" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping at net dmem_ctl_2[1]</font>
28) instance work.decoder(verilog)-dmem_ctl_2[3:0], output net "dmem_ctl_2[1]" in work.decoder(verilog)
input nets to instance:
net "un1_wb_we307_2" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "un1_alu_we_3_sqmuxa" in work.decoder(verilog)
net "dmem_ctl_1[0]" in work.decoder(verilog)
net "dmem_ctl_1[1]" in work.decoder(verilog)
net "dmem_ctl_1[2]" in work.decoder(verilog)
net "dmem_ctl_1[3]" in work.decoder(verilog)
net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we307" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we308" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we310" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we311" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we312" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping at net dmem_ctl_2[2]</font>
29) instance work.decoder(verilog)-dmem_ctl_2[3:0], output net "dmem_ctl_2[2]" in work.decoder(verilog)
input nets to instance:
net "un1_wb_we307_2" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "un1_alu_we_3_sqmuxa" in work.decoder(verilog)
net "dmem_ctl_1[0]" in work.decoder(verilog)
net "dmem_ctl_1[1]" in work.decoder(verilog)
net "dmem_ctl_1[2]" in work.decoder(verilog)
net "dmem_ctl_1[3]" in work.decoder(verilog)
net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we307" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we308" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we310" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we311" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we312" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping at net dmem_ctl_2[3]</font>
30) instance work.decoder(verilog)-dmem_ctl_2[3:0], output net "dmem_ctl_2[3]" in work.decoder(verilog)
input nets to instance:
net "un1_wb_we307_2" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "un1_alu_we_3_sqmuxa" in work.decoder(verilog)
net "dmem_ctl_1[0]" in work.decoder(verilog)
net "dmem_ctl_1[1]" in work.decoder(verilog)
net "dmem_ctl_1[2]" in work.decoder(verilog)
net "dmem_ctl_1[3]" in work.decoder(verilog)
net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we307" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we308" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we310" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we311" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we312" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
End of loops
<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="f:\a\rtl\verilog\mem_module.v:88:4:88:10:@W:BN132:@XP_MSG">mem_module.v(88)</a><!@TM:1190250740> | Removing sequential instance isys.mips_core.MEM_CTL.dmem_ctl_post.byte_addr_o[0], because it is equivalent to instance isys.mips_core.alu_pass0.r32_o[0]</font>
<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="f:\a\rtl\verilog\mem_module.v:88:4:88:10:@W:BN132:@XP_MSG">mem_module.v(88)</a><!@TM:1190250740> | Removing sequential instance isys.mips_core.MEM_CTL.dmem_ctl_post.byte_addr_o[1], because it is equivalent to instance isys.mips_core.alu_pass0.r32_o[1]</font>
Encoding state machine work.ctl_FSM(verilog)-CurrState_Sreg0[8:0]
original code -> new code
0000 -> 000000000
0001 -> 000000011
0010 -> 000000101
0011 -> 000001001
0100 -> 000010001
0101 -> 000100001
0110 -> 001000001
0111 -> 010000001
1000 -> 100000001
<font color=#A52A2A>@W:<a href="@W:FA140:@XP_HELP">FA140</a> : <a href="f:\a\rtl\verilog\ctl_fsm.v:126:16:126:17:@W:FA140:@XP_MSG">ctl_fsm.v(126)</a><!@TM:1190250740> | DFF work.ctl_FSM(verilog)-CurrState_Sreg0[5] is stuck at '0', removing ... </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\ctl_fsm.v:126:16:126:17:@W:BN116:@XP_MSG">ctl_fsm.v(126)</a><!@TM:1190250740> | Removing sequential instance CurrState_Sreg0[5] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:MO127:@XP_HELP">MO127</a> : <a href="f:\a\rtl\verilog\ctl_fsm.v:58:8:58:12:@W:MO127:@XP_MSG">ctl_fsm.v(58)</a><!@TM:1190250740> | Sequential instance isys.mips_core.iRF_stage.MIAN_FSM.iack_1 has been reduced to a combinational gate by constant propagation</font>
@N: : <a href="f:\a\rtl\verilog\exec_stage.v:572:4:572:10:@N::@XP_MSG">exec_stage.v(572)</a><!@TM:1190250740> | Found counter in view:work.muldiv_ff(verilog) inst count[5:0]
Warning: Found 30 combinational loops!
Each loop is reported with an instance in the loop
and nets connected to that instance.
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
1) instance fsm_dly_2[2:0] work.decoder(verilog)-fsm_dly_2[2:0], output net "fsm_dly_2[0]" in work.decoder(verilog)
input nets to instance:
net "alu_func_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_1_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_3_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_4_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_5_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_6_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_7_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_8_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_9_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_10_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_11_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_12_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_13_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_14_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_15_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_16_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_17_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_18_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_19_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_20_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_21_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_22_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_23_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_24_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_25_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_26_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_27_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_28_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_3_sqmuxa" in work.decoder(verilog)
net "fsm_dly_1[0]" in work.decoder(verilog)
net "fsm_dly_1[1]" in work.decoder(verilog)
net "fsm_dly_1[2]" in work.decoder(verilog)
net "alu_we_4_sqmuxa" in work.decoder(verilog)
net "fsm_dly_1[0]" in work.decoder(verilog)
net "fsm_dly_1[1]" in work.decoder(verilog)
net "fsm_dly_1[2]" in work.decoder(verilog)
net "wb_we292" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we293" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we294" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we295" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we296" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we297" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we298" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we299" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we300" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we301" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we302" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we303" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we304" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we305" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
net "fsm_dly_1[0]" in work.decoder(verilog)
net "fsm_dly_1[1]" in work.decoder(verilog)
net "fsm_dly_1[2]" in work.decoder(verilog)
net "wb_we307" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we308" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we309" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we310" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we311" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we312" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
2) instance fsm_dly_2[2:0] work.decoder(verilog)-fsm_dly_2[2:0], output net "fsm_dly_2[1]" in work.decoder(verilog)
input nets to instance:
net "alu_func_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_1_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_3_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_4_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_5_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_6_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_7_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_8_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_9_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_10_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_11_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_12_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_13_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_14_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_15_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_16_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_17_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_18_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_19_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_20_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_21_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_22_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_23_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_24_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_25_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_26_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_27_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_28_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_3_sqmuxa" in work.decoder(verilog)
net "fsm_dly_1[0]" in work.decoder(verilog)
net "fsm_dly_1[1]" in work.decoder(verilog)
net "fsm_dly_1[2]" in work.decoder(verilog)
net "alu_we_4_sqmuxa" in work.decoder(verilog)
net "fsm_dly_1[0]" in work.decoder(verilog)
net "fsm_dly_1[1]" in work.decoder(verilog)
net "fsm_dly_1[2]" in work.decoder(verilog)
net "wb_we292" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we293" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we294" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we295" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we296" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we297" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we298" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we299" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we300" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we301" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we302" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we303" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we304" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we305" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
net "fsm_dly_1[0]" in work.decoder(verilog)
net "fsm_dly_1[1]" in work.decoder(verilog)
net "fsm_dly_1[2]" in work.decoder(verilog)
net "wb_we307" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we308" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we309" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we310" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we311" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we312" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
3) instance fsm_dly_2[2:0] work.decoder(verilog)-fsm_dly_2[2:0], output net "fsm_dly_2[2]" in work.decoder(verilog)
input nets to instance:
net "alu_func_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_1_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_3_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_4_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_5_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_6_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_7_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_8_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_9_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_10_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_11_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_12_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_13_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_14_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_15_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_16_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_17_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_18_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_19_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_20_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_21_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_22_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_23_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_24_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_25_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_26_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_27_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_28_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_3_sqmuxa" in work.decoder(verilog)
net "fsm_dly_1[0]" in work.decoder(verilog)
net "fsm_dly_1[1]" in work.decoder(verilog)
net "fsm_dly_1[2]" in work.decoder(verilog)
net "alu_we_4_sqmuxa" in work.decoder(verilog)
net "fsm_dly_1[0]" in work.decoder(verilog)
net "fsm_dly_1[1]" in work.decoder(verilog)
net "fsm_dly_1[2]" in work.decoder(verilog)
net "wb_we292" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we293" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we294" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we295" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we296" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we297" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we298" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we299" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we300" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we301" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we302" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we303" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we304" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we305" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
net "fsm_dly_1[0]" in work.decoder(verilog)
net "fsm_dly_1[1]" in work.decoder(verilog)
net "fsm_dly_1[2]" in work.decoder(verilog)
net "wb_we307" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we308" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we309" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we310" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we311" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we312" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
4) instance ext_ctl_1[0] work.decoder(verilog)-ext_ctl_1[0], output net "ext_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "ext_ctl_2[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
5) instance ext_ctl_1[1] work.decoder(verilog)-ext_ctl_1[1], output net "ext_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "ext_ctl_2[1]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
6) instance ext_ctl_1[2] work.decoder(verilog)-ext_ctl_1[2], output net "ext_ctl_1[2]" in work.decoder(verilog)
input nets to instance:
net "ext_ctl_2[2]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
7) instance rd_sel_1[0] work.decoder(verilog)-rd_sel_1[0], output net "rd_sel_1[0]" in work.decoder(verilog)
input nets to instance:
net "rd_sel_2[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
8) instance rd_sel_1[1] work.decoder(verilog)-rd_sel_1[1], output net "rd_sel_1[1]" in work.decoder(verilog)
input nets to instance:
net "rd_sel_2[1]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_22" in work.decoder(verilog)
net "wb_we315" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
9) instance cmp_ctl_1[0] work.decoder(verilog)-cmp_ctl_1[0], output net "cmp_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "cmp_ctl_2[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
10) instance cmp_ctl_1[1] work.decoder(verilog)-cmp_ctl_1[1], output net "cmp_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "cmp_ctl_2[1]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
11) instance cmp_ctl_1[2] work.decoder(verilog)-cmp_ctl_1[2], output net "cmp_ctl_1[2]" in work.decoder(verilog)
input nets to instance:
net "cmp_ctl_2[2]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
12) instance pc_gen_ctl_1[0] work.decoder(verilog)-pc_gen_ctl_1[0], output net "pc_gen_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "pc_gen_ctl_2[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
13) instance pc_gen_ctl_1[1] work.decoder(verilog)-pc_gen_ctl_1[1], output net "pc_gen_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "pc_gen_ctl_2[1]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
14) instance pc_gen_ctl_1[2] work.decoder(verilog)-pc_gen_ctl_1[2], output net "pc_gen_ctl_1[2]" in work.decoder(verilog)
input nets to instance:
net "pc_gen_ctl_2[2]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
15) instance muxa_ctl_1[0] work.decoder(verilog)-muxa_ctl_1[0], output net "muxa_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "muxa_ctl_2[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
16) instance muxa_ctl_1[1] work.decoder(verilog)-muxa_ctl_1[1], output net "muxa_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "muxa_ctl_2[1]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
17) instance muxb_ctl_1[0] work.decoder(verilog)-muxb_ctl_1[0], output net "muxb_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "muxb_ctl_2[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
18) instance muxb_ctl_1[1] work.decoder(verilog)-muxb_ctl_1[1], output net "muxb_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "muxb_ctl_2[1]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
19) instance alu_func_1[0] work.decoder(verilog)-alu_func_1[0], output net "alu_func_1[0]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
20) instance alu_func_1[1] work.decoder(verilog)-alu_func_1[1], output net "alu_func_1[1]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[1]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
21) instance alu_func_1[2] work.decoder(verilog)-alu_func_1[2], output net "alu_func_1[2]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[2]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
22) instance alu_func_1[3] work.decoder(verilog)-alu_func_1[3], output net "alu_func_1[3]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[3]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
23) instance alu_func_1[4] work.decoder(verilog)-alu_func_1[4], output net "alu_func_1[4]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[4]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
24) instance dmem_ctl_1[0] work.decoder(verilog)-dmem_ctl_1[0], output net "dmem_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "dmem_ctl_2[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
25) instance dmem_ctl_1[1] work.decoder(verilog)-dmem_ctl_1[1], output net "dmem_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "dmem_ctl_2[1]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_22" in work.decoder(verilog)
net "wb_we315" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
26) instance dmem_ctl_1[2] work.decoder(verilog)-dmem_ctl_1[2], output net "dmem_ctl_1[2]" in work.decoder(verilog)
input nets to instance:
net "dmem_ctl_2[2]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_24" in work.decoder(verilog)
net "un1_ins_i_15" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
27) instance dmem_ctl_1[3] work.decoder(verilog)-dmem_ctl_1[3], output net "dmem_ctl_1[3]" in work.decoder(verilog)
input nets to instance:
net "dmem_ctl_2[3]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
28) instance alu_we[0] work.decoder(verilog)-alu_we[0], output net "alu_we[0]" in work.decoder(verilog)
input nets to instance:
net "alu_we_1[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
29) instance wb_mux[0] work.decoder(verilog)-wb_mux[0], output net "wb_mux[0]" in work.decoder(verilog)
input nets to instance:
net "wb_mux_1[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
30) instance wb_we[0] work.decoder(verilog)-wb_we[0], output net "wb_we[0]" in work.decoder(verilog)
input nets to instance:
net "wb_we_1[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
End of loops
Warning: Found 28 combinational loops!
Each loop is reported with an instance in the loop
and nets connected to that instance.
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
1) instance fsm_dly_2[2:0] work.decoder(verilog)-fsm_dly_2[2:0], output net "fsm_dly_2[0]" in work.decoder(verilog)
input nets to instance:
net "alu_func_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_1_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_3_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_4_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_5_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_6_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_7_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_8_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_9_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_10_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_11_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_12_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_13_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_14_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_15_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_16_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_17_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_18_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_19_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_20_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_21_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_22_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_23_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_24_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_25_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_26_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_27_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_28_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_3_sqmuxa" in work.decoder(verilog)
net "fsm_dly_1[0]" in work.decoder(verilog)
net "fsm_dly_1[1]" in work.decoder(verilog)
net "fsm_dly_1[2]" in work.decoder(verilog)
net "alu_we_4_sqmuxa" in work.decoder(verilog)
net "fsm_dly_1[0]" in work.decoder(verilog)
net "fsm_dly_1[1]" in work.decoder(verilog)
net "fsm_dly_1[2]" in work.decoder(verilog)
net "wb_we292" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we293" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we294" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we295" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we296" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we297" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we298" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we299" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we300" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we301" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we302" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we303" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we304" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we305" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
net "fsm_dly_1[0]" in work.decoder(verilog)
net "fsm_dly_1[1]" in work.decoder(verilog)
net "fsm_dly_1[2]" in work.decoder(verilog)
net "wb_we307" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we308" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we309" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we310" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we311" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we312" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
2) instance ext_ctl_1[0] work.decoder(verilog)-ext_ctl_1[0], output net "ext_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "ext_ctl_2[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
3) instance ext_ctl_1[1] work.decoder(verilog)-ext_ctl_1[1], output net "ext_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "ext_ctl_2[1]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
4) instance ext_ctl_1[2] work.decoder(verilog)-ext_ctl_1[2], output net "ext_ctl_1[2]" in work.decoder(verilog)
input nets to instance:
net "ext_ctl_2[2]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
5) instance rd_sel_1[0] work.decoder(verilog)-rd_sel_1[0], output net "rd_sel_1[0]" in work.decoder(verilog)
input nets to instance:
net "rd_sel_2[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
6) instance rd_sel_1[1] work.decoder(verilog)-rd_sel_1[1], output net "rd_sel_1[1]" in work.decoder(verilog)
input nets to instance:
net "rd_sel_2[1]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_22" in work.decoder(verilog)
net "wb_we315" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
7) instance cmp_ctl_1[0] work.decoder(verilog)-cmp_ctl_1[0], output net "cmp_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "cmp_ctl_2[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
8) instance cmp_ctl_1[1] work.decoder(verilog)-cmp_ctl_1[1], output net "cmp_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "cmp_ctl_2[1]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
9) instance cmp_ctl_1[2] work.decoder(verilog)-cmp_ctl_1[2], output net "cmp_ctl_1[2]" in work.decoder(verilog)
input nets to instance:
net "cmp_ctl_2[2]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
10) instance pc_gen_ctl_1[0] work.decoder(verilog)-pc_gen_ctl_1[0], output net "pc_gen_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "pc_gen_ctl_2[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
11) instance pc_gen_ctl_1[1] work.decoder(verilog)-pc_gen_ctl_1[1], output net "pc_gen_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "pc_gen_ctl_2[1]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
12) instance pc_gen_ctl_1[2] work.decoder(verilog)-pc_gen_ctl_1[2], output net "pc_gen_ctl_1[2]" in work.decoder(verilog)
input nets to instance:
net "pc_gen_ctl_2[2]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
13) instance muxa_ctl_1[0] work.decoder(verilog)-muxa_ctl_1[0], output net "muxa_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "muxa_ctl_2[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
14) instance muxa_ctl_1[1] work.decoder(verilog)-muxa_ctl_1[1], output net "muxa_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "muxa_ctl_2[1]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
15) instance muxb_ctl_1[0] work.decoder(verilog)-muxb_ctl_1[0], output net "muxb_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "muxb_ctl_2[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
16) instance muxb_ctl_1[1] work.decoder(verilog)-muxb_ctl_1[1], output net "muxb_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "muxb_ctl_2[1]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
17) instance alu_func_1[0] work.decoder(verilog)-alu_func_1[0], output net "alu_func_1[0]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
18) instance alu_func_1[1] work.decoder(verilog)-alu_func_1[1], output net "alu_func_1[1]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[1]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
19) instance alu_func_1[2] work.decoder(verilog)-alu_func_1[2], output net "alu_func_1[2]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[2]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
20) instance alu_func_1[3] work.decoder(verilog)-alu_func_1[3], output net "alu_func_1[3]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[3]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
21) instance alu_func_1[4] work.decoder(verilog)-alu_func_1[4], output net "alu_func_1[4]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[4]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
22) instance dmem_ctl_1[0] work.decoder(verilog)-dmem_ctl_1[0], output net "dmem_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "dmem_ctl_2[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
23) instance dmem_ctl_1[1] work.decoder(verilog)-dmem_ctl_1[1], output net "dmem_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "dmem_ctl_2[1]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_22" in work.decoder(verilog)
net "wb_we315" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
24) instance dmem_ctl_1[2] work.decoder(verilog)-dmem_ctl_1[2], output net "dmem_ctl_1[2]" in work.decoder(verilog)
input nets to instance:
net "dmem_ctl_2[2]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_24" in work.decoder(verilog)
net "un1_ins_i_15" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
25) instance dmem_ctl_1[3] work.decoder(verilog)-dmem_ctl_1[3], output net "dmem_ctl_1[3]" in work.decoder(verilog)
input nets to instance:
net "dmem_ctl_2[3]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
26) instance alu_we[0] work.decoder(verilog)-alu_we[0], output net "alu_we[0]" in work.decoder(verilog)
input nets to instance:
net "alu_we_1[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
27) instance wb_mux[0] work.decoder(verilog)-wb_mux[0], output net "wb_mux[0]" in work.decoder(verilog)
input nets to instance:
net "wb_mux_1[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
28) instance wb_we[0] work.decoder(verilog)-wb_we[0], output net "wb_we[0]" in work.decoder(verilog)
input nets to instance:
net "wb_we_1[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
End of loops
@N: : <a href="f:\a\rtl\verilog\mips_uart.v:243:4:243:10:@N::@XP_MSG">mips_uart.v(243)</a><!@TM:1190250740> | Found counter in view:work.uart_read(verilog) inst clk_ctr[15:0]
@N: : <a href="f:\a\rtl\verilog\mips_uart.v:256:4:256:10:@N::@XP_MSG">mips_uart.v(256)</a><!@TM:1190250740> | Found counter in view:work.uart_read(verilog) inst bit_ctr[2:0]
Encoding state machine work.uart_read(verilog)-ua_state[4:0]
original code -> new code
000 -> 00000
001 -> 00011
010 -> 00101
011 -> 01001
100 -> 10001
@N: : <a href="f:\a\rtl\verilog\mips_uart.v:138:4:138:10:@N::@XP_MSG">mips_uart.v(138)</a><!@TM:1190250740> | Found counter in view:work.uart_write(verilog) inst clk_ctr[15:0]
@N: : <a href="f:\a\rtl\verilog\mips_uart.v:151:4:151:10:@N::@XP_MSG">mips_uart.v(151)</a><!@TM:1190250740> | Found counter in view:work.uart_write(verilog) inst bit_ctr[2:0]
Encoding state machine work.uart_write(verilog)-ua_state[7:0]
original code -> new code
000 -> 00000000
001 -> 00000011
010 -> 00000101
011 -> 00001001
100 -> 00010001
101 -> 00100001
110 -> 01000001
111 -> 10000001
@N:<a href="@N:MO106:@XP_HELP">MO106</a> : <a href="f:\a\rtl\verilog\dvc.v:67:12:67:16:@N:MO106:@XP_MSG">dvc.v(67)</a><!@TM:1190250740> | Found ROM, 'seg_20[6:0]', 16 words by 7 bits
@N:<a href="@N:MO106:@XP_HELP">MO106</a> : <a href="f:\a\rtl\verilog\dvc.v:67:12:67:16:@N:MO106:@XP_MSG">dvc.v(67)</a><!@TM:1190250740> | Found ROM, 'seg[6:0]', 16 words by 7 bits
@N: : <a href="f:\a\rtl\verilog\dvc.v:23:4:23:10:@N::@XP_MSG">dvc.v(23)</a><!@TM:1190250740> | Found counter in view:work.tmr0(verilog) inst cntr[31:0]
Warning: Found 28 combinational loops!
Each loop is reported with an instance in the loop
and nets connected to that instance.
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
1) instance fsm_dly_2[0] work.decoder(verilog)-fsm_dly_2[0], output net "fsm_dly_2[0]" in work.decoder(verilog)
input nets to instance:
net "N_172" in work.decoder(verilog)
net "fsm_dly_1[0]" in work.decoder(verilog)
net "N_415" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
2) instance ext_ctl_1[0] work.decoder(verilog)-ext_ctl_1[0], output net "ext_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "ext_ctl_2[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
3) instance ext_ctl_1[1] work.decoder(verilog)-ext_ctl_1[1], output net "ext_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "ext_ctl_2[1]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
4) instance ext_ctl_1[2] work.decoder(verilog)-ext_ctl_1[2], output net "ext_ctl_1[2]" in work.decoder(verilog)
input nets to instance:
net "ext_ctl_2[2]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
5) instance rd_sel_1[0] work.decoder(verilog)-rd_sel_1[0], output net "rd_sel_1[0]" in work.decoder(verilog)
input nets to instance:
net "rd_sel_2[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
6) instance rd_sel_1[1] work.decoder(verilog)-rd_sel_1[1], output net "rd_sel_1[1]" in work.decoder(verilog)
input nets to instance:
net "rd_sel_2[1]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "N_438" in work.decoder(verilog)
net "wb_we315" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
7) instance cmp_ctl_1[0] work.decoder(verilog)-cmp_ctl_1[0], output net "cmp_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "cmp_ctl_2[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
8) instance cmp_ctl_1[1] work.decoder(verilog)-cmp_ctl_1[1], output net "cmp_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "cmp_ctl_2[1]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
9) instance cmp_ctl_1[2] work.decoder(verilog)-cmp_ctl_1[2], output net "cmp_ctl_1[2]" in work.decoder(verilog)
input nets to instance:
net "cmp_ctl_2[2]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
10) instance pc_gen_ctl_1[0] work.decoder(verilog)-pc_gen_ctl_1[0], output net "pc_gen_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "pc_gen_ctl_2[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
11) instance pc_gen_ctl_1[1] work.decoder(verilog)-pc_gen_ctl_1[1], output net "pc_gen_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "pc_gen_ctl_2[1]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
12) instance pc_gen_ctl_1[2] work.decoder(verilog)-pc_gen_ctl_1[2], output net "pc_gen_ctl_1[2]" in work.decoder(verilog)
input nets to instance:
net "pc_gen_ctl_2[2]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
13) instance muxa_ctl_1[0] work.decoder(verilog)-muxa_ctl_1[0], output net "muxa_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "muxa_ctl_2[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
14) instance muxa_ctl_1[1] work.decoder(verilog)-muxa_ctl_1[1], output net "muxa_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "muxa_ctl_2[1]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
15) instance muxb_ctl_1[0] work.decoder(verilog)-muxb_ctl_1[0], output net "muxb_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "muxb_ctl_2[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
16) instance muxb_ctl_1[1] work.decoder(verilog)-muxb_ctl_1[1], output net "muxb_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "muxb_ctl_2[1]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
17) instance alu_func_1[0] work.decoder(verilog)-alu_func_1[0], output net "alu_func_1[0]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
18) instance alu_func_1[1] work.decoder(verilog)-alu_func_1[1], output net "alu_func_1[1]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[1]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
19) instance alu_func_1[2] work.decoder(verilog)-alu_func_1[2], output net "alu_func_1[2]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[2]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
20) instance alu_func_1[3] work.decoder(verilog)-alu_func_1[3], output net "alu_func_1[3]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[3]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
21) instance alu_func_1[4] work.decoder(verilog)-alu_func_1[4], output net "alu_func_1[4]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[4]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
22) instance dmem_ctl_1[0] work.decoder(verilog)-dmem_ctl_1[0], output net "dmem_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "dmem_ctl_2[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
23) instance dmem_ctl_1[1] work.decoder(verilog)-dmem_ctl_1[1], output net "dmem_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "dmem_ctl_2[1]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "N_438" in work.decoder(verilog)
net "wb_we315" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
24) instance dmem_ctl_1[2] work.decoder(verilog)-dmem_ctl_1[2], output net "dmem_ctl_1[2]" in work.decoder(verilog)
input nets to instance:
net "dmem_ctl_2[2]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_24" in work.decoder(verilog)
net "un1_ins_i_15" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
25) instance dmem_ctl_1[3] work.decoder(verilog)-dmem_ctl_1[3], output net "dmem_ctl_1[3]" in work.decoder(verilog)
input nets to instance:
net "dmem_ctl_2[3]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
26) instance alu_we[0] work.decoder(verilog)-alu_we[0], output net "alu_we[0]" in work.decoder(verilog)
input nets to instance:
net "alu_we_1[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
27) instance wb_mux[0] work.decoder(verilog)-wb_mux[0], output net "wb_mux[0]" in work.decoder(verilog)
input nets to instance:
net "wb_mux_1[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
28) instance wb_we[0] work.decoder(verilog)-wb_we[0], output net "wb_we[0]" in work.decoder(verilog)
input nets to instance:
net "wb_we_1[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
End of loops
Warning: Found 28 combinational loops!
Each loop is reported with an instance in the loop
and nets connected to that instance.
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
1) instance fsm_dly_2[0] work.decoder(verilog)-fsm_dly_2[0], output net "fsm_dly_2[0]" in work.decoder(verilog)
input nets to instance:
net "N_172" in work.decoder(verilog)
net "fsm_dly_1[0]" in work.decoder(verilog)
net "N_415" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
2) instance ext_ctl_1[0] work.decoder(verilog)-ext_ctl_1[0], output net "ext_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "ext_ctl_2[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
3) instance ext_ctl_1[1] work.decoder(verilog)-ext_ctl_1[1], output net "ext_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "ext_ctl_2[1]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
4) instance ext_ctl_1[2] work.decoder(verilog)-ext_ctl_1[2], output net "ext_ctl_1[2]" in work.decoder(verilog)
input nets to instance:
net "ext_ctl_2[2]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
5) instance rd_sel_1[0] work.decoder(verilog)-rd_sel_1[0], output net "rd_sel_1[0]" in work.decoder(verilog)
input nets to instance:
net "rd_sel_2[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
6) instance rd_sel_1[1] work.decoder(verilog)-rd_sel_1[1], output net "rd_sel_1[1]" in work.decoder(verilog)
input nets to instance:
net "rd_sel_2[1]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "N_438" in work.decoder(verilog)
net "wb_we315" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
7) instance cmp_ctl_1[0] work.decoder(verilog)-cmp_ctl_1[0], output net "cmp_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "cmp_ctl_2[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
8) instance cmp_ctl_1[1] work.decoder(verilog)-cmp_ctl_1[1], output net "cmp_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "cmp_ctl_2[1]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
9) instance cmp_ctl_1[2] work.decoder(verilog)-cmp_ctl_1[2], output net "cmp_ctl_1[2]" in work.decoder(verilog)
input nets to instance:
net "cmp_ctl_2[2]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
10) instance pc_gen_ctl_1[0] work.decoder(verilog)-pc_gen_ctl_1[0], output net "pc_gen_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "pc_gen_ctl_2[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
11) instance pc_gen_ctl_1[1] work.decoder(verilog)-pc_gen_ctl_1[1], output net "pc_gen_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "pc_gen_ctl_2[1]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
12) instance pc_gen_ctl_1[2] work.decoder(verilog)-pc_gen_ctl_1[2], output net "pc_gen_ctl_1[2]" in work.decoder(verilog)
input nets to instance:
net "pc_gen_ctl_2[2]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
13) instance muxa_ctl_1[0] work.decoder(verilog)-muxa_ctl_1[0], output net "muxa_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "muxa_ctl_2[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
14) instance muxa_ctl_1[1] work.decoder(verilog)-muxa_ctl_1[1], output net "muxa_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "muxa_ctl_2[1]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
15) instance muxb_ctl_1[0] work.decoder(verilog)-muxb_ctl_1[0], output net "muxb_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "muxb_ctl_2[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
16) instance muxb_ctl_1[1] work.decoder(verilog)-muxb_ctl_1[1], output net "muxb_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "muxb_ctl_2[1]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
17) instance alu_func_1[0] work.decoder(verilog)-alu_func_1[0], output net "alu_func_1[0]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
18) instance alu_func_1[1] work.decoder(verilog)-alu_func_1[1], output net "alu_func_1[1]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[1]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
19) instance alu_func_1[2] work.decoder(verilog)-alu_func_1[2], output net "alu_func_1[2]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[2]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
20) instance alu_func_1[3] work.decoder(verilog)-alu_func_1[3], output net "alu_func_1[3]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[3]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
21) instance alu_func_1[4] work.decoder(verilog)-alu_func_1[4], output net "alu_func_1[4]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[4]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
22) instance dmem_ctl_1[0] work.decoder(verilog)-dmem_ctl_1[0], output net "dmem_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "dmem_ctl_2[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
23) instance dmem_ctl_1[1] work.decoder(verilog)-dmem_ctl_1[1], output net "dmem_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "dmem_ctl_2[1]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "N_438" in work.decoder(verilog)
net "wb_we315" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
24) instance dmem_ctl_1[2] work.decoder(verilog)-dmem_ctl_1[2], output net "dmem_ctl_1[2]" in work.decoder(verilog)
input nets to instance:
net "dmem_ctl_2[2]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_24" in work.decoder(verilog)
net "un1_ins_i_15" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
25) instance dmem_ctl_1[3] work.decoder(verilog)-dmem_ctl_1[3], output net "dmem_ctl_1[3]" in work.decoder(verilog)
input nets to instance:
net "dmem_ctl_2[3]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
26) instance alu_we[0] work.decoder(verilog)-alu_we[0], output net "alu_we[0]" in work.decoder(verilog)
input nets to instance:
net "alu_we_1[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
27) instance wb_mux[0] work.decoder(verilog)-wb_mux[0], output net "wb_mux[0]" in work.decoder(verilog)
input nets to instance:
net "wb_mux_1[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
28) instance wb_we[0] work.decoder(verilog)-wb_we[0], output net "wb_we[0]" in work.decoder(verilog)
input nets to instance:
net "wb_we_1[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
End of loops
Warning: Found 28 combinational loops!
Each loop is reported with an instance in the loop
and nets connected to that instance.
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
1) instance fsm_dly_2[0] work.decoder(verilog)-fsm_dly_2[0], output net "fsm_dly_2[0]" in work.decoder(verilog)
input nets to instance:
net "N_172" in work.decoder(verilog)
net "fsm_dly_1[0]" in work.decoder(verilog)
net "N_415" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
2) instance ext_ctl_1[0] work.decoder(verilog)-ext_ctl_1[0], output net "ext_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "ext_ctl_2[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
3) instance ext_ctl_1[1] work.decoder(verilog)-ext_ctl_1[1], output net "ext_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "ext_ctl_2[1]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
4) instance ext_ctl_1[2] work.decoder(verilog)-ext_ctl_1[2], output net "ext_ctl_1[2]" in work.decoder(verilog)
input nets to instance:
net "ext_ctl_2[2]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
5) instance rd_sel_1[0] work.decoder(verilog)-rd_sel_1[0], output net "rd_sel_1[0]" in work.decoder(verilog)
input nets to instance:
net "rd_sel_2[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
6) instance rd_sel_1[1] work.decoder(verilog)-rd_sel_1[1], output net "rd_sel_1[1]" in work.decoder(verilog)
input nets to instance:
net "rd_sel_2[1]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "N_438" in work.decoder(verilog)
net "wb_we315" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
7) instance cmp_ctl_1[0] work.decoder(verilog)-cmp_ctl_1[0], output net "cmp_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "cmp_ctl_2[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
8) instance cmp_ctl_1[1] work.decoder(verilog)-cmp_ctl_1[1], output net "cmp_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "cmp_ctl_2[1]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
9) instance cmp_ctl_1[2] work.decoder(verilog)-cmp_ctl_1[2], output net "cmp_ctl_1[2]" in work.decoder(verilog)
input nets to instance:
net "cmp_ctl_2[2]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
10) instance pc_gen_ctl_1[0] work.decoder(verilog)-pc_gen_ctl_1[0], output net "pc_gen_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "pc_gen_ctl_2[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
11) instance pc_gen_ctl_1[1] work.decoder(verilog)-pc_gen_ctl_1[1], output net "pc_gen_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "pc_gen_ctl_2[1]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
12) instance pc_gen_ctl_1[2] work.decoder(verilog)-pc_gen_ctl_1[2], output net "pc_gen_ctl_1[2]" in work.decoder(verilog)
input nets to instance:
net "pc_gen_ctl_2[2]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
13) instance muxa_ctl_1[0] work.decoder(verilog)-muxa_ctl_1[0], output net "muxa_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "muxa_ctl_2[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
14) instance muxa_ctl_1[1] work.decoder(verilog)-muxa_ctl_1[1], output net "muxa_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "muxa_ctl_2[1]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
15) instance muxb_ctl_1[0] work.decoder(verilog)-muxb_ctl_1[0], output net "muxb_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "muxb_ctl_2[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
16) instance muxb_ctl_1[1] work.decoder(verilog)-muxb_ctl_1[1], output net "muxb_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "muxb_ctl_2[1]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
17) instance alu_func_1[0] work.decoder(verilog)-alu_func_1[0], output net "alu_func_1[0]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
18) instance alu_func_1[1] work.decoder(verilog)-alu_func_1[1], output net "alu_func_1[1]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[1]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
19) instance alu_func_1[2] work.decoder(verilog)-alu_func_1[2], output net "alu_func_1[2]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[2]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
20) instance alu_func_1[3] work.decoder(verilog)-alu_func_1[3], output net "alu_func_1[3]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[3]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
21) instance alu_func_1[4] work.decoder(verilog)-alu_func_1[4], output net "alu_func_1[4]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[4]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
22) instance dmem_ctl_1[0] work.decoder(verilog)-dmem_ctl_1[0], output net "dmem_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "dmem_ctl_2[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
23) instance dmem_ctl_1[1] work.decoder(verilog)-dmem_ctl_1[1], output net "dmem_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "dmem_ctl_2[1]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "N_438" in work.decoder(verilog)
net "wb_we315" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
24) instance dmem_ctl_1[2] work.decoder(verilog)-dmem_ctl_1[2], output net "dmem_ctl_1[2]" in work.decoder(verilog)
input nets to instance:
net "dmem_ctl_2[2]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_24" in work.decoder(verilog)
net "un1_ins_i_15" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
25) instance dmem_ctl_1[3] work.decoder(verilog)-dmem_ctl_1[3], output net "dmem_ctl_1[3]" in work.decoder(verilog)
input nets to instance:
net "dmem_ctl_2[3]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
26) instance alu_we[0] work.decoder(verilog)-alu_we[0], output net "alu_we[0]" in work.decoder(verilog)
input nets to instance:
net "alu_we_1[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
27) instance wb_mux[0] work.decoder(verilog)-wb_mux[0], output net "wb_mux[0]" in work.decoder(verilog)
input nets to instance:
net "wb_mux_1[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
28) instance wb_we[0] work.decoder(verilog)-wb_we[0], output net "wb_we[0]" in work.decoder(verilog)
input nets to instance:
net "wb_we_1[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
End of loops
Automatic dissolve during optimization of view:work.mips_core(verilog) of iRF_stage.reg_bank(reg_array)
Auto Dissolve of decoder_pipe (inst of view:work.decode_pipe(verilog))
Auto Dissolve of iRF_stage.i_cmp (inst of view:work.compare(verilog))
Auto Dissolve of mips_tmr0 (inst of view:work.tmr0(verilog))
Warning: Found 28 combinational loops!
Each loop is reported with an instance in the loop
and nets connected to that instance.
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
1) instance isys.mips_core.decoder_pipe.idecoder.fsm_dly_1[0] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.fsm_dly_1[0], output net "isys.mips_core.BUS197[0]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.fsm_dly_2[0]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_436" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
2) instance isys.mips_core.decoder_pipe.idecoder.ext_ctl_1[0] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.ext_ctl_1[0], output net "isys.mips_core.decoder_pipe.BUS2072[0]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.N_1374" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
3) instance isys.mips_core.decoder_pipe.idecoder.ext_ctl_1[1] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.ext_ctl_1[1], output net "isys.mips_core.decoder_pipe.BUS2072[1]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.N_1375" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_436" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
4) instance isys.mips_core.decoder_pipe.idecoder.ext_ctl_1[2] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.ext_ctl_1[2], output net "isys.mips_core.decoder_pipe.BUS2072[2]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.ext_ctl_2[2]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_436" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
5) instance isys.mips_core.decoder_pipe.idecoder.rd_sel_1[0] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.rd_sel_1[0], output net "isys.mips_core.decoder_pipe.BUS2110[0]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.rd_sel_2[0]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_436" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
6) instance isys.mips_core.decoder_pipe.idecoder.rd_sel_1[1] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.rd_sel_1[1], output net "isys.mips_core.decoder_pipe.BUS2110[1]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.rd_sel_2[1]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_438" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.wb_we315" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
7) instance isys.mips_core.decoder_pipe.idecoder.cmp_ctl_1[0] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.cmp_ctl_1[0], output net "isys.mips_core.decoder_pipe.BUS2056[0]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.cmp_ctl_2[0]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_436" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
8) instance isys.mips_core.decoder_pipe.idecoder.cmp_ctl_1[1] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.cmp_ctl_1[1], output net "isys.mips_core.decoder_pipe.BUS2056[1]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.cmp_ctl_2[1]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_436" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
9) instance isys.mips_core.decoder_pipe.idecoder.cmp_ctl_1[2] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.cmp_ctl_1[2], output net "isys.mips_core.decoder_pipe.BUS2056[2]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.cmp_ctl_2[2]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_436" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
10) instance isys.mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[0] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[0], output net "isys.mips_core.decoder_pipe.BUS2102[0]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.N_1377" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
11) instance isys.mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[1] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[1], output net "isys.mips_core.decoder_pipe.BUS2102[1]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.pc_gen_ctl_2[1]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_436" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
12) instance isys.mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[2] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[2], output net "isys.mips_core.decoder_pipe.BUS2102[2]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.N_1260_i" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
13) instance isys.mips_core.decoder_pipe.idecoder.muxa_ctl_1[0] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.muxa_ctl_1[0], output net "isys.mips_core.decoder_pipe.BUS2086[0]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.muxa_ctl_2[0]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_436" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
14) instance isys.mips_core.decoder_pipe.idecoder.muxa_ctl_1[1] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.muxa_ctl_1[1], output net "isys.mips_core.decoder_pipe.BUS2086[1]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.muxa_ctl_2[1]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
15) instance isys.mips_core.decoder_pipe.idecoder.muxb_ctl_1[0] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.muxb_ctl_1[0], output net "isys.mips_core.decoder_pipe.BUS2094[0]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.muxb_ctl_2[0]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_436" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
16) instance isys.mips_core.decoder_pipe.idecoder.muxb_ctl_1[1] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.muxb_ctl_1[1], output net "isys.mips_core.decoder_pipe.BUS2094[1]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.muxb_ctl_2[1]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
17) instance isys.mips_core.decoder_pipe.idecoder.alu_func_1[0] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.alu_func_1[0], output net "isys.mips_core.decoder_pipe.BUS2040[0]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.alu_func_2[0]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_436" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
18) instance isys.mips_core.decoder_pipe.idecoder.alu_func_1[1] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.alu_func_1[1], output net "isys.mips_core.decoder_pipe.BUS2040[1]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.alu_func_2[1]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_436" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
19) instance isys.mips_core.decoder_pipe.idecoder.alu_func_1[2] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.alu_func_1[2], output net "isys.mips_core.decoder_pipe.BUS2040[2]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.N_1373" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
20) instance isys.mips_core.decoder_pipe.idecoder.alu_func_1[3] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.alu_func_1[3], output net "isys.mips_core.decoder_pipe.BUS2040[3]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.alu_func_2[3]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
21) instance isys.mips_core.decoder_pipe.idecoder.alu_func_1[4] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.alu_func_1[4], output net "isys.mips_core.decoder_pipe.BUS2040[4]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.alu_func_2[4]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_436" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
22) instance isys.mips_core.decoder_pipe.idecoder.dmem_ctl_1[0] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.dmem_ctl_1[0], output net "isys.mips_core.decoder_pipe.BUS2064[0]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.dmem_ctl_2[0]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
23) instance isys.mips_core.decoder_pipe.idecoder.dmem_ctl_1[1] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.dmem_ctl_1[1], output net "isys.mips_core.decoder_pipe.BUS2064[1]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.dmem_ctl_2[1]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_438" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.wb_we315" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
24) instance isys.mips_core.decoder_pipe.idecoder.dmem_ctl_1[2] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.dmem_ctl_1[2], output net "isys.mips_core.decoder_pipe.BUS2064[2]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.dmem_ctl_2[2]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_24" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_15" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
25) instance isys.mips_core.decoder_pipe.idecoder.dmem_ctl_1[3] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.dmem_ctl_1[3], output net "isys.mips_core.decoder_pipe.BUS2064[3]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.dmem_ctl_2[3]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_436" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
26) instance isys.mips_core.decoder_pipe.idecoder.alu_we[0] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.alu_we[0], output net "isys.mips_core.decoder_pipe.BUS2048[0]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.alu_we_1[0]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_436" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
27) instance isys.mips_core.decoder_pipe.idecoder.wb_mux[0] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.wb_mux[0], output net "isys.mips_core.decoder_pipe.BUS2118[0]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.wb_mux_1[0]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_436" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
28) instance isys.mips_core.decoder_pipe.idecoder.wb_we[0] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.wb_we[0], output net "isys.mips_core.decoder_pipe.BUS2126[0]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.wb_we_1[0]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_436" in work.mips_top(verilog)
End of loops
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\mips_dvc.v:117:4:117:10:@W:BN116:@XP_MSG">mips_dvc.v(117)</a><!@TM:1190250740> | Removing sequential instance isys.imips_dvc.key2_addr[31] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\mips_dvc.v:117:4:117:10:@W:BN116:@XP_MSG">mips_dvc.v(117)</a><!@TM:1190250740> | Removing sequential instance isys.imips_dvc.key2_addr[30] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\mips_dvc.v:117:4:117:10:@W:BN116:@XP_MSG">mips_dvc.v(117)</a><!@TM:1190250740> | Removing sequential instance isys.imips_dvc.key2_addr[29] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\mips_dvc.v:117:4:117:10:@W:BN116:@XP_MSG">mips_dvc.v(117)</a><!@TM:1190250740> | Removing sequential instance isys.imips_dvc.key2_addr[28] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\mips_dvc.v:117:4:117:10:@W:BN116:@XP_MSG">mips_dvc.v(117)</a><!@TM:1190250740> | Removing sequential instance isys.imips_dvc.key2_addr[27] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\mips_dvc.v:117:4:117:10:@W:BN116:@XP_MSG">mips_dvc.v(117)</a><!@TM:1190250740> | Removing sequential instance isys.imips_dvc.key2_addr[26] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\mips_dvc.v:117:4:117:10:@W:BN116:@XP_MSG">mips_dvc.v(117)</a><!@TM:1190250740> | Removing sequential instance isys.imips_dvc.key2_addr[25] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\mips_dvc.v:117:4:117:10:@W:BN116:@XP_MSG">mips_dvc.v(117)</a><!@TM:1190250740> | Removing sequential instance isys.imips_dvc.key2_addr[24] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\mips_dvc.v:117:4:117:10:@W:BN116:@XP_MSG">mips_dvc.v(117)</a><!@TM:1190250740> | Removing sequential instance isys.imips_dvc.key2_addr[23] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\mips_dvc.v:117:4:117:10:@W:BN116:@XP_MSG">mips_dvc.v(117)</a><!@TM:1190250740> | Removing sequential instance isys.imips_dvc.key2_addr[22] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\mips_dvc.v:117:4:117:10:@W:BN116:@XP_MSG">mips_dvc.v(117)</a><!@TM:1190250740> | Removing sequential instance isys.imips_dvc.key2_addr[21] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\mips_dvc.v:117:4:117:10:@W:BN116:@XP_MSG">mips_dvc.v(117)</a><!@TM:1190250740> | Removing sequential instance isys.imips_dvc.key2_addr[20] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\mips_dvc.v:117:4:117:10:@W:BN116:@XP_MSG">mips_dvc.v(117)</a><!@TM:1190250740> | Removing sequential instance isys.imips_dvc.key2_addr[19] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\mips_dvc.v:117:4:117:10:@W:BN116:@XP_MSG">mips_dvc.v(117)</a><!@TM:1190250740> | Removing sequential instance isys.imips_dvc.key2_addr[18] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\mips_dvc.v:117:4:117:10:@W:BN116:@XP_MSG">mips_dvc.v(117)</a><!@TM:1190250740> | Removing sequential instance isys.imips_dvc.key2_addr[17] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\mips_dvc.v:117:4:117:10:@W:BN116:@XP_MSG">mips_dvc.v(117)</a><!@TM:1190250740> | Removing sequential instance isys.imips_dvc.key2_addr[16] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\mips_dvc.v:117:4:117:10:@W:BN116:@XP_MSG">mips_dvc.v(117)</a><!@TM:1190250740> | Removing sequential instance isys.imips_dvc.key2_addr[15] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\mips_dvc.v:117:4:117:10:@W:BN116:@XP_MSG">mips_dvc.v(117)</a><!@TM:1190250740> | Removing sequential instance isys.imips_dvc.key2_addr[14] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\mips_dvc.v:117:4:117:10:@W:BN116:@XP_MSG">mips_dvc.v(117)</a><!@TM:1190250740> | Removing sequential instance isys.imips_dvc.key2_addr[13] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\mips_dvc.v:117:4:117:10:@W:BN116:@XP_MSG">mips_dvc.v(117)</a><!@TM:1190250740> | Removing sequential instance isys.imips_dvc.key2_addr[12] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\mips_dvc.v:117:4:117:10:@W:BN116:@XP_MSG">mips_dvc.v(117)</a><!@TM:1190250740> | Removing sequential instance isys.imips_dvc.key2_addr[11] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\mips_dvc.v:117:4:117:10:@W:BN116:@XP_MSG">mips_dvc.v(117)</a><!@TM:1190250740> | Removing sequential instance isys.imips_dvc.key2_addr[10] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\mips_dvc.v:117:4:117:10:@W:BN116:@XP_MSG">mips_dvc.v(117)</a><!@TM:1190250740> | Removing sequential instance isys.imips_dvc.key2_addr[9] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\mips_dvc.v:117:4:117:10:@W:BN116:@XP_MSG">mips_dvc.v(117)</a><!@TM:1190250740> | Removing sequential instance isys.imips_dvc.key2_addr[8] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\mips_dvc.v:117:4:117:10:@W:BN116:@XP_MSG">mips_dvc.v(117)</a><!@TM:1190250740> | Removing sequential instance isys.imips_dvc.key2_addr[7] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\mips_dvc.v:117:4:117:10:@W:BN116:@XP_MSG">mips_dvc.v(117)</a><!@TM:1190250740> | Removing sequential instance isys.imips_dvc.key2_addr[6] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\mips_dvc.v:117:4:117:10:@W:BN116:@XP_MSG">mips_dvc.v(117)</a><!@TM:1190250740> | Removing sequential instance isys.imips_dvc.key2_addr[5] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\mips_dvc.v:117:4:117:10:@W:BN116:@XP_MSG">mips_dvc.v(117)</a><!@TM:1190250740> | Removing sequential instance isys.imips_dvc.key2_addr[4] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\mips_dvc.v:117:4:117:10:@W:BN116:@XP_MSG">mips_dvc.v(117)</a><!@TM:1190250740> | Removing sequential instance isys.imips_dvc.key2_addr[3] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\mips_dvc.v:117:4:117:10:@W:BN116:@XP_MSG">mips_dvc.v(117)</a><!@TM:1190250740> | Removing sequential instance isys.imips_dvc.key2_addr[2] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\mips_dvc.v:117:4:117:10:@W:BN116:@XP_MSG">mips_dvc.v(117)</a><!@TM:1190250740> | Removing sequential instance isys.imips_dvc.key2_addr[1] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\mips_dvc.v:117:4:117:10:@W:BN116:@XP_MSG">mips_dvc.v(117)</a><!@TM:1190250740> | Removing sequential instance isys.imips_dvc.key2_addr[0] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\mips_dvc.v:117:4:117:10:@W:BN116:@XP_MSG">mips_dvc.v(117)</a><!@TM:1190250740> | Removing sequential instance isys.imips_dvc.key1_addr[31] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\mips_dvc.v:117:4:117:10:@W:BN116:@XP_MSG">mips_dvc.v(117)</a><!@TM:1190250740> | Removing sequential instance isys.imips_dvc.key1_addr[30] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\mips_dvc.v:117:4:117:10:@W:BN116:@XP_MSG">mips_dvc.v(117)</a><!@TM:1190250740> | Removing sequential instance isys.imips_dvc.key1_addr[29] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\mips_dvc.v:117:4:117:10:@W:BN116:@XP_MSG">mips_dvc.v(117)</a><!@TM:1190250740> | Removing sequential instance isys.imips_dvc.key1_addr[28] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\mips_dvc.v:117:4:117:10:@W:BN116:@XP_MSG">mips_dvc.v(117)</a><!@TM:1190250740> | Removing sequential instance isys.imips_dvc.key1_addr[27] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\mips_dvc.v:117:4:117:10:@W:BN116:@XP_MSG">mips_dvc.v(117)</a><!@TM:1190250740> | Removing sequential instance isys.imips_dvc.key1_addr[26] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\mips_dvc.v:117:4:117:10:@W:BN116:@XP_MSG">mips_dvc.v(117)</a><!@TM:1190250740> | Removing sequential instance isys.imips_dvc.key1_addr[25] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\mips_dvc.v:117:4:117:10:@W:BN116:@XP_MSG">mips_dvc.v(117)</a><!@TM:1190250740> | Removing sequential instance isys.imips_dvc.key1_addr[24] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\mips_dvc.v:117:4:117:10:@W:BN116:@XP_MSG">mips_dvc.v(117)</a><!@TM:1190250740> | Removing sequential instance isys.imips_dvc.key1_addr[23] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\mips_dvc.v:117:4:117:10:@W:BN116:@XP_MSG">mips_dvc.v(117)</a><!@TM:1190250740> | Removing sequential instance isys.imips_dvc.key1_addr[22] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\mips_dvc.v:117:4:117:10:@W:BN116:@XP_MSG">mips_dvc.v(117)</a><!@TM:1190250740> | Removing sequential instance isys.imips_dvc.key1_addr[21] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\mips_dvc.v:117:4:117:10:@W:BN116:@XP_MSG">mips_dvc.v(117)</a><!@TM:1190250740> | Removing sequential instance isys.imips_dvc.key1_addr[20] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\mips_dvc.v:117:4:117:10:@W:BN116:@XP_MSG">mips_dvc.v(117)</a><!@TM:1190250740> | Removing sequential instance isys.imips_dvc.key1_addr[19] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\mips_dvc.v:117:4:117:10:@W:BN116:@XP_MSG">mips_dvc.v(117)</a><!@TM:1190250740> | Removing sequential instance isys.imips_dvc.key1_addr[18] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\mips_dvc.v:117:4:117:10:@W:BN116:@XP_MSG">mips_dvc.v(117)</a><!@TM:1190250740> | Removing sequential instance isys.imips_dvc.key1_addr[17] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\mips_dvc.v:117:4:117:10:@W:BN116:@XP_MSG">mips_dvc.v(117)</a><!@TM:1190250740> | Removing sequential instance isys.imips_dvc.key1_addr[16] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\mips_dvc.v:117:4:117:10:@W:BN116:@XP_MSG">mips_dvc.v(117)</a><!@TM:1190250740> | Removing sequential instance isys.imips_dvc.key1_addr[15] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\mips_dvc.v:117:4:117:10:@W:BN116:@XP_MSG">mips_dvc.v(117)</a><!@TM:1190250740> | Removing sequential instance isys.imips_dvc.key1_addr[14] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\mips_dvc.v:117:4:117:10:@W:BN116:@XP_MSG">mips_dvc.v(117)</a><!@TM:1190250740> | Removing sequential instance isys.imips_dvc.key1_addr[13] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\mips_dvc.v:117:4:117:10:@W:BN116:@XP_MSG">mips_dvc.v(117)</a><!@TM:1190250740> | Removing sequential instance isys.imips_dvc.key1_addr[12] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\mips_dvc.v:117:4:117:10:@W:BN116:@XP_MSG">mips_dvc.v(117)</a><!@TM:1190250740> | Removing sequential instance isys.imips_dvc.key1_addr[11] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\mips_dvc.v:117:4:117:10:@W:BN116:@XP_MSG">mips_dvc.v(117)</a><!@TM:1190250740> | Removing sequential instance isys.imips_dvc.key1_addr[10] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\mips_dvc.v:117:4:117:10:@W:BN116:@XP_MSG">mips_dvc.v(117)</a><!@TM:1190250740> | Removing sequential instance isys.imips_dvc.key1_addr[9] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\mips_dvc.v:117:4:117:10:@W:BN116:@XP_MSG">mips_dvc.v(117)</a><!@TM:1190250740> | Removing sequential instance isys.imips_dvc.key1_addr[8] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\mips_dvc.v:117:4:117:10:@W:BN116:@XP_MSG">mips_dvc.v(117)</a><!@TM:1190250740> | Removing sequential instance isys.imips_dvc.key1_addr[7] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\mips_dvc.v:117:4:117:10:@W:BN116:@XP_MSG">mips_dvc.v(117)</a><!@TM:1190250740> | Removing sequential instance isys.imips_dvc.key1_addr[6] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\mips_dvc.v:117:4:117:10:@W:BN116:@XP_MSG">mips_dvc.v(117)</a><!@TM:1190250740> | Removing sequential instance isys.imips_dvc.key1_addr[5] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\mips_dvc.v:117:4:117:10:@W:BN116:@XP_MSG">mips_dvc.v(117)</a><!@TM:1190250740> | Removing sequential instance isys.imips_dvc.key1_addr[4] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\mips_dvc.v:117:4:117:10:@W:BN116:@XP_MSG">mips_dvc.v(117)</a><!@TM:1190250740> | Removing sequential instance isys.imips_dvc.key1_addr[3] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\mips_dvc.v:117:4:117:10:@W:BN116:@XP_MSG">mips_dvc.v(117)</a><!@TM:1190250740> | Removing sequential instance isys.imips_dvc.key1_addr[2] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\mips_dvc.v:117:4:117:10:@W:BN116:@XP_MSG">mips_dvc.v(117)</a><!@TM:1190250740> | Removing sequential instance isys.imips_dvc.key1_addr[1] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\mips_dvc.v:117:4:117:10:@W:BN116:@XP_MSG">mips_dvc.v(117)</a><!@TM:1190250740> | Removing sequential instance isys.imips_dvc.key1_addr[0] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\mips_dvc.v:117:4:117:10:@W:BN116:@XP_MSG">mips_dvc.v(117)</a><!@TM:1190250740> | Removing sequential instance isys.imips_dvc.tmr_addr[31] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\mips_dvc.v:117:4:117:10:@W:BN116:@XP_MSG">mips_dvc.v(117)</a><!@TM:1190250740> | Removing sequential instance isys.imips_dvc.tmr_addr[30] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\mips_dvc.v:117:4:117:10:@W:BN116:@XP_MSG">mips_dvc.v(117)</a><!@TM:1190250740> | Removing sequential instance isys.imips_dvc.tmr_addr[29] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\mips_dvc.v:117:4:117:10:@W:BN116:@XP_MSG">mips_dvc.v(117)</a><!@TM:1190250740> | Removing sequential instance isys.imips_dvc.tmr_addr[28] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\mips_dvc.v:117:4:117:10:@W:BN116:@XP_MSG">mips_dvc.v(117)</a><!@TM:1190250740> | Removing sequential instance isys.imips_dvc.tmr_addr[27] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\mips_dvc.v:117:4:117:10:@W:BN116:@XP_MSG">mips_dvc.v(117)</a><!@TM:1190250740> | Removing sequential instance isys.imips_dvc.tmr_addr[26] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\mips_dvc.v:117:4:117:10:@W:BN116:@XP_MSG">mips_dvc.v(117)</a><!@TM:1190250740> | Removing sequential instance isys.imips_dvc.tmr_addr[25] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\mips_dvc.v:117:4:117:10:@W:BN116:@XP_MSG">mips_dvc.v(117)</a><!@TM:1190250740> | Removing sequential instance isys.imips_dvc.tmr_addr[24] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\mips_dvc.v:117:4:117:10:@W:BN116:@XP_MSG">mips_dvc.v(117)</a><!@TM:1190250740> | Removing sequential instance isys.imips_dvc.tmr_addr[23] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\mips_dvc.v:117:4:117:10:@W:BN116:@XP_MSG">mips_dvc.v(117)</a><!@TM:1190250740> | Removing sequential instance isys.imips_dvc.tmr_addr[22] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\mips_dvc.v:117:4:117:10:@W:BN116:@XP_MSG">mips_dvc.v(117)</a><!@TM:1190250740> | Removing sequential instance isys.imips_dvc.tmr_addr[21] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\mips_dvc.v:117:4:117:10:@W:BN116:@XP_MSG">mips_dvc.v(117)</a><!@TM:1190250740> | Removing sequential instance isys.imips_dvc.tmr_addr[20] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\mips_dvc.v:117:4:117:10:@W:BN116:@XP_MSG">mips_dvc.v(117)</a><!@TM:1190250740> | Removing sequential instance isys.imips_dvc.tmr_addr[19] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\mips_dvc.v:117:4:117:10:@W:BN116:@XP_MSG">mips_dvc.v(117)</a><!@TM:1190250740> | Removing sequential instance isys.imips_dvc.tmr_addr[18] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\mips_dvc.v:117:4:117:10:@W:BN116:@XP_MSG">mips_dvc.v(117)</a><!@TM:1190250740> | Removing sequential instance isys.imips_dvc.tmr_addr[17] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\mips_dvc.v:117:4:117:10:@W:BN116:@XP_MSG">mips_dvc.v(117)</a><!@TM:1190250740> | Removing sequential instance isys.imips_dvc.tmr_addr[16] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\mips_dvc.v:117:4:117:10:@W:BN116:@XP_MSG">mips_dvc.v(117)</a><!@TM:1190250740> | Removing sequential instance isys.imips_dvc.tmr_addr[15] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\mips_dvc.v:117:4:117:10:@W:BN116:@XP_MSG">mips_dvc.v(117)</a><!@TM:1190250740> | Removing sequential instance isys.imips_dvc.tmr_addr[14] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\mips_dvc.v:117:4:117:10:@W:BN116:@XP_MSG">mips_dvc.v(117)</a><!@TM:1190250740> | Removing sequential instance isys.imips_dvc.tmr_addr[13] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\mips_dvc.v:117:4:117:10:@W:BN116:@XP_MSG">mips_dvc.v(117)</a><!@TM:1190250740> | Removing sequential instance isys.imips_dvc.tmr_addr[12] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\mips_dvc.v:117:4:117:10:@W:BN116:@XP_MSG">mips_dvc.v(117)</a><!@TM:1190250740> | Removing sequential instance isys.imips_dvc.tmr_addr[11] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\mips_dvc.v:117:4:117:10:@W:BN116:@XP_MSG">mips_dvc.v(117)</a><!@TM:1190250740> | Removing sequential instance isys.imips_dvc.tmr_addr[10] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\mips_dvc.v:117:4:117:10:@W:BN116:@XP_MSG">mips_dvc.v(117)</a><!@TM:1190250740> | Removing sequential instance isys.imips_dvc.tmr_addr[9] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\mips_dvc.v:117:4:117:10:@W:BN116:@XP_MSG">mips_dvc.v(117)</a><!@TM:1190250740> | Removing sequential instance isys.imips_dvc.tmr_addr[8] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\mips_dvc.v:117:4:117:10:@W:BN116:@XP_MSG">mips_dvc.v(117)</a><!@TM:1190250740> | Removing sequential instance isys.imips_dvc.tmr_addr[7] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\mips_dvc.v:117:4:117:10:@W:BN116:@XP_MSG">mips_dvc.v(117)</a><!@TM:1190250740> | Removing sequential instance isys.imips_dvc.tmr_addr[6] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\mips_dvc.v:117:4:117:10:@W:BN116:@XP_MSG">mips_dvc.v(117)</a><!@TM:1190250740> | Removing sequential instance isys.imips_dvc.tmr_addr[5] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\mips_dvc.v:117:4:117:10:@W:BN116:@XP_MSG">mips_dvc.v(117)</a><!@TM:1190250740> | Removing sequential instance isys.imips_dvc.tmr_addr[4] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\mips_dvc.v:117:4:117:10:@W:BN116:@XP_MSG">mips_dvc.v(117)</a><!@TM:1190250740> | Removing sequential instance isys.imips_dvc.tmr_addr[3] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\mips_dvc.v:117:4:117:10:@W:BN116:@XP_MSG">mips_dvc.v(117)</a><!@TM:1190250740> | Removing sequential instance isys.imips_dvc.tmr_addr[2] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\mips_dvc.v:117:4:117:10:@W:BN116:@XP_MSG">mips_dvc.v(117)</a><!@TM:1190250740> | Removing sequential instance isys.imips_dvc.tmr_addr[1] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\mips_dvc.v:117:4:117:10:@W:BN116:@XP_MSG">mips_dvc.v(117)</a><!@TM:1190250740> | Removing sequential instance isys.imips_dvc.tmr_addr[0] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\dvc.v:45:4:45:10:@W:BN116:@XP_MSG">dvc.v(45)</a><!@TM:1190250740> | Removing sequential instance isys.imips_dvc.mips_tmr0.itmr_d.q of view:PrimLib.dffr(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\tools.v:104:111:104:117:@W:BN116:@XP_MSG">tools.v(104)</a><!@TM:1190250740> | Removing sequential instance isys.mips_core.iRF_stage.ins_reg.r32_o[31] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\tools.v:104:111:104:117:@W:BN116:@XP_MSG">tools.v(104)</a><!@TM:1190250740> | Removing sequential instance isys.mips_core.iRF_stage.ins_reg.r32_o[30] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\tools.v:104:111:104:117:@W:BN116:@XP_MSG">tools.v(104)</a><!@TM:1190250740> | Removing sequential instance isys.mips_core.iRF_stage.ins_reg.r32_o[29] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\tools.v:104:111:104:117:@W:BN116:@XP_MSG">tools.v(104)</a><!@TM:1190250740> | Removing sequential instance isys.mips_core.iRF_stage.ins_reg.r32_o[28] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\tools.v:104:111:104:117:@W:BN116:@XP_MSG">tools.v(104)</a><!@TM:1190250740> | Removing sequential instance isys.mips_core.iRF_stage.ins_reg.r32_o[27] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\tools.v:104:111:104:117:@W:BN116:@XP_MSG">tools.v(104)</a><!@TM:1190250740> | Removing sequential instance isys.mips_core.iRF_stage.ins_reg.r32_o[26] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
Warning: Found 28 combinational loops!
Each loop is reported with an instance in the loop
and nets connected to that instance.
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
1) instance isys.mips_core.decoder_pipe.idecoder.fsm_dly_1[0] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.fsm_dly_1[0], output net "isys.mips_core.BUS197[0]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.fsm_dly_2[0]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_436" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
2) instance isys.mips_core.decoder_pipe.idecoder.ext_ctl_1[0] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.ext_ctl_1[0], output net "isys.mips_core.decoder_pipe.BUS2072[0]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.N_1374" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
3) instance isys.mips_core.decoder_pipe.idecoder.ext_ctl_1[1] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.ext_ctl_1[1], output net "isys.mips_core.decoder_pipe.BUS2072[1]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.N_1375" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_436" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
4) instance isys.mips_core.decoder_pipe.idecoder.ext_ctl_1[2] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.ext_ctl_1[2], output net "isys.mips_core.decoder_pipe.BUS2072[2]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.ext_ctl_2[2]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_436" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
5) instance isys.mips_core.decoder_pipe.idecoder.rd_sel_1[0] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.rd_sel_1[0], output net "isys.mips_core.decoder_pipe.BUS2110[0]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.rd_sel_2[0]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_436" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
6) instance isys.mips_core.decoder_pipe.idecoder.rd_sel_1[1] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.rd_sel_1[1], output net "isys.mips_core.decoder_pipe.BUS2110[1]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.rd_sel_2[1]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_438" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.wb_we315" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
7) instance isys.mips_core.decoder_pipe.idecoder.cmp_ctl_1[0] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.cmp_ctl_1[0], output net "isys.mips_core.decoder_pipe.BUS2056[0]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.cmp_ctl_2[0]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_436" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
8) instance isys.mips_core.decoder_pipe.idecoder.cmp_ctl_1[1] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.cmp_ctl_1[1], output net "isys.mips_core.decoder_pipe.BUS2056[1]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.cmp_ctl_2[1]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_436" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
9) instance isys.mips_core.decoder_pipe.idecoder.cmp_ctl_1[2] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.cmp_ctl_1[2], output net "isys.mips_core.decoder_pipe.BUS2056[2]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.cmp_ctl_2[2]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_436" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
10) instance isys.mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[0] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[0], output net "isys.mips_core.decoder_pipe.BUS2102[0]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.N_1377" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
11) instance isys.mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[1] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[1], output net "isys.mips_core.decoder_pipe.BUS2102[1]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.pc_gen_ctl_2[1]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_436" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
12) instance isys.mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[2] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[2], output net "isys.mips_core.decoder_pipe.BUS2102[2]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.N_1260_i" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
13) instance isys.mips_core.decoder_pipe.idecoder.muxa_ctl_1[0] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.muxa_ctl_1[0], output net "isys.mips_core.decoder_pipe.BUS2086[0]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.muxa_ctl_2[0]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_436" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
14) instance isys.mips_core.decoder_pipe.idecoder.muxa_ctl_1[1] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.muxa_ctl_1[1], output net "isys.mips_core.decoder_pipe.BUS2086[1]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.muxa_ctl_2[1]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
15) instance isys.mips_core.decoder_pipe.idecoder.muxb_ctl_1[0] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.muxb_ctl_1[0], output net "isys.mips_core.decoder_pipe.BUS2094[0]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.muxb_ctl_2[0]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_436" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
16) instance isys.mips_core.decoder_pipe.idecoder.muxb_ctl_1[1] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.muxb_ctl_1[1], output net "isys.mips_core.decoder_pipe.BUS2094[1]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.muxb_ctl_2[1]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
17) instance isys.mips_core.decoder_pipe.idecoder.alu_func_1[0] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.alu_func_1[0], output net "isys.mips_core.decoder_pipe.BUS2040[0]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.alu_func_2[0]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_436" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
18) instance isys.mips_core.decoder_pipe.idecoder.alu_func_1[1] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.alu_func_1[1], output net "isys.mips_core.decoder_pipe.BUS2040[1]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.alu_func_2[1]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_436" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
19) instance isys.mips_core.decoder_pipe.idecoder.alu_func_1[2] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.alu_func_1[2], output net "isys.mips_core.decoder_pipe.BUS2040[2]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.N_1373" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
20) instance isys.mips_core.decoder_pipe.idecoder.alu_func_1[3] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.alu_func_1[3], output net "isys.mips_core.decoder_pipe.BUS2040[3]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.alu_func_2[3]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
21) instance isys.mips_core.decoder_pipe.idecoder.alu_func_1[4] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.alu_func_1[4], output net "isys.mips_core.decoder_pipe.BUS2040[4]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.alu_func_2[4]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_436" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
22) instance isys.mips_core.decoder_pipe.idecoder.dmem_ctl_1[0] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.dmem_ctl_1[0], output net "isys.mips_core.decoder_pipe.BUS2064[0]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.dmem_ctl_2[0]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
23) instance isys.mips_core.decoder_pipe.idecoder.dmem_ctl_1[1] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.dmem_ctl_1[1], output net "isys.mips_core.decoder_pipe.BUS2064[1]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.dmem_ctl_2[1]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_438" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.wb_we315" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
24) instance isys.mips_core.decoder_pipe.idecoder.dmem_ctl_1[2] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.dmem_ctl_1[2], output net "isys.mips_core.decoder_pipe.BUS2064[2]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.dmem_ctl_2[2]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_18_m" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_15" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
25) instance isys.mips_core.decoder_pipe.idecoder.dmem_ctl_1[3] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.dmem_ctl_1[3], output net "isys.mips_core.decoder_pipe.BUS2064[3]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.dmem_ctl_2[3]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_436" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
26) instance isys.mips_core.decoder_pipe.idecoder.alu_we[0] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.alu_we[0], output net "isys.mips_core.decoder_pipe.BUS2048[0]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.alu_we_1[0]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_436" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
27) instance isys.mips_core.decoder_pipe.idecoder.wb_mux[0] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.wb_mux[0], output net "isys.mips_core.decoder_pipe.BUS2118[0]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.wb_mux_1[0]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_436" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
28) instance isys.mips_core.decoder_pipe.idecoder.wb_we[0] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.wb_we[0], output net "isys.mips_core.decoder_pipe.BUS2126[0]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.wb_we_1[0]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_436" in work.mips_top(verilog)
End of loops
Warning: Found 28 combinational loops!
Each loop is reported with an instance in the loop
and nets connected to that instance.
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
1) instance isys.mips_core.decoder_pipe.idecoder.fsm_dly_1[0] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.fsm_dly_1[0], output net "isys.mips_core.BUS197[0]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.fsm_dly_2[0]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_436" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
2) instance isys.mips_core.decoder_pipe.idecoder.ext_ctl_1[0] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.ext_ctl_1[0], output net "isys.mips_core.decoder_pipe.BUS2072[0]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.N_1374" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
3) instance isys.mips_core.decoder_pipe.idecoder.ext_ctl_1[1] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.ext_ctl_1[1], output net "isys.mips_core.decoder_pipe.BUS2072[1]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.N_1375" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_436" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
4) instance isys.mips_core.decoder_pipe.idecoder.ext_ctl_1[2] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.ext_ctl_1[2], output net "isys.mips_core.decoder_pipe.BUS2072[2]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.ext_ctl_2[2]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_436" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
5) instance isys.mips_core.decoder_pipe.idecoder.rd_sel_1[0] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.rd_sel_1[0], output net "isys.mips_core.decoder_pipe.BUS2110[0]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.rd_sel_2[0]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_436" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
6) instance isys.mips_core.decoder_pipe.idecoder.rd_sel_1[1] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.rd_sel_1[1], output net "isys.mips_core.decoder_pipe.BUS2110[1]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.rd_sel_2[1]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_438" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.wb_we315" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
7) instance isys.mips_core.decoder_pipe.idecoder.cmp_ctl_1[0] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.cmp_ctl_1[0], output net "isys.mips_core.decoder_pipe.BUS2056[0]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.cmp_ctl_2[0]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_436" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
8) instance isys.mips_core.decoder_pipe.idecoder.cmp_ctl_1[1] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.cmp_ctl_1[1], output net "isys.mips_core.decoder_pipe.BUS2056[1]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.cmp_ctl_2[1]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_436" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
9) instance isys.mips_core.decoder_pipe.idecoder.cmp_ctl_1[2] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.cmp_ctl_1[2], output net "isys.mips_core.decoder_pipe.BUS2056[2]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.cmp_ctl_2[2]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_436" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
10) instance isys.mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[0] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[0], output net "isys.mips_core.decoder_pipe.BUS2102[0]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.N_1377" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
11) instance isys.mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[1] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[1], output net "isys.mips_core.decoder_pipe.BUS2102[1]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.pc_gen_ctl_2[1]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_436" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
12) instance isys.mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[2] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[2], output net "isys.mips_core.decoder_pipe.BUS2102[2]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.N_1260_i" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
13) instance isys.mips_core.decoder_pipe.idecoder.muxa_ctl_1[0] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.muxa_ctl_1[0], output net "isys.mips_core.decoder_pipe.BUS2086[0]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.muxa_ctl_2[0]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_436" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
14) instance isys.mips_core.decoder_pipe.idecoder.muxa_ctl_1[1] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.muxa_ctl_1[1], output net "isys.mips_core.decoder_pipe.BUS2086[1]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.muxa_ctl_2[1]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
15) instance isys.mips_core.decoder_pipe.idecoder.muxb_ctl_1[0] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.muxb_ctl_1[0], output net "isys.mips_core.decoder_pipe.BUS2094[0]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.muxb_ctl_2[0]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_436" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
16) instance isys.mips_core.decoder_pipe.idecoder.muxb_ctl_1[1] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.muxb_ctl_1[1], output net "isys.mips_core.decoder_pipe.BUS2094[1]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.muxb_ctl_2[1]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
17) instance isys.mips_core.decoder_pipe.idecoder.alu_func_1[0] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.alu_func_1[0], output net "isys.mips_core.decoder_pipe.BUS2040[0]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.alu_func_2[0]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_436" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
18) instance isys.mips_core.decoder_pipe.idecoder.alu_func_1[1] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.alu_func_1[1], output net "isys.mips_core.decoder_pipe.BUS2040[1]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.alu_func_2[1]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_436" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
19) instance isys.mips_core.decoder_pipe.idecoder.alu_func_1[2] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.alu_func_1[2], output net "isys.mips_core.decoder_pipe.BUS2040[2]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.N_1373" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
20) instance isys.mips_core.decoder_pipe.idecoder.alu_func_1[3] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.alu_func_1[3], output net "isys.mips_core.decoder_pipe.BUS2040[3]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.alu_func_2[3]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
21) instance isys.mips_core.decoder_pipe.idecoder.alu_func_1[4] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.alu_func_1[4], output net "isys.mips_core.decoder_pipe.BUS2040[4]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.alu_func_2[4]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_436" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
22) instance isys.mips_core.decoder_pipe.idecoder.dmem_ctl_1[0] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.dmem_ctl_1[0], output net "isys.mips_core.decoder_pipe.BUS2064[0]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.dmem_ctl_2[0]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
23) instance isys.mips_core.decoder_pipe.idecoder.dmem_ctl_1[1] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.dmem_ctl_1[1], output net "isys.mips_core.decoder_pipe.BUS2064[1]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.dmem_ctl_2[1]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_438" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.wb_we315" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
24) instance isys.mips_core.decoder_pipe.idecoder.dmem_ctl_1[2] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.dmem_ctl_1[2], output net "isys.mips_core.decoder_pipe.BUS2064[2]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.dmem_ctl_2[2]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_18_m" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_15" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
25) instance isys.mips_core.decoder_pipe.idecoder.dmem_ctl_1[3] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.dmem_ctl_1[3], output net "isys.mips_core.decoder_pipe.BUS2064[3]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.dmem_ctl_2[3]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_436" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
26) instance isys.mips_core.decoder_pipe.idecoder.alu_we[0] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.alu_we[0], output net "isys.mips_core.decoder_pipe.BUS2048[0]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.alu_we_1[0]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_436" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
27) instance isys.mips_core.decoder_pipe.idecoder.wb_mux[0] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.wb_mux[0], output net "isys.mips_core.decoder_pipe.BUS2118[0]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.wb_mux_1[0]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_436" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
28) instance isys.mips_core.decoder_pipe.idecoder.wb_we[0] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.wb_we[0], output net "isys.mips_core.decoder_pipe.BUS2126[0]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.wb_we_1[0]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_436" in work.mips_top(verilog)
End of loops
Warning: Found 28 combinational loops!
Each loop is reported with an instance in the loop
and nets connected to that instance.
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
1) instance isys.mips_core.decoder_pipe.idecoder.fsm_dly_1[0] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.fsm_dly_1[0], output net "isys.mips_core.BUS197[0]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.fsm_dly_2[0]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_436" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
2) instance isys.mips_core.decoder_pipe.idecoder.ext_ctl_1[0] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.ext_ctl_1[0], output net "isys.mips_core.decoder_pipe.BUS2072[0]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.N_1374" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
3) instance isys.mips_core.decoder_pipe.idecoder.ext_ctl_1[1] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.ext_ctl_1[1], output net "isys.mips_core.decoder_pipe.BUS2072[1]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.N_1375" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_436" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
4) instance isys.mips_core.decoder_pipe.idecoder.ext_ctl_1[2] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.ext_ctl_1[2], output net "isys.mips_core.decoder_pipe.BUS2072[2]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.ext_ctl_2[2]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_436" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
5) instance isys.mips_core.decoder_pipe.idecoder.rd_sel_1[0] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.rd_sel_1[0], output net "isys.mips_core.decoder_pipe.BUS2110[0]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.rd_sel_2[0]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_436" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
6) instance isys.mips_core.decoder_pipe.idecoder.rd_sel_1[1] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.rd_sel_1[1], output net "isys.mips_core.decoder_pipe.BUS2110[1]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.rd_sel_2[1]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_438" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.wb_we315" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
7) instance isys.mips_core.decoder_pipe.idecoder.cmp_ctl_1[0] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.cmp_ctl_1[0], output net "isys.mips_core.decoder_pipe.BUS2056[0]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.cmp_ctl_2[0]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_436" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
8) instance isys.mips_core.decoder_pipe.idecoder.cmp_ctl_1[1] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.cmp_ctl_1[1], output net "isys.mips_core.decoder_pipe.BUS2056[1]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.cmp_ctl_2[1]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_436" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
9) instance isys.mips_core.decoder_pipe.idecoder.cmp_ctl_1[2] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.cmp_ctl_1[2], output net "isys.mips_core.decoder_pipe.BUS2056[2]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.cmp_ctl_2[2]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_436" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
10) instance isys.mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[0] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[0], output net "isys.mips_core.decoder_pipe.BUS2102[0]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.N_1377" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
11) instance isys.mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[1] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[1], output net "isys.mips_core.decoder_pipe.BUS2102[1]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.pc_gen_ctl_2[1]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_436" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
12) instance isys.mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[2] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[2], output net "isys.mips_core.decoder_pipe.BUS2102[2]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.N_1260_i" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
13) instance isys.mips_core.decoder_pipe.idecoder.muxa_ctl_1[0] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.muxa_ctl_1[0], output net "isys.mips_core.decoder_pipe.BUS2086[0]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.muxa_ctl_2[0]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_436" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
14) instance isys.mips_core.decoder_pipe.idecoder.muxa_ctl_1[1] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.muxa_ctl_1[1], output net "isys.mips_core.decoder_pipe.BUS2086[1]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.muxa_ctl_2[1]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
15) instance isys.mips_core.decoder_pipe.idecoder.muxb_ctl_1[0] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.muxb_ctl_1[0], output net "isys.mips_core.decoder_pipe.BUS2094[0]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.muxb_ctl_2[0]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_436" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
16) instance isys.mips_core.decoder_pipe.idecoder.muxb_ctl_1[1] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.muxb_ctl_1[1], output net "isys.mips_core.decoder_pipe.BUS2094[1]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.muxb_ctl_2[1]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
17) instance isys.mips_core.decoder_pipe.idecoder.alu_func_1[0] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.alu_func_1[0], output net "isys.mips_core.decoder_pipe.BUS2040[0]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.alu_func_2[0]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_436" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
18) instance isys.mips_core.decoder_pipe.idecoder.alu_func_1[1] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.alu_func_1[1], output net "isys.mips_core.decoder_pipe.BUS2040[1]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.alu_func_2[1]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_436" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
19) instance isys.mips_core.decoder_pipe.idecoder.alu_func_1[2] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.alu_func_1[2], output net "isys.mips_core.decoder_pipe.BUS2040[2]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.N_1373" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
20) instance isys.mips_core.decoder_pipe.idecoder.alu_func_1[3] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.alu_func_1[3], output net "isys.mips_core.decoder_pipe.BUS2040[3]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.alu_func_2[3]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
21) instance isys.mips_core.decoder_pipe.idecoder.alu_func_1[4] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.alu_func_1[4], output net "isys.mips_core.decoder_pipe.BUS2040[4]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.alu_func_2[4]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_436" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
22) instance isys.mips_core.decoder_pipe.idecoder.dmem_ctl_1[0] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.dmem_ctl_1[0], output net "isys.mips_core.decoder_pipe.BUS2064[0]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.dmem_ctl_2[0]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
23) instance isys.mips_core.decoder_pipe.idecoder.dmem_ctl_1[1] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.dmem_ctl_1[1], output net "isys.mips_core.decoder_pipe.BUS2064[1]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.dmem_ctl_2[1]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_438" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.wb_we315" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
24) instance isys.mips_core.decoder_pipe.idecoder.dmem_ctl_1[2] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.dmem_ctl_1[2], output net "isys.mips_core.decoder_pipe.BUS2064[2]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.dmem_ctl_2[2]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_18_m" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_15" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
25) instance isys.mips_core.decoder_pipe.idecoder.dmem_ctl_1[3] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.dmem_ctl_1[3], output net "isys.mips_core.decoder_pipe.BUS2064[3]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.dmem_ctl_2[3]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_436" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
26) instance isys.mips_core.decoder_pipe.idecoder.alu_we[0] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.alu_we[0], output net "isys.mips_core.decoder_pipe.BUS2048[0]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.alu_we_1[0]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_436" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
27) instance isys.mips_core.decoder_pipe.idecoder.wb_mux[0] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.wb_mux[0], output net "isys.mips_core.decoder_pipe.BUS2118[0]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.wb_mux_1[0]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_436" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
28) instance isys.mips_core.decoder_pipe.idecoder.wb_we[0] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.wb_we[0], output net "isys.mips_core.decoder_pipe.BUS2126[0]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.wb_we_1[0]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_436" in work.mips_top(verilog)
End of loops
Warning: Found 28 combinational loops!
Each loop is reported with an instance in the loop
and nets connected to that instance.
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
1) instance isys.mips_core.decoder_pipe.idecoder.fsm_dly_1[0] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.fsm_dly_1[0], output net "isys.mips_core.BUS197[0]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.fsm_dly_2[0]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_436" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
2) instance isys.mips_core.decoder_pipe.idecoder.ext_ctl_1[0] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.ext_ctl_1[0], output net "isys.mips_core.decoder_pipe.BUS2072[0]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.N_1374" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
3) instance isys.mips_core.decoder_pipe.idecoder.ext_ctl_1[1] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.ext_ctl_1[1], output net "isys.mips_core.decoder_pipe.BUS2072[1]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.N_1375" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_436" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
4) instance isys.mips_core.decoder_pipe.idecoder.ext_ctl_1[2] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.ext_ctl_1[2], output net "isys.mips_core.decoder_pipe.BUS2072[2]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.ext_ctl_2[2]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_436" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
5) instance isys.mips_core.decoder_pipe.idecoder.rd_sel_1[0] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.rd_sel_1[0], output net "isys.mips_core.decoder_pipe.BUS2110[0]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.rd_sel_2[0]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_436" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
6) instance isys.mips_core.decoder_pipe.idecoder.rd_sel_1[1] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.rd_sel_1[1], output net "isys.mips_core.decoder_pipe.BUS2110[1]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.rd_sel_2[1]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_438" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.wb_we315" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
7) instance isys.mips_core.decoder_pipe.idecoder.cmp_ctl_1[0] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.cmp_ctl_1[0], output net "isys.mips_core.decoder_pipe.BUS2056[0]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.cmp_ctl_2[0]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_436" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
8) instance isys.mips_core.decoder_pipe.idecoder.cmp_ctl_1[1] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.cmp_ctl_1[1], output net "isys.mips_core.decoder_pipe.BUS2056[1]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.cmp_ctl_2[1]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_436" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
9) instance isys.mips_core.decoder_pipe.idecoder.cmp_ctl_1[2] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.cmp_ctl_1[2], output net "isys.mips_core.decoder_pipe.BUS2056[2]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.cmp_ctl_2[2]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_436" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
10) instance isys.mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[0] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[0], output net "isys.mips_core.decoder_pipe.BUS2102[0]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.N_1377" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
11) instance isys.mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[1] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[1], output net "isys.mips_core.decoder_pipe.BUS2102[1]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.pc_gen_ctl_2[1]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_436" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
12) instance isys.mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[2] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[2], output net "isys.mips_core.decoder_pipe.BUS2102[2]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.N_1260_i" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
13) instance isys.mips_core.decoder_pipe.idecoder.muxa_ctl_1[0] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.muxa_ctl_1[0], output net "isys.mips_core.decoder_pipe.BUS2086[0]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.muxa_ctl_2[0]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_436" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
14) instance isys.mips_core.decoder_pipe.idecoder.muxa_ctl_1[1] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.muxa_ctl_1[1], output net "isys.mips_core.decoder_pipe.BUS2086[1]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.muxa_ctl_2[1]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
15) instance isys.mips_core.decoder_pipe.idecoder.muxb_ctl_1[0] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.muxb_ctl_1[0], output net "isys.mips_core.decoder_pipe.BUS2094[0]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.muxb_ctl_2[0]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_436" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
16) instance isys.mips_core.decoder_pipe.idecoder.muxb_ctl_1[1] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.muxb_ctl_1[1], output net "isys.mips_core.decoder_pipe.BUS2094[1]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.muxb_ctl_2[1]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
17) instance isys.mips_core.decoder_pipe.idecoder.alu_func_1[0] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.alu_func_1[0], output net "isys.mips_core.decoder_pipe.BUS2040[0]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.alu_func_2[0]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_436" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
18) instance isys.mips_core.decoder_pipe.idecoder.alu_func_1[1] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.alu_func_1[1], output net "isys.mips_core.decoder_pipe.BUS2040[1]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.alu_func_2[1]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_436" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
19) instance isys.mips_core.decoder_pipe.idecoder.alu_func_1[2] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.alu_func_1[2], output net "isys.mips_core.decoder_pipe.BUS2040[2]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.N_1373" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
20) instance isys.mips_core.decoder_pipe.idecoder.alu_func_1[3] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.alu_func_1[3], output net "isys.mips_core.decoder_pipe.BUS2040[3]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.alu_func_2[3]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
21) instance isys.mips_core.decoder_pipe.idecoder.alu_func_1[4] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.alu_func_1[4], output net "isys.mips_core.decoder_pipe.BUS2040[4]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.alu_func_2[4]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_436" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
22) instance isys.mips_core.decoder_pipe.idecoder.dmem_ctl_1[0] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.dmem_ctl_1[0], output net "isys.mips_core.decoder_pipe.BUS2064[0]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.dmem_ctl_2[0]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
23) instance isys.mips_core.decoder_pipe.idecoder.dmem_ctl_1[1] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.dmem_ctl_1[1], output net "isys.mips_core.decoder_pipe.BUS2064[1]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.dmem_ctl_2[1]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_438" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.wb_we315" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
24) instance isys.mips_core.decoder_pipe.idecoder.dmem_ctl_1[2] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.dmem_ctl_1[2], output net "isys.mips_core.decoder_pipe.BUS2064[2]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.dmem_ctl_2[2]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_18_m" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_15" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
25) instance isys.mips_core.decoder_pipe.idecoder.dmem_ctl_1[3] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.dmem_ctl_1[3], output net "isys.mips_core.decoder_pipe.BUS2064[3]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.dmem_ctl_2[3]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_436" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
26) instance isys.mips_core.decoder_pipe.idecoder.alu_we[0] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.alu_we[0], output net "isys.mips_core.decoder_pipe.BUS2048[0]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.alu_we_1[0]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_436" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
27) instance isys.mips_core.decoder_pipe.idecoder.wb_mux[0] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.wb_mux[0], output net "isys.mips_core.decoder_pipe.BUS2118[0]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.wb_mux_1[0]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_436" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping</font>
28) instance isys.mips_core.decoder_pipe.idecoder.wb_we[0] work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.wb_we[0], output net "isys.mips_core.decoder_pipe.BUS2126[0]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.wb_we_1[0]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_436" in work.mips_top(verilog)
End of loops
Warning: Found 28 combinational loops!
Each loop is reported with an instance in the loop
and nets connected to that instance.
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping at net isys.mips_core.BUS197[0]</font>
1) instance work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.fsm_dly_1[0], output net "isys.mips_core.BUS197[0]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.fsm_dly_2[0]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_436" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping at net isys.mips_core.decoder_pipe.BUS2072[0]</font>
2) instance work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.ext_ctl_1[0], output net "isys.mips_core.decoder_pipe.BUS2072[0]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.N_1374" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping at net isys.mips_core.decoder_pipe.BUS2072[1]</font>
3) instance work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.ext_ctl_1[1], output net "isys.mips_core.decoder_pipe.BUS2072[1]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.N_1375" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_436" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping at net isys.mips_core.decoder_pipe.BUS2072[2]</font>
4) instance work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.ext_ctl_1[2], output net "isys.mips_core.decoder_pipe.BUS2072[2]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.ext_ctl_2[2]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_436" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping at net isys.mips_core.decoder_pipe.BUS2110[0]</font>
5) instance work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.rd_sel_1[0], output net "isys.mips_core.decoder_pipe.BUS2110[0]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.rd_sel_2[0]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_436" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping at net isys.mips_core.decoder_pipe.BUS2110[1]</font>
6) instance work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.rd_sel_1[1], output net "isys.mips_core.decoder_pipe.BUS2110[1]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.rd_sel_2[1]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_438" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.wb_we315" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping at net isys.mips_core.decoder_pipe.BUS2056[0]</font>
7) instance work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.cmp_ctl_1[0], output net "isys.mips_core.decoder_pipe.BUS2056[0]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.cmp_ctl_2[0]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_436" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping at net isys.mips_core.decoder_pipe.BUS2056[1]</font>
8) instance work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.cmp_ctl_1[1], output net "isys.mips_core.decoder_pipe.BUS2056[1]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.cmp_ctl_2[1]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_436" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping at net isys.mips_core.decoder_pipe.BUS2056[2]</font>
9) instance work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.cmp_ctl_1[2], output net "isys.mips_core.decoder_pipe.BUS2056[2]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.cmp_ctl_2[2]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_436" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping at net isys.mips_core.decoder_pipe.BUS2102[0]</font>
10) instance work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[0], output net "isys.mips_core.decoder_pipe.BUS2102[0]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.N_1377" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping at net isys.mips_core.decoder_pipe.BUS2102[1]</font>
11) instance work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[1], output net "isys.mips_core.decoder_pipe.BUS2102[1]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.pc_gen_ctl_2[1]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_436" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping at net isys.mips_core.decoder_pipe.BUS2102[2]</font>
12) instance work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[2], output net "isys.mips_core.decoder_pipe.BUS2102[2]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.N_1260_i_0" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping at net isys.mips_core.decoder_pipe.BUS2086[0]</font>
13) instance work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.muxa_ctl_1[0], output net "isys.mips_core.decoder_pipe.BUS2086[0]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.muxa_ctl_2[0]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_436" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping at net isys.mips_core.decoder_pipe.BUS2086[1]</font>
14) instance work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.muxa_ctl_1[1], output net "isys.mips_core.decoder_pipe.BUS2086[1]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.muxa_ctl_2[1]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping at net isys.mips_core.decoder_pipe.BUS2094[0]</font>
15) instance work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.muxb_ctl_1[0], output net "isys.mips_core.decoder_pipe.BUS2094[0]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.muxb_ctl_2[0]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_436" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping at net isys.mips_core.decoder_pipe.BUS2094[1]</font>
16) instance work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.muxb_ctl_1[1], output net "isys.mips_core.decoder_pipe.BUS2094[1]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.muxb_ctl_2[1]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping at net isys.mips_core.decoder_pipe.BUS2040[0]</font>
17) instance work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.alu_func_1[0], output net "isys.mips_core.decoder_pipe.BUS2040[0]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.alu_func_2[0]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_436" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping at net isys.mips_core.decoder_pipe.BUS2040[1]</font>
18) instance work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.alu_func_1[1], output net "isys.mips_core.decoder_pipe.BUS2040[1]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.alu_func_2[1]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_436" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping at net isys.mips_core.decoder_pipe.BUS2040[2]</font>
19) instance work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.alu_func_1[2], output net "isys.mips_core.decoder_pipe.BUS2040[2]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.N_1373" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping at net isys.mips_core.decoder_pipe.BUS2040[3]</font>
20) instance work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.alu_func_1[3], output net "isys.mips_core.decoder_pipe.BUS2040[3]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.alu_func_2[3]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping at net isys.mips_core.decoder_pipe.BUS2040[4]</font>
21) instance work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.alu_func_1[4], output net "isys.mips_core.decoder_pipe.BUS2040[4]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.alu_func_2[4]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_436" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping at net isys.mips_core.decoder_pipe.BUS2064[0]</font>
22) instance work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.dmem_ctl_1[0], output net "isys.mips_core.decoder_pipe.BUS2064[0]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.dmem_ctl_2[0]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping at net isys.mips_core.decoder_pipe.BUS2064[1]</font>
23) instance work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.dmem_ctl_1[1], output net "isys.mips_core.decoder_pipe.BUS2064[1]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.dmem_ctl_2[1]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_438" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.wb_we315" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping at net isys.mips_core.decoder_pipe.BUS2064[2]</font>
24) instance work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.dmem_ctl_1[2], output net "isys.mips_core.decoder_pipe.BUS2064[2]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.dmem_ctl_2[2]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_18_m" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_ins_i_15" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping at net isys.mips_core.decoder_pipe.BUS2064[3]</font>
25) instance work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.dmem_ctl_1[3], output net "isys.mips_core.decoder_pipe.BUS2064[3]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.dmem_ctl_2[3]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_436" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping at net isys.mips_core.decoder_pipe.BUS2048[0]</font>
26) instance work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.alu_we[0], output net "isys.mips_core.decoder_pipe.BUS2048[0]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.alu_we_1[0]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_436" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping at net isys.mips_core.decoder_pipe.BUS2118[0]</font>
27) instance work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.wb_mux[0], output net "isys.mips_core.decoder_pipe.BUS2118[0]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.wb_mux_1[0]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_436" in work.mips_top(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190250740> | Found combinational loop during mapping at net isys.mips_core.decoder_pipe.BUS2126[0]</font>
28) instance work.mips_top(verilog)-isys.mips_core.decoder_pipe.idecoder.wb_we[0], output net "isys.mips_core.decoder_pipe.BUS2126[0]" in work.mips_top(verilog)
input nets to instance:
net "isys.mips_core.decoder_pipe.idecoder.wb_we_1[0]" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.un1_wb_we312" in work.mips_top(verilog)
net "isys.mips_core.decoder_pipe.idecoder.N_436" in work.mips_top(verilog)
End of loops