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Subversion Repositories mips789

[/] [mips789/] [branches/] [avendor/] [synplify_prj/] [rev_1/] [fifo512_cyclone.srr] - Rev 53

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#Program: Synplify Pro 8.1
#OS: Windows_NT

$ Start of Compile
#Fri Oct 10 10:26:44 2008

Synplicity Verilog Compiler, version 3.1.0, Build 049R, built May  3 2005
Copyright (C) 1994-2005, Synplicity Inc.  All Rights Reserved

@I::"C:\Program Files\Synplicity\fpga_81\lib\altera\altera.v"
@I::"C:\Program Files\Synplicity\fpga_81\lib\altera\cyclone.v"
@I::"C:\Program Files\Synplicity\fpga_81\lib\altera\altera_mf.v"
@I::"C:\Program Files\Synplicity\fpga_81\lib\altera\altera_lpm.v"
@I::"E:\mips789\mips789\rtl\verilog\EXEC_stage.v"
@I:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":"E:\mips789\mips789\rtl\verilog\include.h"
@I:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":"E:\mips789\mips789\rtl\verilog\include.h"
@N:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":694:80:694:92|Read parallel_case directive 
@I::"E:\mips789\mips789\rtl\verilog\RF_components.v"
@I:"E:\mips789\mips789\rtl\verilog\RF_components.v":"E:\mips789\mips789\rtl\verilog\include.h"
@I::"E:\mips789\mips789\rtl\verilog\RF_stage.v"
@I:"E:\mips789\mips789\rtl\verilog\RF_stage.v":"E:\mips789\mips789\rtl\verilog\include.h"
@I::"E:\mips789\mips789\rtl\verilog\ctl_fsm.v"
@I:"E:\mips789\mips789\rtl\verilog\ctl_fsm.v":"E:\mips789\mips789\rtl\verilog\include.h"
@N:"E:\mips789\mips789\rtl\verilog\ctl_fsm.v":58:43:58:55|Read parallel_case directive 
@N:"E:\mips789\mips789\rtl\verilog\ctl_fsm.v":58:57:58:65|Read full_case directive 
@W: CG286 :"E:\mips789\mips789\rtl\verilog\ctl_fsm.v":58:8:58:11|Case statement has both a full_case directive and a default clause.  The full_case directive is ignored.
@I::"E:\mips789\mips789\rtl\verilog\decode_pipe.v"
@I:"E:\mips789\mips789\rtl\verilog\decode_pipe.v":"E:\mips789\mips789\rtl\verilog\include.h"
@N:"E:\mips789\mips789\rtl\verilog\decode_pipe.v":31:34:31:46|Read parallel_case directive 
@N:"E:\mips789\mips789\rtl\verilog\decode_pipe.v":34:45:34:57|Read parallel_case directive 
@N:"E:\mips789\mips789\rtl\verilog\decode_pipe.v":533:47:533:59|Read parallel_case directive 
@N:"E:\mips789\mips789\rtl\verilog\decode_pipe.v":835:49:835:61|Read parallel_case directive 
@I::"E:\mips789\mips789\rtl\verilog\dvc.v"
@I:"E:\mips789\mips789\rtl\verilog\dvc.v":"E:\mips789\mips789\rtl\verilog\include.h"
@I::"E:\mips789\mips789\rtl\verilog\fifo.v"
@I:"E:\mips789\mips789\rtl\verilog\fifo.v":"E:\mips789\mips789\rtl\verilog\include.h"
@I::"E:\mips789\mips789\rtl\verilog\forward.v"
@I:"E:\mips789\mips789\rtl\verilog\forward.v":"E:\mips789\mips789\rtl\verilog\include.h"
@I::"E:\mips789\mips789\rtl\verilog\mem_module.v"
@I:"E:\mips789\mips789\rtl\verilog\mem_module.v":"E:\mips789\mips789\rtl\verilog\include.h"
@I::"E:\mips789\mips789\rtl\verilog\mips_core.v"
@I:"E:\mips789\mips789\rtl\verilog\mips_core.v":"E:\mips789\mips789\rtl\verilog\include.h"
@I::"E:\mips789\mips789\rtl\verilog\mips_dvc.v"
@I:"E:\mips789\mips789\rtl\verilog\mips_dvc.v":"E:\mips789\mips789\rtl\verilog\include.h"
@I::"E:\mips789\mips789\rtl\verilog\mips_sys.v"
@I:"E:\mips789\mips789\rtl\verilog\mips_sys.v":"E:\mips789\mips789\rtl\verilog\include.h"
@I::"E:\mips789\mips789\rtl\verilog\mips_uart.v"
@I:"E:\mips789\mips789\rtl\verilog\mips_uart.v":"E:\mips789\mips789\rtl\verilog\include.h"
@I::"E:\mips789\mips789\rtl\verilog\ram_module.v"
@I:"E:\mips789\mips789\rtl\verilog\ram_module.v":"E:\mips789\mips789\rtl\verilog\include.h"
@I::"E:\mips789\mips789\rtl\verilog\sim_ram.v"
@I::"E:\mips789\mips789\rtl\verilog\ulit.v"
@I:"E:\mips789\mips789\rtl\verilog\ulit.v":"E:\mips789\mips789\rtl\verilog\include.h"
@I::"E:\mips789\mips789\rtl\verilog\altera\fifo512_cyclone.v"
@N:"E:\mips789\mips789\rtl\verilog\altera\fifo512_cyclone.v":39:12:39:24|Read directive translate_off 
@N:"E:\mips789\mips789\rtl\verilog\altera\fifo512_cyclone.v":41:12:41:23|Read directive translate_on 
@N:"E:\mips789\mips789\rtl\verilog\altera\fifo512_cyclone.v":74:16:74:28|Read directive translate_off 
@N:"E:\mips789\mips789\rtl\verilog\altera\fifo512_cyclone.v":81:16:81:27|Read directive translate_on 
Verilog syntax check successful!
Options changed - recompiling
Selecting top level module mips_sys
@N:"E:\mips789\mips789\rtl\verilog\mem_module.v":78:7:78:25|Synthesizing module infile_dmem_ctl_reg

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <30> of dmem_addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <29> of dmem_addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <28> of dmem_addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <27> of dmem_addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <26> of dmem_addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <25> of dmem_addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <24> of dmem_addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <23> of dmem_addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <22> of dmem_addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <21> of dmem_addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <20> of dmem_addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <19> of dmem_addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <18> of dmem_addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <17> of dmem_addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <16> of dmem_addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <15> of dmem_addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <14> of dmem_addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <13> of dmem_addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <12> of dmem_addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <11> of dmem_addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <10> of dmem_addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <9> of dmem_addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <8> of dmem_addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <7> of dmem_addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <6> of dmem_addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <5> of dmem_addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <4> of dmem_addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <3> of dmem_addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <2> of dmem_addr_i[31:0] is unused

@N:"E:\mips789\mips789\rtl\verilog\mem_module.v":96:7:96:18|Synthesizing module mem_addr_ctl

@W: CL118 :"E:\mips789\mips789\rtl\verilog\mem_module.v":102:4:102:7|Latch generated from always block for signal wr_en[3:0], probably caused by a missing assignment in an if or case stmt
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <31> of addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <30> of addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <29> of addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <28> of addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <27> of addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <26> of addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <25> of addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <24> of addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <23> of addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <22> of addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <21> of addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <20> of addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <19> of addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <18> of addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <17> of addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <16> of addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <15> of addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <14> of addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <13> of addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <12> of addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <11> of addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <10> of addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <9> of addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <8> of addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <7> of addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <6> of addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <5> of addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <4> of addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <3> of addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <2> of addr_i[31:0] is unused

@N:"E:\mips789\mips789\rtl\verilog\mem_module.v":199:7:199:17|Synthesizing module mem_din_ctl

@N:"E:\mips789\mips789\rtl\verilog\mem_module.v":130:7:130:18|Synthesizing module mem_dout_ctl

@W: CL118 :"E:\mips789\mips789\rtl\verilog\mem_module.v":161:4:161:7|Latch generated from always block for signal dout[31:0], probably caused by a missing assignment in an if or case stmt
@N:"E:\mips789\mips789\rtl\verilog\mem_module.v":4:7:4:16|Synthesizing module mem_module

@N:"E:\mips789\mips789\rtl\verilog\ulit.v":3:7:3:13|Synthesizing module cal_cpi

@N:"E:\mips789\mips789\rtl\verilog\ctl_fsm.v":2:7:2:13|Synthesizing module ctl_FSM

@W: CL118 :"E:\mips789\mips789\rtl\verilog\ctl_fsm.v":58:8:58:11|Latch generated from always block for signal zz_is_nop, probably caused by a missing assignment in an if or case stmt
@W: CL113 :"E:\mips789\mips789\rtl\verilog\ctl_fsm.v":58:8:58:11|Feedback mux created for signal iack.
@W: CL118 :"E:\mips789\mips789\rtl\verilog\ctl_fsm.v":58:8:58:11|Latch generated from always block for signal iack, probably caused by a missing assignment in an if or case stmt
@W: CL118 :"E:\mips789\mips789\rtl\verilog\ctl_fsm.v":58:8:58:11|Latch generated from always block for signal next_delay_counter_Sreg0[5:0], probably caused by a missing assignment in an if or case stmt
@N: CL201 :"E:\mips789\mips789\rtl\verilog\ctl_fsm.v":224:4:224:9|Trying to extract state machine for register CurrState_Sreg0
Extracted state machine for register CurrState_Sreg0
State machine has 9 reachable states with original encodings of:
   0000
   0001
   0010
   0011
   0100
   0101
   0110
   0111
   1000
@N:"E:\mips789\mips789\rtl\verilog\RF_components.v":50:7:50:12|Synthesizing module pc_gen

@N:"E:\mips789\mips789\rtl\verilog\RF_components.v":30:7:30:13|Synthesizing module compare

@W: CG133 :"E:\mips789\mips789\rtl\verilog\RF_components.v":36:14:36:16|No assignment to sum
@N:"E:\mips789\mips789\rtl\verilog\RF_components.v":2:7:2:9|Synthesizing module ext

@W:"E:\mips789\mips789\rtl\verilog\RF_components.v":3:21:3:25|Input port bit <31> of ins_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\RF_components.v":3:21:3:25|Input port bit <30> of ins_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\RF_components.v":3:21:3:25|Input port bit <29> of ins_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\RF_components.v":3:21:3:25|Input port bit <28> of ins_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\RF_components.v":3:21:3:25|Input port bit <27> of ins_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\RF_components.v":3:21:3:25|Input port bit <26> of ins_i[31:0] is unused

@N:"E:\mips789\mips789\rtl\verilog\ulit.v":104:7:104:21|Synthesizing module r32_reg_clr_cls

@N: CG179 :"E:\mips789\mips789\rtl\verilog\ulit.v":104:167:104:171|Removing redundant assignment
@N:"E:\mips789\mips789\rtl\verilog\ulit.v":30:7:30:10|Synthesizing module jack

@W:"E:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|Input port bit <31> of ins_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|Input port bit <30> of ins_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|Input port bit <29> of ins_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|Input port bit <28> of ins_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|Input port bit <27> of ins_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|Input port bit <26> of ins_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|Input port bit <10> of ins_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|Input port bit <9> of ins_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|Input port bit <8> of ins_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|Input port bit <7> of ins_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|Input port bit <6> of ins_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|Input port bit <5> of ins_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|Input port bit <4> of ins_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|Input port bit <3> of ins_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|Input port bit <2> of ins_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|Input port bit <1> of ins_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|Input port bit <0> of ins_i[31:0] is unused

@N:"E:\mips789\mips789\rtl\verilog\ulit.v":64:7:64:12|Synthesizing module rd_sel

@N:"E:\mips789\mips789\rtl\verilog\RF_components.v":90:7:90:15|Synthesizing module reg_array

@N: CL134 :"E:\mips789\mips789\rtl\verilog\RF_components.v":140:4:140:9|Found RAM reg_bank, depth=32, width=32
@N: CL134 :"E:\mips789\mips789\rtl\verilog\RF_components.v":140:4:140:9|Found RAM reg_bank, depth=32, width=32
@N:"E:\mips789\mips789\rtl\verilog\forward.v":25:7:25:13|Synthesizing module fwd_mux

@N:"E:\mips789\mips789\rtl\verilog\RF_stage.v":3:7:3:14|Synthesizing module rf_stage

@W: CS149 :"E:\mips789\mips789\rtl\verilog\RF_stage.v":91:24:91:29|Port width mismatch for port ins_no.  Formal has width 101, Actual 1
@W: CS149 :"E:\mips789\mips789\rtl\verilog\RF_stage.v":90:24:90:29|Port width mismatch for port clk_no.  Formal has width 101, Actual 1
@W: CL168 :"E:\mips789\mips789\rtl\verilog\RF_stage.v":87:12:87:18|Pruning instance CAL_CPI - not in use ...

@N:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":521:7:521:15|Synthesizing module muldiv_ff

@W: CL169 :"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":572:4:572:9|Pruning Register LAST_CYCLE_DEAL_SECTION.eqz 

@W: CL169 :"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":572:4:572:9|Pruning Register LAST_CYCLE_DEAL_SECTION.LAST_CYCLE_DEAL_SECTION_DEFAULT.op1s_eq_h64 

@W: CL169 :"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":572:4:572:9|Pruning Register LAST_CYCLE_DEAL_SECTION.eqop2 

@W: CL169 :"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":572:4:572:9|Pruning Register LAST_CYCLE_DEAL_SECTION.eqnop2 

@W: CL169 :"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":572:4:572:9|Pruning Register LAST_CYCLE_DEAL_SECTION.LAST_CYCLE_DEAL_SECTION_DEFAULT.op1s_eq_op2s 

@W: CL169 :"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":572:4:572:9|Pruning Register START_SECTION.over[32:0] 

@N:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":233:7:233:9|Synthesizing module alu

@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":238:16:238:16|No assignment to wire c

@N:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":266:4:266:14|Synthesizing module shifter_tak

@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":270:25:270:50|Input port bit <31> of shift_amount[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":270:25:270:50|Input port bit <30> of shift_amount[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":270:25:270:50|Input port bit <29> of shift_amount[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":270:25:270:50|Input port bit <28> of shift_amount[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":270:25:270:50|Input port bit <27> of shift_amount[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":270:25:270:50|Input port bit <26> of shift_amount[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":270:25:270:50|Input port bit <25> of shift_amount[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":270:25:270:50|Input port bit <24> of shift_amount[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":270:25:270:50|Input port bit <23> of shift_amount[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":270:25:270:50|Input port bit <22> of shift_amount[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":270:25:270:50|Input port bit <21> of shift_amount[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":270:25:270:50|Input port bit <20> of shift_amount[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":270:25:270:50|Input port bit <19> of shift_amount[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":270:25:270:50|Input port bit <18> of shift_amount[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":270:25:270:50|Input port bit <17> of shift_amount[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":270:25:270:50|Input port bit <16> of shift_amount[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":270:25:270:50|Input port bit <15> of shift_amount[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":270:25:270:50|Input port bit <14> of shift_amount[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":270:25:270:50|Input port bit <13> of shift_amount[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":270:25:270:50|Input port bit <12> of shift_amount[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":270:25:270:50|Input port bit <11> of shift_amount[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":270:25:270:50|Input port bit <10> of shift_amount[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":270:25:270:50|Input port bit <9> of shift_amount[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":270:25:270:50|Input port bit <8> of shift_amount[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":270:25:270:50|Input port bit <7> of shift_amount[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":270:25:270:50|Input port bit <6> of shift_amount[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":270:25:270:50|Input port bit <5> of shift_amount[31:0] is unused

@N:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":138:7:138:13|Synthesizing module big_alu

@N:"E:\mips789\mips789\rtl\verilog\ulit.v":22:7:22:11|Synthesizing module add32

@N:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":188:7:188:14|Synthesizing module alu_muxa

@N:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":212:7:212:14|Synthesizing module alu_muxb

@N:"E:\mips789\mips789\rtl\verilog\ulit.v":150:7:150:13|Synthesizing module r32_reg

@N:"E:\mips789\mips789\rtl\verilog\ulit.v":173:7:173:17|Synthesizing module r32_reg_cls

@N: CG179 :"E:\mips789\mips789\rtl\verilog\ulit.v":173:132:173:136|Removing redundant assignment
@N:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":3:7:3:16|Synthesizing module exec_stage

@N:"E:\mips789\mips789\rtl\verilog\ulit.v":54:7:54:10|Synthesizing module or32

@N:"E:\mips789\mips789\rtl\verilog\decode_pipe.v":2:7:2:13|Synthesizing module decoder

@W: CL118 :"E:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Latch generated from always block for signal alu_func[4:0], probably caused by a missing assignment in an if or case stmt
@W: CL118 :"E:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Latch generated from always block for signal pc_gen_ctl[2:0], probably caused by a missing assignment in an if or case stmt
@W: CL118 :"E:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Latch generated from always block for signal fsm_dly[2:0], probably caused by a missing assignment in an if or case stmt
@W: CL118 :"E:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Latch generated from always block for signal ext_ctl[2:0], probably caused by a missing assignment in an if or case stmt
@W: CL118 :"E:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Latch generated from always block for signal rd_sel[1:0], probably caused by a missing assignment in an if or case stmt
@W: CL118 :"E:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Latch generated from always block for signal muxb_ctl[1:0], probably caused by a missing assignment in an if or case stmt
@W: CL118 :"E:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Latch generated from always block for signal muxa_ctl[1:0], probably caused by a missing assignment in an if or case stmt
@W: CL118 :"E:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Latch generated from always block for signal alu_we[0], probably caused by a missing assignment in an if or case stmt
@W: CL118 :"E:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Latch generated from always block for signal dmem_ctl[3:0], probably caused by a missing assignment in an if or case stmt
@W: CL118 :"E:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Latch generated from always block for signal cmp_ctl[2:0], probably caused by a missing assignment in an if or case stmt
@W: CL118 :"E:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Latch generated from always block for signal wb_we[0], probably caused by a missing assignment in an if or case stmt
@W: CL118 :"E:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Latch generated from always block for signal wb_mux[0], probably caused by a missing assignment in an if or case stmt
@W:"E:\mips789\mips789\rtl\verilog\decode_pipe.v":3:20:3:24|Input port bit <15> of ins_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\decode_pipe.v":3:20:3:24|Input port bit <14> of ins_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\decode_pipe.v":3:20:3:24|Input port bit <13> of ins_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\decode_pipe.v":3:20:3:24|Input port bit <12> of ins_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\decode_pipe.v":3:20:3:24|Input port bit <11> of ins_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\decode_pipe.v":3:20:3:24|Input port bit <10> of ins_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\decode_pipe.v":3:20:3:24|Input port bit <9> of ins_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\decode_pipe.v":3:20:3:24|Input port bit <8> of ins_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\decode_pipe.v":3:20:3:24|Input port bit <7> of ins_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\decode_pipe.v":3:20:3:24|Input port bit <6> of ins_i[31:0] is unused

@N:"E:\mips789\mips789\rtl\verilog\ulit.v":90:7:90:26|Synthesizing module muxb_ctl_reg_clr_cls

@N: CG179 :"E:\mips789\mips789\rtl\verilog\ulit.v":90:202:90:211|Removing redundant assignment
@N:"E:\mips789\mips789\rtl\verilog\ulit.v":94:7:94:28|Synthesizing module wb_mux_ctl_reg_clr_cls

@N: CG179 :"E:\mips789\mips789\rtl\verilog\ulit.v":94:216:94:227|Removing redundant assignment
@N:"E:\mips789\mips789\rtl\verilog\ulit.v":95:7:95:23|Synthesizing module wb_we_reg_clr_cls

@N: CG179 :"E:\mips789\mips789\rtl\verilog\ulit.v":95:181:95:187|Removing redundant assignment
@N:"E:\mips789\mips789\rtl\verilog\ulit.v":141:7:141:15|Synthesizing module wb_we_reg

@N:"E:\mips789\mips789\rtl\verilog\ulit.v":117:7:117:24|Synthesizing module wb_mux_ctl_reg_clr

@N:"E:\mips789\mips789\rtl\verilog\ulit.v":113:7:113:22|Synthesizing module muxb_ctl_reg_clr

@N:"E:\mips789\mips789\rtl\verilog\ulit.v":116:7:116:22|Synthesizing module dmem_ctl_reg_clr

@N:"E:\mips789\mips789\rtl\verilog\ulit.v":114:7:114:22|Synthesizing module alu_func_reg_clr

@N:"E:\mips789\mips789\rtl\verilog\ulit.v":112:7:112:22|Synthesizing module muxa_ctl_reg_clr

@N:"E:\mips789\mips789\rtl\verilog\ulit.v":140:7:140:20|Synthesizing module wb_mux_ctl_reg

@N:"E:\mips789\mips789\rtl\verilog\ulit.v":118:7:118:19|Synthesizing module wb_we_reg_clr

@N:"E:\mips789\mips789\rtl\verilog\ulit.v":86:7:86:25|Synthesizing module cmp_ctl_reg_clr_cls

@N: CG179 :"E:\mips789\mips789\rtl\verilog\ulit.v":86:195:86:203|Removing redundant assignment
@N:"E:\mips789\mips789\rtl\verilog\ulit.v":115:7:115:20|Synthesizing module alu_we_reg_clr

@N:"E:\mips789\mips789\rtl\verilog\ulit.v":91:7:91:26|Synthesizing module alu_func_reg_clr_cls

@N: CG179 :"E:\mips789\mips789\rtl\verilog\ulit.v":91:202:91:211|Removing redundant assignment
@N:"E:\mips789\mips789\rtl\verilog\ulit.v":93:7:93:26|Synthesizing module dmem_ctl_reg_clr_cls

@N: CG179 :"E:\mips789\mips789\rtl\verilog\ulit.v":93:202:93:211|Removing redundant assignment
@N:"E:\mips789\mips789\rtl\verilog\ulit.v":84:7:84:25|Synthesizing module ext_ctl_reg_clr_cls

@N: CG179 :"E:\mips789\mips789\rtl\verilog\ulit.v":84:195:84:203|Removing redundant assignment
@N:"E:\mips789\mips789\rtl\verilog\ulit.v":85:7:85:24|Synthesizing module rd_sel_reg_clr_cls

@N: CG179 :"E:\mips789\mips789\rtl\verilog\ulit.v":85:188:85:195|Removing redundant assignment
@N:"E:\mips789\mips789\rtl\verilog\ulit.v":92:7:92:24|Synthesizing module alu_we_reg_clr_cls

@N: CG179 :"E:\mips789\mips789\rtl\verilog\ulit.v":92:188:92:195|Removing redundant assignment
@N:"E:\mips789\mips789\rtl\verilog\ulit.v":89:7:89:26|Synthesizing module muxa_ctl_reg_clr_cls

@N: CG179 :"E:\mips789\mips789\rtl\verilog\ulit.v":89:202:89:211|Removing redundant assignment
@N:"E:\mips789\mips789\rtl\verilog\ulit.v":87:7:87:28|Synthesizing module pc_gen_ctl_reg_clr_cls

@N: CG179 :"E:\mips789\mips789\rtl\verilog\ulit.v":87:216:87:227|Removing redundant assignment
@N:"E:\mips789\mips789\rtl\verilog\ulit.v":139:7:139:18|Synthesizing module dmem_ctl_reg

@N:"E:\mips789\mips789\rtl\verilog\decode_pipe.v":1090:7:1090:19|Synthesizing module pipelinedregs

@N:"E:\mips789\mips789\rtl\verilog\decode_pipe.v":1419:7:1419:17|Synthesizing module decode_pipe

@N:"E:\mips789\mips789\rtl\verilog\forward.v":12:7:12:18|Synthesizing module forward_node

@N:"E:\mips789\mips789\rtl\verilog\forward.v":4:7:4:15|Synthesizing module fw_latch5

@N:"E:\mips789\mips789\rtl\verilog\forward.v":41:7:41:13|Synthesizing module forward

@N:"E:\mips789\mips789\rtl\verilog\ulit.v":149:7:149:12|Synthesizing module r5_reg

@N:"E:\mips789\mips789\rtl\verilog\ulit.v":43:7:43:12|Synthesizing module wb_mux

@N:"E:\mips789\mips789\rtl\verilog\mips_core.v":3:7:3:15|Synthesizing module mips_core

@N:"E:\mips789\mips789\rtl\verilog\mips_uart.v":210:7:210:15|Synthesizing module uart_read

@N: CL201 :"E:\mips789\mips789\rtl\verilog\mips_uart.v":274:4:274:9|Trying to extract state machine for register ua_state
Extracted state machine for register ua_state
State machine has 5 reachable states with original encodings of:
   000
   001
   010
   011
   100
@N:"E:\mips789\mips789\rtl\verilog\mips_uart.v":3:7:3:11|Synthesizing module rxd_d

@N:"C:\Program Files\Synplicity\fpga_81\lib\altera\altera_mf.v":3709:7:3709:12|Synthesizing module scfifo

        lpm_width=32'b00000000000000000000000000001000
        lpm_widthu=32'b00000000000000000000000000001001
        lpm_numwords=32'b00000000000000000000001000000000
        lpm_showahead=24'b010011110100011001000110
        intended_device_family=56'b01000011011110010110001101101100011011110110111001100101
        almost_full_value=32'b00000000000000000000000000000000
        almost_empty_value=32'b00000000000000000000000000000000
        underflow_checking=16'b0100111101001110
        overflow_checking=16'b0100111101001110
        allow_rwcycle_when_full=24'b010011110100011001000110
        lpm_hint=152'b01010010010000010100110101011111010000100100110001001111010000110100101101011111010101000101100101010000010001010011110101000001010101010101010001001111
        use_eab=16'b0100111101001110
        add_ram_output_register=24'b010011110100011001000110
        maximum_depth=32'b00000000000000000000000000000000
        lpm_type=48'b011100110110001101100110011010010110011001101111
   Generated name = scfifo_Z1
@N:"E:\mips789\mips789\rtl\verilog\altera\fifo512_cyclone.v":42:7:42:21|Synthesizing module fifo512_cyclone

@N:"E:\mips789\mips789\rtl\verilog\mips_uart.v":70:7:70:16|Synthesizing module uart_write

@W: CG133 :"E:\mips789\mips789\rtl\verilog\mips_uart.v":94:9:94:20|No assignment to write_done_n
@N: CL201 :"E:\mips789\mips789\rtl\verilog\mips_uart.v":168:4:168:9|Trying to extract state machine for register ua_state
Extracted state machine for register ua_state
State machine has 8 reachable states with original encodings of:
   000
   001
   010
   011
   100
   101
   110
   111
@N:"E:\mips789\mips789\rtl\verilog\mips_uart.v":12:7:12:11|Synthesizing module uart0

@W:"E:\mips789\mips789\rtl\verilog\mips_uart.v":38:9:38:17|No assignment to wire w_rxd_clr

@N:"E:\mips789\mips789\rtl\verilog\dvc.v":52:7:52:16|Synthesizing module seg7led_cv

@N:"E:\mips789\mips789\rtl\verilog\dvc.v":43:7:43:11|Synthesizing module tmr_d

@N:"E:\mips789\mips789\rtl\verilog\dvc.v":3:7:3:10|Synthesizing module tmr0

@N:"E:\mips789\mips789\rtl\verilog\mips_dvc.v":3:7:3:14|Synthesizing module mips_dvc

@N:"E:\mips789\mips789\rtl\verilog\mips_sys.v":4:7:4:14|Synthesizing module mips_sys

@W:"E:\mips789\mips789\rtl\verilog\mips_sys.v":78:16:78:24|No assignment to wire data2core

@W:"E:\mips789\mips789\rtl\verilog\mips_sys.v":79:16:79:23|No assignment to wire data2mem

@W:"E:\mips789\mips789\rtl\verilog\mips_sys.v":80:16:80:23|No assignment to wire ins2core

@W:"E:\mips789\mips789\rtl\verilog\mips_sys.v":81:16:81:23|No assignment to wire mem_Addr

@W:"E:\mips789\mips789\rtl\verilog\mips_sys.v":82:16:82:17|No assignment to wire pc

@W:"E:\mips789\mips789\rtl\verilog\mips_sys.v":83:15:83:19|No assignment to wire wr_en

@END
Process took 0h:00m:11s realtime, 0h:00m:11s cputime
# Fri Oct 10 10:26:56 2008

###########################################################[
Version 8.1
Synplicity Altera Technology Mapper, Version 8.1.0, Build 539R, Built May  6 2005
Copyright (C) 1994-2005, Synplicity Inc.  All Rights Reserved



Running FSM Explorer ...

Automatic dissolve at startup in view:work.mem_module(verilog) of i_mem_din_ctl(mem_din_ctl)
Automatic dissolve at startup in view:work.mem_module(verilog) of i_mem_addr_ctl(mem_addr_ctl)
Automatic dissolve at startup in view:work.mem_module(verilog) of dmem_ctl_post(infile_dmem_ctl_reg)
Automatic dissolve at startup in view:work.rf_stage(verilog) of rs_fwd_rs(fwd_mux)
Automatic dissolve at startup in view:work.rf_stage(verilog) of rf_fwd_rt(fwd_mux)
Automatic dissolve at startup in view:work.rf_stage(verilog) of jack2(jack)
Automatic dissolve at startup in view:work.rf_stage(verilog) of jack1(jack)
Automatic dissolve at startup in view:work.rf_stage(verilog) of ins_reg(r32_reg_clr_cls)
Automatic dissolve at startup in view:work.rf_stage(verilog) of i_pc_gen(pc_gen)
Automatic dissolve at startup in view:work.exec_stage(verilog) of spc(r32_reg_cls)
Automatic dissolve at startup in view:work.exec_stage(verilog) of pc_nxt(r32_reg)
Automatic dissolve at startup in view:work.exec_stage(verilog) of i_alu_muxb(alu_muxb)
Automatic dissolve at startup in view:work.exec_stage(verilog) of i_alu_muxa(alu_muxa)
Automatic dissolve at startup in view:work.exec_stage(verilog) of dmem_fw_mux(fwd_mux)
Automatic dissolve at startup in view:work.exec_stage(verilog) of add4(add32)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U9(dmem_ctl_reg)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U8(pc_gen_ctl_reg_clr_cls)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U7(muxa_ctl_reg_clr_cls)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U6(alu_we_reg_clr_cls)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U5(rd_sel_reg_clr_cls)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U4(ext_ctl_reg_clr_cls)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U3(dmem_ctl_reg_clr_cls)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U26(alu_func_reg_clr_cls)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U24(alu_we_reg_clr)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U22(wb_we_reg)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U21(wb_mux_ctl_reg)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U20(wb_we_reg)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U2(cmp_ctl_reg_clr_cls)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U19(wb_we_reg_clr)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U18(wb_mux_ctl_reg)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U17(muxa_ctl_reg_clr)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U16(alu_func_reg_clr)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U15(dmem_ctl_reg_clr)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U14(muxb_ctl_reg_clr)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U13(wb_mux_ctl_reg_clr)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U12(wb_we_reg)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U11(wb_we_reg_clr_cls)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U10(wb_mux_ctl_reg_clr_cls)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U1(muxb_ctl_reg_clr_cls)
Automatic dissolve at startup in view:work.decode_pipe(verilog) of pipereg(pipelinedregs)
Automatic dissolve at startup in view:work.forward(verilog) of fw_reg_rnt(fw_latch5)
Automatic dissolve at startup in view:work.forward(verilog) of fw_reg_rns(fw_latch5)
Automatic dissolve at startup in view:work.mips_core(verilog) of wb_mux(wb_mux)
Automatic dissolve at startup in view:work.mips_core(verilog) of rt_reg(r32_reg)
Automatic dissolve at startup in view:work.mips_core(verilog) of rs_reg(r32_reg)
Automatic dissolve at startup in view:work.mips_core(verilog) of rnd_pass2(r5_reg)
Automatic dissolve at startup in view:work.mips_core(verilog) of rnd_pass1(r5_reg)
Automatic dissolve at startup in view:work.mips_core(verilog) of rnd_pass0(r5_reg)
Automatic dissolve at startup in view:work.mips_core(verilog) of pc(r32_reg)
Automatic dissolve at startup in view:work.mips_core(verilog) of ext_reg(r32_reg)
Automatic dissolve at startup in view:work.mips_core(verilog) of cop_dout_reg(r32_reg)
Automatic dissolve at startup in view:work.mips_core(verilog) of cop_data_reg(r32_reg)
Automatic dissolve at startup in view:work.mips_core(verilog) of cop_data_or(or32)
Automatic dissolve at startup in view:work.mips_core(verilog) of alu_pass1(r32_reg)
Automatic dissolve at startup in view:work.mips_core(verilog) of alu_pass0(r32_reg)
Automatic dissolve at startup in view:work.mips_core(verilog) of iexec_stage(exec_stage)
Automatic dissolve at startup in view:work.mips_core(verilog) of iRF_stage(rf_stage)
Automatic dissolve at startup in view:work.mips_core(verilog) of MEM_CTL(mem_module)
Automatic dissolve at startup in view:work.uart_write(verilog) of fifo(fifo512_cyclone)
Automatic dissolve at startup in view:work.uart0(verilog) of rxd_rdy_hold_lw(rxd_d)
Automatic dissolve at startup in view:work.tmr0(verilog) of itmr_d(tmr_d)
Warning: Found 30 combinational loops!
         Each loop is reported with an instance in the loop
         and nets connected to that instance.
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net fsm_dly_1[0]
1) instance work.decoder(verilog)-fsm_dly_1[0], output net "fsm_dly_1[0]" in work.decoder(verilog)
    input nets to instance:
        net "fsm_dly_2[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net fsm_dly_1[1]
2) instance work.decoder(verilog)-fsm_dly_1[2:1], output net "fsm_dly_1[1]" in work.decoder(verilog)
    input nets to instance:
        net "fsm_dly_2[1]" in work.decoder(verilog)
        net "fsm_dly_2[2]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net fsm_dly_1[2]
3) instance work.decoder(verilog)-fsm_dly_1[2:1], output net "fsm_dly_1[2]" in work.decoder(verilog)
    input nets to instance:
        net "fsm_dly_2[1]" in work.decoder(verilog)
        net "fsm_dly_2[2]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net ext_ctl_1[0]
4) instance work.decoder(verilog)-ext_ctl_1[0], output net "ext_ctl_1[0]" in work.decoder(verilog)
    input nets to instance:
        net "ext_ctl_2[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_23" in work.decoder(verilog)
        net "un1_ins_i_20" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net ext_ctl_1[1]
5) instance work.decoder(verilog)-ext_ctl_1[1], output net "ext_ctl_1[1]" in work.decoder(verilog)
    input nets to instance:
        net "ext_ctl_2[1]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net ext_ctl_1[2]
6) instance work.decoder(verilog)-ext_ctl_1[2], output net "ext_ctl_1[2]" in work.decoder(verilog)
    input nets to instance:
        net "ext_ctl_2[2]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net rd_sel_1[0]
7) instance work.decoder(verilog)-rd_sel_1[0], output net "rd_sel_1[0]" in work.decoder(verilog)
    input nets to instance:
        net "rd_sel_2[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net rd_sel_1[1]
8) instance work.decoder(verilog)-rd_sel_1[1], output net "rd_sel_1[1]" in work.decoder(verilog)
    input nets to instance:
        net "rd_sel_2[1]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_22" in work.decoder(verilog)
        net "fsm_dly373" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net cmp_ctl_1[0]
9) instance work.decoder(verilog)-cmp_ctl_1[0], output net "cmp_ctl_1[0]" in work.decoder(verilog)
    input nets to instance:
        net "cmp_ctl_2[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net cmp_ctl_1[1]
10) instance work.decoder(verilog)-cmp_ctl_1[1], output net "cmp_ctl_1[1]" in work.decoder(verilog)
    input nets to instance:
        net "cmp_ctl_2[1]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net cmp_ctl_1[2]
11) instance work.decoder(verilog)-cmp_ctl_1[2], output net "cmp_ctl_1[2]" in work.decoder(verilog)
    input nets to instance:
        net "cmp_ctl_2[2]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net pc_gen_ctl_1[0]
12) instance work.decoder(verilog)-pc_gen_ctl_1[0], output net "pc_gen_ctl_1[0]" in work.decoder(verilog)
    input nets to instance:
        net "pc_gen_ctl_2[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_23" in work.decoder(verilog)
        net "un1_ins_i_20" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net pc_gen_ctl_1[1]
13) instance work.decoder(verilog)-pc_gen_ctl_1[1], output net "pc_gen_ctl_1[1]" in work.decoder(verilog)
    input nets to instance:
        net "pc_gen_ctl_2[1]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net pc_gen_ctl_1[2]
14) instance work.decoder(verilog)-pc_gen_ctl_1[2], output net "pc_gen_ctl_1[2]" in work.decoder(verilog)
    input nets to instance:
        net "pc_gen_ctl_2[2]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_23" in work.decoder(verilog)
        net "un1_ins_i_20" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net muxa_ctl_1[0]
15) instance work.decoder(verilog)-muxa_ctl_1[0], output net "muxa_ctl_1[0]" in work.decoder(verilog)
    input nets to instance:
        net "muxa_ctl_2[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net muxa_ctl_1[1]
16) instance work.decoder(verilog)-muxa_ctl_1[1], output net "muxa_ctl_1[1]" in work.decoder(verilog)
    input nets to instance:
        net "muxa_ctl_2[1]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_23" in work.decoder(verilog)
        net "un1_ins_i_20" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net muxb_ctl_1[0]
17) instance work.decoder(verilog)-muxb_ctl_1[0], output net "muxb_ctl_1[0]" in work.decoder(verilog)
    input nets to instance:
        net "muxb_ctl_2[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net muxb_ctl_1[1]
18) instance work.decoder(verilog)-muxb_ctl_1[1], output net "muxb_ctl_1[1]" in work.decoder(verilog)
    input nets to instance:
        net "muxb_ctl_2[1]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_23" in work.decoder(verilog)
        net "un1_ins_i_20" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net alu_func_1[0]
19) instance work.decoder(verilog)-alu_func_1[0], output net "alu_func_1[0]" in work.decoder(verilog)
    input nets to instance:
        net "alu_func_2[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net alu_func_1[1]
20) instance work.decoder(verilog)-alu_func_1[1], output net "alu_func_1[1]" in work.decoder(verilog)
    input nets to instance:
        net "alu_func_2[1]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net alu_func_1[2]
21) instance work.decoder(verilog)-alu_func_1[2], output net "alu_func_1[2]" in work.decoder(verilog)
    input nets to instance:
        net "alu_func_2[2]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_23" in work.decoder(verilog)
        net "un1_ins_i_20" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net alu_func_1[3]
22) instance work.decoder(verilog)-alu_func_1[3], output net "alu_func_1[3]" in work.decoder(verilog)
    input nets to instance:
        net "alu_func_2[3]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_23" in work.decoder(verilog)
        net "un1_ins_i_20" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net alu_func_1[4]
23) instance work.decoder(verilog)-alu_func_1[4], output net "alu_func_1[4]" in work.decoder(verilog)
    input nets to instance:
        net "alu_func_2[4]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net dmem_ctl_1[0]
24) instance work.decoder(verilog)-dmem_ctl_1[0], output net "dmem_ctl_1[0]" in work.decoder(verilog)
    input nets to instance:
        net "dmem_ctl_2[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_23" in work.decoder(verilog)
        net "un1_ins_i_20" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net dmem_ctl_1[1]
25) instance work.decoder(verilog)-dmem_ctl_1[1], output net "dmem_ctl_1[1]" in work.decoder(verilog)
    input nets to instance:
        net "dmem_ctl_2[1]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_22" in work.decoder(verilog)
        net "fsm_dly373" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net dmem_ctl_1[2]
26) instance work.decoder(verilog)-dmem_ctl_1[2], output net "dmem_ctl_1[2]" in work.decoder(verilog)
    input nets to instance:
        net "dmem_ctl_2[2]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_24" in work.decoder(verilog)
        net "un1_ins_i_15" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net dmem_ctl_1[3]
27) instance work.decoder(verilog)-dmem_ctl_1[3], output net "dmem_ctl_1[3]" in work.decoder(verilog)
    input nets to instance:
        net "dmem_ctl_2[3]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net alu_we[0]
28) instance work.decoder(verilog)-alu_we[0], output net "alu_we[0]" in work.decoder(verilog)
    input nets to instance:
        net "alu_we_1[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net wb_mux[0]
29) instance work.decoder(verilog)-wb_mux[0], output net "wb_mux[0]" in work.decoder(verilog)
    input nets to instance:
        net "wb_mux_1[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net wb_we[0]
30) instance work.decoder(verilog)-wb_we[0], output net "wb_we[0]" in work.decoder(verilog)
    input nets to instance:
        net "wb_we_1[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
End of loops
RTL optimization done.
Warning: Found 30 combinational loops!
         Each loop is reported with an instance in the loop
         and nets connected to that instance.
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net fsm_dly_1[0]
1) instance work.decoder(verilog)-fsm_dly_1[0], output net "fsm_dly_1[0]" in work.decoder(verilog)
    input nets to instance:
        net "fsm_dly_2[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net fsm_dly_1[1]
2) instance work.decoder(verilog)-fsm_dly_1[2:1], output net "fsm_dly_1[1]" in work.decoder(verilog)
    input nets to instance:
        net "fsm_dly_2[1]" in work.decoder(verilog)
        net "fsm_dly_2[2]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net fsm_dly_1[2]
3) instance work.decoder(verilog)-fsm_dly_1[2:1], output net "fsm_dly_1[2]" in work.decoder(verilog)
    input nets to instance:
        net "fsm_dly_2[1]" in work.decoder(verilog)
        net "fsm_dly_2[2]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net wb_mux_1[0]
4) instance work.decoder(verilog)-wb_mux_1[0], output net "wb_mux_1[0]" in work.decoder(verilog)
    input nets to instance:
        net "un1_alu_we_3_sqmuxa_4" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "un1_alu_we_3_sqmuxa" in work.decoder(verilog)
        net "wb_mux[0]" in work.decoder(verilog)
        net "un1_fsm_dly365" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net wb_we_1[0]
5) instance work.decoder(verilog)-wb_we_1[0], output net "wb_we_1[0]" in work.decoder(verilog)
    input nets to instance:
        net "un1_alu_we_3_sqmuxa_3" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "un1_alu_we_3_sqmuxa" in work.decoder(verilog)
        net "wb_we[0]" in work.decoder(verilog)
        net "un1_fsm_dly362" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net alu_func_2[0]
6) instance work.decoder(verilog)-alu_func_2[4:0], output net "alu_func_2[0]" in work.decoder(verilog)
    input nets to instance:
        net "alu_func_0_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_1_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_2_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_3_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_4_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_5_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_6_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_7_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_8_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_9_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_10_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_11_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_12_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_13_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_14_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_15_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_16_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_17_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_18_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_19_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_20_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_21_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_22_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_23_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_24_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_25_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_26_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_27_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_28_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_0_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_1_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_2_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_3_sqmuxa" in work.decoder(verilog)
        net "alu_func_1[0]" in work.decoder(verilog)
        net "alu_func_1[1]" in work.decoder(verilog)
        net "alu_func_1[2]" in work.decoder(verilog)
        net "alu_func_1[3]" in work.decoder(verilog)
        net "alu_func_1[4]" in work.decoder(verilog)
        net "alu_we_4_sqmuxa" in work.decoder(verilog)
        net "alu_func_1[0]" in work.decoder(verilog)
        net "alu_func_1[1]" in work.decoder(verilog)
        net "alu_func_1[2]" in work.decoder(verilog)
        net "alu_func_1[3]" in work.decoder(verilog)
        net "alu_func_1[4]" in work.decoder(verilog)
        net "fsm_dly350" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly351" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly352" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly353" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly354" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly355" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly356" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly357" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly358" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly359" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly360" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly361" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly362" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly363" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
        net "alu_func_1[0]" in work.decoder(verilog)
        net "alu_func_1[1]" in work.decoder(verilog)
        net "alu_func_1[2]" in work.decoder(verilog)
        net "alu_func_1[3]" in work.decoder(verilog)
        net "alu_func_1[4]" in work.decoder(verilog)
        net "fsm_dly365" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly366" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly367" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly368" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly369" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly370" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net alu_func_2[1]
7) instance work.decoder(verilog)-alu_func_2[4:0], output net "alu_func_2[1]" in work.decoder(verilog)
    input nets to instance:
        net "alu_func_0_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_1_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_2_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_3_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_4_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_5_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_6_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_7_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_8_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_9_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_10_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_11_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_12_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_13_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_14_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_15_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_16_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_17_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_18_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_19_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_20_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_21_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_22_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_23_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_24_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_25_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_26_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_27_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_28_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_0_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_1_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_2_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_3_sqmuxa" in work.decoder(verilog)
        net "alu_func_1[0]" in work.decoder(verilog)
        net "alu_func_1[1]" in work.decoder(verilog)
        net "alu_func_1[2]" in work.decoder(verilog)
        net "alu_func_1[3]" in work.decoder(verilog)
        net "alu_func_1[4]" in work.decoder(verilog)
        net "alu_we_4_sqmuxa" in work.decoder(verilog)
        net "alu_func_1[0]" in work.decoder(verilog)
        net "alu_func_1[1]" in work.decoder(verilog)
        net "alu_func_1[2]" in work.decoder(verilog)
        net "alu_func_1[3]" in work.decoder(verilog)
        net "alu_func_1[4]" in work.decoder(verilog)
        net "fsm_dly350" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly351" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly352" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly353" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly354" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly355" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly356" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly357" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly358" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly359" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly360" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly361" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly362" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly363" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
        net "alu_func_1[0]" in work.decoder(verilog)
        net "alu_func_1[1]" in work.decoder(verilog)
        net "alu_func_1[2]" in work.decoder(verilog)
        net "alu_func_1[3]" in work.decoder(verilog)
        net "alu_func_1[4]" in work.decoder(verilog)
        net "fsm_dly365" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly366" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly367" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly368" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly369" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly370" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net alu_func_2[2]
8) instance work.decoder(verilog)-alu_func_2[4:0], output net "alu_func_2[2]" in work.decoder(verilog)
    input nets to instance:
        net "alu_func_0_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_1_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_2_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_3_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_4_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_5_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_6_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_7_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_8_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_9_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_10_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_11_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_12_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_13_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_14_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_15_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_16_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_17_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_18_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_19_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_20_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_21_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_22_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_23_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_24_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_25_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_26_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_27_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_28_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_0_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_1_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_2_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_3_sqmuxa" in work.decoder(verilog)
        net "alu_func_1[0]" in work.decoder(verilog)
        net "alu_func_1[1]" in work.decoder(verilog)
        net "alu_func_1[2]" in work.decoder(verilog)
        net "alu_func_1[3]" in work.decoder(verilog)
        net "alu_func_1[4]" in work.decoder(verilog)
        net "alu_we_4_sqmuxa" in work.decoder(verilog)
        net "alu_func_1[0]" in work.decoder(verilog)
        net "alu_func_1[1]" in work.decoder(verilog)
        net "alu_func_1[2]" in work.decoder(verilog)
        net "alu_func_1[3]" in work.decoder(verilog)
        net "alu_func_1[4]" in work.decoder(verilog)
        net "fsm_dly350" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly351" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly352" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly353" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly354" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly355" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly356" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly357" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly358" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly359" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly360" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly361" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly362" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly363" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
        net "alu_func_1[0]" in work.decoder(verilog)
        net "alu_func_1[1]" in work.decoder(verilog)
        net "alu_func_1[2]" in work.decoder(verilog)
        net "alu_func_1[3]" in work.decoder(verilog)
        net "alu_func_1[4]" in work.decoder(verilog)
        net "fsm_dly365" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly366" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly367" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly368" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly369" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly370" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net alu_func_2[3]
9) instance work.decoder(verilog)-alu_func_2[4:0], output net "alu_func_2[3]" in work.decoder(verilog)
    input nets to instance:
        net "alu_func_0_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_1_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_2_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_3_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_4_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_5_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_6_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_7_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_8_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_9_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_10_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_11_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_12_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_13_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_14_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_15_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_16_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_17_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_18_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_19_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_20_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_21_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_22_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_23_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_24_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_25_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_26_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_27_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_28_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_0_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_1_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_2_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_3_sqmuxa" in work.decoder(verilog)
        net "alu_func_1[0]" in work.decoder(verilog)
        net "alu_func_1[1]" in work.decoder(verilog)
        net "alu_func_1[2]" in work.decoder(verilog)
        net "alu_func_1[3]" in work.decoder(verilog)
        net "alu_func_1[4]" in work.decoder(verilog)
        net "alu_we_4_sqmuxa" in work.decoder(verilog)
        net "alu_func_1[0]" in work.decoder(verilog)
        net "alu_func_1[1]" in work.decoder(verilog)
        net "alu_func_1[2]" in work.decoder(verilog)
        net "alu_func_1[3]" in work.decoder(verilog)
        net "alu_func_1[4]" in work.decoder(verilog)
        net "fsm_dly350" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly351" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly352" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly353" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly354" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly355" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly356" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly357" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly358" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly359" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly360" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly361" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly362" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly363" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
        net "alu_func_1[0]" in work.decoder(verilog)
        net "alu_func_1[1]" in work.decoder(verilog)
        net "alu_func_1[2]" in work.decoder(verilog)
        net "alu_func_1[3]" in work.decoder(verilog)
        net "alu_func_1[4]" in work.decoder(verilog)
        net "fsm_dly365" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly366" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly367" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly368" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly369" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly370" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net alu_func_2[4]
10) instance work.decoder(verilog)-alu_func_2[4:0], output net "alu_func_2[4]" in work.decoder(verilog)
    input nets to instance:
        net "alu_func_0_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_1_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_2_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_3_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_4_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_5_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_6_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_7_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_8_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_9_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_10_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_11_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_12_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_13_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_14_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_15_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_16_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_17_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_18_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_19_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_20_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_21_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_22_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_23_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_24_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_25_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_26_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_27_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_28_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_0_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_1_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_2_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_3_sqmuxa" in work.decoder(verilog)
        net "alu_func_1[0]" in work.decoder(verilog)
        net "alu_func_1[1]" in work.decoder(verilog)
        net "alu_func_1[2]" in work.decoder(verilog)
        net "alu_func_1[3]" in work.decoder(verilog)
        net "alu_func_1[4]" in work.decoder(verilog)
        net "alu_we_4_sqmuxa" in work.decoder(verilog)
        net "alu_func_1[0]" in work.decoder(verilog)
        net "alu_func_1[1]" in work.decoder(verilog)
        net "alu_func_1[2]" in work.decoder(verilog)
        net "alu_func_1[3]" in work.decoder(verilog)
        net "alu_func_1[4]" in work.decoder(verilog)
        net "fsm_dly350" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly351" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly352" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly353" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly354" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly355" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly356" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly357" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly358" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly359" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly360" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly361" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly362" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly363" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
        net "alu_func_1[0]" in work.decoder(verilog)
        net "alu_func_1[1]" in work.decoder(verilog)
        net "alu_func_1[2]" in work.decoder(verilog)
        net "alu_func_1[3]" in work.decoder(verilog)
        net "alu_func_1[4]" in work.decoder(verilog)
        net "fsm_dly365" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly366" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly367" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly368" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly369" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly370" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net alu_we_1[0]
11) instance work.decoder(verilog)-alu_we_1[0], output net "alu_we_1[0]" in work.decoder(verilog)
    input nets to instance:
        net "alu_func_0_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_1_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_2_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_3_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_4_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_5_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_6_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_7_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_8_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_9_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_10_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_11_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_12_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_13_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_14_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_15_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_16_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_17_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_18_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_19_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_20_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_21_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_22_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_23_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_24_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_25_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_26_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_27_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_28_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_0_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_1_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_2_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_3_sqmuxa" in work.decoder(verilog)
        net "alu_we[0]" in work.decoder(verilog)
        net "alu_we_4_sqmuxa" in work.decoder(verilog)
        net "alu_we[0]" in work.decoder(verilog)
        net "fsm_dly350" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly351" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly352" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly353" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly354" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly355" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly356" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly357" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly358" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly359" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly360" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly361" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly362" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly363" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
        net "alu_we[0]" in work.decoder(verilog)
        net "fsm_dly365" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly366" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly367" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly368" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly369" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly370" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net ext_ctl_2[0]
12) instance work.decoder(verilog)-ext_ctl_2[2:0], output net "ext_ctl_2[0]" in work.decoder(verilog)
    input nets to instance:
        net "alu_func_0_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_1_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_2_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_3_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_4_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_5_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_6_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_7_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_8_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_9_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_10_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_11_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_12_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_13_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_14_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_15_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_16_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_17_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_18_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_19_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_20_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_21_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_22_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_23_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_24_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_25_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_26_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_27_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_28_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_0_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_we_1_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_we_2_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_3_sqmuxa" in work.decoder(verilog)
        net "ext_ctl_1[0]" in work.decoder(verilog)
        net "ext_ctl_1[1]" in work.decoder(verilog)
        net "ext_ctl_1[2]" in work.decoder(verilog)
        net "alu_we_4_sqmuxa" in work.decoder(verilog)
        net "ext_ctl_1[0]" in work.decoder(verilog)
        net "ext_ctl_1[1]" in work.decoder(verilog)
        net "ext_ctl_1[2]" in work.decoder(verilog)
        net "fsm_dly350" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly351" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly352" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly353" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly354" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly355" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly356" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly357" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly358" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly359" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly360" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly361" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly362" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly363" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
        net "ext_ctl_1[0]" in work.decoder(verilog)
        net "ext_ctl_1[1]" in work.decoder(verilog)
        net "ext_ctl_1[2]" in work.decoder(verilog)
        net "fsm_dly365" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly366" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly367" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly368" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly369" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly370" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net ext_ctl_2[1]
13) instance work.decoder(verilog)-ext_ctl_2[2:0], output net "ext_ctl_2[1]" in work.decoder(verilog)
    input nets to instance:
        net "alu_func_0_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_1_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_2_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_3_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_4_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_5_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_6_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_7_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_8_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_9_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_10_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_11_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_12_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_13_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_14_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_15_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_16_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_17_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_18_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_19_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_20_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_21_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_22_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_23_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_24_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_25_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_26_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_27_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_28_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_0_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_we_1_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_we_2_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_3_sqmuxa" in work.decoder(verilog)
        net "ext_ctl_1[0]" in work.decoder(verilog)
        net "ext_ctl_1[1]" in work.decoder(verilog)
        net "ext_ctl_1[2]" in work.decoder(verilog)
        net "alu_we_4_sqmuxa" in work.decoder(verilog)
        net "ext_ctl_1[0]" in work.decoder(verilog)
        net "ext_ctl_1[1]" in work.decoder(verilog)
        net "ext_ctl_1[2]" in work.decoder(verilog)
        net "fsm_dly350" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly351" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly352" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly353" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly354" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly355" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly356" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly357" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly358" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly359" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly360" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly361" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly362" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly363" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
        net "ext_ctl_1[0]" in work.decoder(verilog)
        net "ext_ctl_1[1]" in work.decoder(verilog)
        net "ext_ctl_1[2]" in work.decoder(verilog)
        net "fsm_dly365" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly366" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly367" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly368" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly369" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly370" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net ext_ctl_2[2]
14) instance work.decoder(verilog)-ext_ctl_2[2:0], output net "ext_ctl_2[2]" in work.decoder(verilog)
    input nets to instance:
        net "alu_func_0_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_1_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_2_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_3_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_4_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_5_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_6_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_7_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_8_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_9_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_10_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_11_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_12_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_13_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_14_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_15_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_16_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_17_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_18_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_19_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_20_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_21_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_22_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_23_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_24_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_25_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_26_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_27_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_28_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_0_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_we_1_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_we_2_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_3_sqmuxa" in work.decoder(verilog)
        net "ext_ctl_1[0]" in work.decoder(verilog)
        net "ext_ctl_1[1]" in work.decoder(verilog)
        net "ext_ctl_1[2]" in work.decoder(verilog)
        net "alu_we_4_sqmuxa" in work.decoder(verilog)
        net "ext_ctl_1[0]" in work.decoder(verilog)
        net "ext_ctl_1[1]" in work.decoder(verilog)
        net "ext_ctl_1[2]" in work.decoder(verilog)
        net "fsm_dly350" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly351" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly352" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly353" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly354" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly355" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly356" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly357" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly358" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly359" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly360" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly361" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly362" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly363" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
        net "ext_ctl_1[0]" in work.decoder(verilog)
        net "ext_ctl_1[1]" in work.decoder(verilog)
        net "ext_ctl_1[2]" in work.decoder(verilog)
        net "fsm_dly365" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly366" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly367" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly368" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly369" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly370" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net muxa_ctl_2[0]
15) instance work.decoder(verilog)-muxa_ctl_2[1:0], output net "muxa_ctl_2[0]" in work.decoder(verilog)
    input nets to instance:
        net "alu_func_0_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_1_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_2_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_3_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_4_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_5_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_6_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_7_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_8_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_9_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_10_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_11_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_12_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_13_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_14_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_15_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_16_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_17_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_18_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_19_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_20_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_21_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_22_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_23_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_24_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_25_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_26_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_27_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_28_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_0_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_1_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_2_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_3_sqmuxa" in work.decoder(verilog)
        net "muxa_ctl_1[0]" in work.decoder(verilog)
        net "muxa_ctl_1[1]" in work.decoder(verilog)
        net "alu_we_4_sqmuxa" in work.decoder(verilog)
        net "muxa_ctl_1[0]" in work.decoder(verilog)
        net "muxa_ctl_1[1]" in work.decoder(verilog)
        net "fsm_dly350" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly351" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly352" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly353" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly354" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly355" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly356" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly357" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly358" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly359" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly360" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly361" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly362" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly363" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
        net "muxa_ctl_1[0]" in work.decoder(verilog)
        net "muxa_ctl_1[1]" in work.decoder(verilog)
        net "fsm_dly365" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly366" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly367" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly368" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly369" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly370" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net muxa_ctl_2[1]
16) instance work.decoder(verilog)-muxa_ctl_2[1:0], output net "muxa_ctl_2[1]" in work.decoder(verilog)
    input nets to instance:
        net "alu_func_0_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_1_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_2_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_3_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_4_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_5_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_6_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_7_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_8_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_9_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_10_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_11_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_12_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_13_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_14_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_15_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_16_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_17_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_18_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_19_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_20_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_21_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_22_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_23_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_24_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_25_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_26_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_27_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_28_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_0_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_1_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_2_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_3_sqmuxa" in work.decoder(verilog)
        net "muxa_ctl_1[0]" in work.decoder(verilog)
        net "muxa_ctl_1[1]" in work.decoder(verilog)
        net "alu_we_4_sqmuxa" in work.decoder(verilog)
        net "muxa_ctl_1[0]" in work.decoder(verilog)
        net "muxa_ctl_1[1]" in work.decoder(verilog)
        net "fsm_dly350" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly351" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly352" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly353" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly354" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly355" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly356" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly357" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly358" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly359" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly360" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly361" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly362" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly363" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
        net "muxa_ctl_1[0]" in work.decoder(verilog)
        net "muxa_ctl_1[1]" in work.decoder(verilog)
        net "fsm_dly365" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly366" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly367" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly368" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly369" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly370" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net muxb_ctl_2[0]
17) instance work.decoder(verilog)-muxb_ctl_2[1:0], output net "muxb_ctl_2[0]" in work.decoder(verilog)
    input nets to instance:
        net "alu_func_0_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_1_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_2_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_3_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_4_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_5_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_6_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_7_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_8_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_9_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_10_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_11_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_12_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_13_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_14_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_15_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_16_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_17_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_18_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_19_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_20_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_21_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_22_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_23_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_24_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_25_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_26_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_27_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_28_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_0_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_1_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_2_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_3_sqmuxa" in work.decoder(verilog)
        net "muxb_ctl_1[0]" in work.decoder(verilog)
        net "muxb_ctl_1[1]" in work.decoder(verilog)
        net "alu_we_4_sqmuxa" in work.decoder(verilog)
        net "muxb_ctl_1[0]" in work.decoder(verilog)
        net "muxb_ctl_1[1]" in work.decoder(verilog)
        net "fsm_dly350" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly351" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly352" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly353" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly354" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly355" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly356" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly357" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly358" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly359" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly360" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly361" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly362" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly363" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
        net "muxb_ctl_1[0]" in work.decoder(verilog)
        net "muxb_ctl_1[1]" in work.decoder(verilog)
        net "fsm_dly365" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly366" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly367" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly368" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly369" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly370" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net muxb_ctl_2[1]
18) instance work.decoder(verilog)-muxb_ctl_2[1:0], output net "muxb_ctl_2[1]" in work.decoder(verilog)
    input nets to instance:
        net "alu_func_0_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_1_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_2_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_3_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_4_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_5_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_6_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_7_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_8_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_9_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_10_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_11_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_12_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_13_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_14_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_15_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_16_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_17_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_18_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_19_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_20_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_21_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_22_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_23_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_24_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_25_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_26_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_27_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_28_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_0_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_1_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_2_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_3_sqmuxa" in work.decoder(verilog)
        net "muxb_ctl_1[0]" in work.decoder(verilog)
        net "muxb_ctl_1[1]" in work.decoder(verilog)
        net "alu_we_4_sqmuxa" in work.decoder(verilog)
        net "muxb_ctl_1[0]" in work.decoder(verilog)
        net "muxb_ctl_1[1]" in work.decoder(verilog)
        net "fsm_dly350" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly351" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly352" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly353" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly354" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly355" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly356" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly357" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly358" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly359" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly360" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly361" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly362" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly363" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
        net "muxb_ctl_1[0]" in work.decoder(verilog)
        net "muxb_ctl_1[1]" in work.decoder(verilog)
        net "fsm_dly365" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly366" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly367" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly368" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly369" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly370" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net pc_gen_ctl_2[0]
19) instance work.decoder(verilog)-pc_gen_ctl_2[2:0], output net "pc_gen_ctl_2[0]" in work.decoder(verilog)
    input nets to instance:
        net "alu_func_0_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_1_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_2_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_3_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_4_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_5_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_6_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_7_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_8_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_9_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_10_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_11_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_12_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_13_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_14_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_15_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_16_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_17_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_18_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_19_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_20_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_21_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_22_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_23_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_24_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_25_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_26_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_27_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_28_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_0_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_we_1_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_we_2_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_3_sqmuxa" in work.decoder(verilog)
        net "pc_gen_ctl_1[0]" in work.decoder(verilog)
        net "pc_gen_ctl_1[1]" in work.decoder(verilog)
        net "pc_gen_ctl_1[2]" in work.decoder(verilog)
        net "alu_we_4_sqmuxa" in work.decoder(verilog)
        net "pc_gen_ctl_1[0]" in work.decoder(verilog)
        net "pc_gen_ctl_1[1]" in work.decoder(verilog)
        net "pc_gen_ctl_1[2]" in work.decoder(verilog)
        net "fsm_dly350" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly351" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly352" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly353" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly354" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly355" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly356" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly357" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly358" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly359" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly360" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly361" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly362" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly363" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
        net "pc_gen_ctl_1[0]" in work.decoder(verilog)
        net "pc_gen_ctl_1[1]" in work.decoder(verilog)
        net "pc_gen_ctl_1[2]" in work.decoder(verilog)
        net "fsm_dly365" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly366" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly367" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly368" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly369" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly370" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net pc_gen_ctl_2[1]
20) instance work.decoder(verilog)-pc_gen_ctl_2[2:0], output net "pc_gen_ctl_2[1]" in work.decoder(verilog)
    input nets to instance:
        net "alu_func_0_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_1_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_2_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_3_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_4_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_5_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_6_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_7_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_8_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_9_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_10_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_11_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_12_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_13_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_14_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_15_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_16_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_17_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_18_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_19_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_20_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_21_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_22_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_23_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_24_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_25_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_26_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_27_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_28_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_0_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_we_1_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_we_2_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_3_sqmuxa" in work.decoder(verilog)
        net "pc_gen_ctl_1[0]" in work.decoder(verilog)
        net "pc_gen_ctl_1[1]" in work.decoder(verilog)
        net "pc_gen_ctl_1[2]" in work.decoder(verilog)
        net "alu_we_4_sqmuxa" in work.decoder(verilog)
        net "pc_gen_ctl_1[0]" in work.decoder(verilog)
        net "pc_gen_ctl_1[1]" in work.decoder(verilog)
        net "pc_gen_ctl_1[2]" in work.decoder(verilog)
        net "fsm_dly350" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly351" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly352" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly353" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly354" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly355" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly356" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly357" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly358" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly359" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly360" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly361" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly362" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly363" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
        net "pc_gen_ctl_1[0]" in work.decoder(verilog)
        net "pc_gen_ctl_1[1]" in work.decoder(verilog)
        net "pc_gen_ctl_1[2]" in work.decoder(verilog)
        net "fsm_dly365" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly366" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly367" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly368" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly369" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly370" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net pc_gen_ctl_2[2]
21) instance work.decoder(verilog)-pc_gen_ctl_2[2:0], output net "pc_gen_ctl_2[2]" in work.decoder(verilog)
    input nets to instance:
        net "alu_func_0_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_1_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_2_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_3_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_4_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_5_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_6_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_7_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_8_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_9_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_10_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_11_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_12_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_13_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_14_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_15_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_16_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_17_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_18_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_19_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_20_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_21_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_22_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_23_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_24_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_25_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_26_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_27_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_28_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_0_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_we_1_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_we_2_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_3_sqmuxa" in work.decoder(verilog)
        net "pc_gen_ctl_1[0]" in work.decoder(verilog)
        net "pc_gen_ctl_1[1]" in work.decoder(verilog)
        net "pc_gen_ctl_1[2]" in work.decoder(verilog)
        net "alu_we_4_sqmuxa" in work.decoder(verilog)
        net "pc_gen_ctl_1[0]" in work.decoder(verilog)
        net "pc_gen_ctl_1[1]" in work.decoder(verilog)
        net "pc_gen_ctl_1[2]" in work.decoder(verilog)
        net "fsm_dly350" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly351" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly352" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly353" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly354" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly355" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly356" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly357" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly358" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly359" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly360" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly361" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly362" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly363" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
        net "pc_gen_ctl_1[0]" in work.decoder(verilog)
        net "pc_gen_ctl_1[1]" in work.decoder(verilog)
        net "pc_gen_ctl_1[2]" in work.decoder(verilog)
        net "fsm_dly365" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly366" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly367" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly368" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly369" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly370" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net rd_sel_2[0]
22) instance work.decoder(verilog)-rd_sel_2[1:0], output net "rd_sel_2[0]" in work.decoder(verilog)
    input nets to instance:
        net "alu_func_0_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_1_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_2_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_3_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_4_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_5_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_6_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_7_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_8_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_9_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_10_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_11_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_12_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_13_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_14_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_15_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_16_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_17_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_18_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_19_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_20_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_21_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_22_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_23_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_24_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_25_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_26_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_27_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_28_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_0_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_1_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_2_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_3_sqmuxa" in work.decoder(verilog)
        net "rd_sel_1[0]" in work.decoder(verilog)
        net "rd_sel_1[1]" in work.decoder(verilog)
        net "alu_we_4_sqmuxa" in work.decoder(verilog)
        net "rd_sel_1[0]" in work.decoder(verilog)
        net "rd_sel_1[1]" in work.decoder(verilog)
        net "fsm_dly350" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly351" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly352" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly353" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly354" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly355" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly356" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly357" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly358" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly359" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly360" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly361" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly362" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly363" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
        net "rd_sel_1[0]" in work.decoder(verilog)
        net "rd_sel_1[1]" in work.decoder(verilog)
        net "fsm_dly365" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly366" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly367" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly368" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly369" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly370" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net rd_sel_2[1]
23) instance work.decoder(verilog)-rd_sel_2[1:0], output net "rd_sel_2[1]" in work.decoder(verilog)
    input nets to instance:
        net "alu_func_0_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_1_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_2_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_3_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_4_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_5_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_6_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_7_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_8_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_9_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_10_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_11_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_12_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_13_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_14_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_15_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_16_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_17_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_18_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_19_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_20_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_21_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_22_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_23_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_24_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_25_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_26_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_27_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_28_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_0_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_1_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_2_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_3_sqmuxa" in work.decoder(verilog)
        net "rd_sel_1[0]" in work.decoder(verilog)
        net "rd_sel_1[1]" in work.decoder(verilog)
        net "alu_we_4_sqmuxa" in work.decoder(verilog)
        net "rd_sel_1[0]" in work.decoder(verilog)
        net "rd_sel_1[1]" in work.decoder(verilog)
        net "fsm_dly350" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly351" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly352" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly353" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly354" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly355" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly356" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly357" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly358" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly359" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly360" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly361" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly362" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly363" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
        net "rd_sel_1[0]" in work.decoder(verilog)
        net "rd_sel_1[1]" in work.decoder(verilog)
        net "fsm_dly365" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly366" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly367" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly368" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly369" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly370" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net cmp_ctl_2[0]
24) instance work.decoder(verilog)-cmp_ctl_2[2:0], output net "cmp_ctl_2[0]" in work.decoder(verilog)
    input nets to instance:
        net "un1_fsm_dly352_1" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_0_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_we_1_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "un1_alu_we_3_sqmuxa" in work.decoder(verilog)
        net "cmp_ctl_1[0]" in work.decoder(verilog)
        net "cmp_ctl_1[1]" in work.decoder(verilog)
        net "cmp_ctl_1[2]" in work.decoder(verilog)
        net "fsm_dly352" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly353" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly354" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly355" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net cmp_ctl_2[1]
25) instance work.decoder(verilog)-cmp_ctl_2[2:0], output net "cmp_ctl_2[1]" in work.decoder(verilog)
    input nets to instance:
        net "un1_fsm_dly352_1" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_0_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_we_1_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "un1_alu_we_3_sqmuxa" in work.decoder(verilog)
        net "cmp_ctl_1[0]" in work.decoder(verilog)
        net "cmp_ctl_1[1]" in work.decoder(verilog)
        net "cmp_ctl_1[2]" in work.decoder(verilog)
        net "fsm_dly352" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly353" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly354" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly355" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net cmp_ctl_2[2]
26) instance work.decoder(verilog)-cmp_ctl_2[2:0], output net "cmp_ctl_2[2]" in work.decoder(verilog)
    input nets to instance:
        net "un1_fsm_dly352_1" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_0_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_we_1_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "un1_alu_we_3_sqmuxa" in work.decoder(verilog)
        net "cmp_ctl_1[0]" in work.decoder(verilog)
        net "cmp_ctl_1[1]" in work.decoder(verilog)
        net "cmp_ctl_1[2]" in work.decoder(verilog)
        net "fsm_dly352" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly353" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly354" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly355" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net dmem_ctl_2[0]
27) instance work.decoder(verilog)-dmem_ctl_2[3:0], output net "dmem_ctl_2[0]" in work.decoder(verilog)
    input nets to instance:
        net "un1_fsm_dly365_2" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "un1_alu_we_3_sqmuxa" in work.decoder(verilog)
        net "dmem_ctl_1[0]" in work.decoder(verilog)
        net "dmem_ctl_1[1]" in work.decoder(verilog)
        net "dmem_ctl_1[2]" in work.decoder(verilog)
        net "dmem_ctl_1[3]" in work.decoder(verilog)
        net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly365" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly366" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly368" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly369" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly370" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net dmem_ctl_2[1]
28) instance work.decoder(verilog)-dmem_ctl_2[3:0], output net "dmem_ctl_2[1]" in work.decoder(verilog)
    input nets to instance:
        net "un1_fsm_dly365_2" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "un1_alu_we_3_sqmuxa" in work.decoder(verilog)
        net "dmem_ctl_1[0]" in work.decoder(verilog)
        net "dmem_ctl_1[1]" in work.decoder(verilog)
        net "dmem_ctl_1[2]" in work.decoder(verilog)
        net "dmem_ctl_1[3]" in work.decoder(verilog)
        net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly365" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly366" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly368" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly369" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly370" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net dmem_ctl_2[2]
29) instance work.decoder(verilog)-dmem_ctl_2[3:0], output net "dmem_ctl_2[2]" in work.decoder(verilog)
    input nets to instance:
        net "un1_fsm_dly365_2" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "un1_alu_we_3_sqmuxa" in work.decoder(verilog)
        net "dmem_ctl_1[0]" in work.decoder(verilog)
        net "dmem_ctl_1[1]" in work.decoder(verilog)
        net "dmem_ctl_1[2]" in work.decoder(verilog)
        net "dmem_ctl_1[3]" in work.decoder(verilog)
        net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly365" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly366" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly368" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly369" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly370" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net dmem_ctl_2[3]
30) instance work.decoder(verilog)-dmem_ctl_2[3:0], output net "dmem_ctl_2[3]" in work.decoder(verilog)
    input nets to instance:
        net "un1_fsm_dly365_2" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "un1_alu_we_3_sqmuxa" in work.decoder(verilog)
        net "dmem_ctl_1[0]" in work.decoder(verilog)
        net "dmem_ctl_1[1]" in work.decoder(verilog)
        net "dmem_ctl_1[2]" in work.decoder(verilog)
        net "dmem_ctl_1[3]" in work.decoder(verilog)
        net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly365" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly366" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly368" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly369" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly370" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
End of loops
@W: BN132 :"e:\mips789\mips789\rtl\verilog\ulit.v":150:83:150:88|Removing sequential instance mips_core.alu_pass0.r32_o[0],  because it is equivalent to instance mips_core.MEM_CTL.dmem_ctl_post.byte_addr_o[0]
@W: BN132 :"e:\mips789\mips789\rtl\verilog\ulit.v":150:83:150:88|Removing sequential instance mips_core.alu_pass0.r32_o[1],  because it is equivalent to instance mips_core.MEM_CTL.dmem_ctl_post.byte_addr_o[1]
@N:"e:\mips789\mips789\rtl\verilog\exec_stage.v":572:4:572:9|Found counter in view:work.muldiv_ff(verilog) inst count[5:0]
Warning: Found 30 combinational loops!
         Each loop is reported with an instance in the loop
         and nets connected to that instance.
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
1) instance fsm_dly_2[2:0] work.decoder(verilog)-fsm_dly_2[2:0], output net "fsm_dly_2[0]" in work.decoder(verilog)
    input nets to instance:
        net "alu_func_0_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_1_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_2_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_3_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_4_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_5_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_6_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_7_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_8_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_9_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_10_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_11_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_12_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_13_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_14_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_15_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_16_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_17_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_18_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_19_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_20_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_21_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_22_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_23_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_24_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_25_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_26_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_27_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_28_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_0_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_1_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_2_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_3_sqmuxa" in work.decoder(verilog)
        net "fsm_dly_1[0]" in work.decoder(verilog)
        net "fsm_dly_1[1]" in work.decoder(verilog)
        net "fsm_dly_1[2]" in work.decoder(verilog)
        net "alu_we_4_sqmuxa" in work.decoder(verilog)
        net "fsm_dly_1[0]" in work.decoder(verilog)
        net "fsm_dly_1[1]" in work.decoder(verilog)
        net "fsm_dly_1[2]" in work.decoder(verilog)
        net "fsm_dly350" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly351" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly352" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly353" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly354" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly355" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly356" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly357" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly358" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly359" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly360" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly361" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly362" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly363" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
        net "fsm_dly_1[0]" in work.decoder(verilog)
        net "fsm_dly_1[1]" in work.decoder(verilog)
        net "fsm_dly_1[2]" in work.decoder(verilog)
        net "fsm_dly365" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly366" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly367" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly368" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly369" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly370" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
2) instance fsm_dly_2[2:0] work.decoder(verilog)-fsm_dly_2[2:0], output net "fsm_dly_2[1]" in work.decoder(verilog)
    input nets to instance:
        net "alu_func_0_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_1_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_2_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_3_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_4_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_5_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_6_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_7_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_8_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_9_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_10_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_11_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_12_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_13_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_14_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_15_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_16_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_17_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_18_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_19_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_20_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_21_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_22_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_23_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_24_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_25_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_26_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_27_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_28_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_0_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_1_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_2_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_3_sqmuxa" in work.decoder(verilog)
        net "fsm_dly_1[0]" in work.decoder(verilog)
        net "fsm_dly_1[1]" in work.decoder(verilog)
        net "fsm_dly_1[2]" in work.decoder(verilog)
        net "alu_we_4_sqmuxa" in work.decoder(verilog)
        net "fsm_dly_1[0]" in work.decoder(verilog)
        net "fsm_dly_1[1]" in work.decoder(verilog)
        net "fsm_dly_1[2]" in work.decoder(verilog)
        net "fsm_dly350" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly351" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly352" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly353" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly354" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly355" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly356" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly357" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly358" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly359" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly360" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly361" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly362" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly363" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
        net "fsm_dly_1[0]" in work.decoder(verilog)
        net "fsm_dly_1[1]" in work.decoder(verilog)
        net "fsm_dly_1[2]" in work.decoder(verilog)
        net "fsm_dly365" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly366" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly367" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly368" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly369" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly370" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
3) instance fsm_dly_2[2:0] work.decoder(verilog)-fsm_dly_2[2:0], output net "fsm_dly_2[2]" in work.decoder(verilog)
    input nets to instance:
        net "alu_func_0_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_1_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_2_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_3_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_4_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_5_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_6_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_7_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_8_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_9_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_10_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_11_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_12_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_13_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_14_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_15_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_16_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_17_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_18_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_19_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_20_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_21_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_22_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_23_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_24_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_25_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_26_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_27_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_28_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_0_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_1_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_2_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_3_sqmuxa" in work.decoder(verilog)
        net "fsm_dly_1[0]" in work.decoder(verilog)
        net "fsm_dly_1[1]" in work.decoder(verilog)
        net "fsm_dly_1[2]" in work.decoder(verilog)
        net "alu_we_4_sqmuxa" in work.decoder(verilog)
        net "fsm_dly_1[0]" in work.decoder(verilog)
        net "fsm_dly_1[1]" in work.decoder(verilog)
        net "fsm_dly_1[2]" in work.decoder(verilog)
        net "fsm_dly350" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly351" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly352" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly353" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly354" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly355" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly356" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly357" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly358" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly359" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly360" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly361" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly362" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly363" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
        net "fsm_dly_1[0]" in work.decoder(verilog)
        net "fsm_dly_1[1]" in work.decoder(verilog)
        net "fsm_dly_1[2]" in work.decoder(verilog)
        net "fsm_dly365" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly366" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly367" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly368" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly369" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly370" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
4) instance ext_ctl_1[0] work.decoder(verilog)-ext_ctl_1[0], output net "ext_ctl_1[0]" in work.decoder(verilog)
    input nets to instance:
        net "ext_ctl_2[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_23" in work.decoder(verilog)
        net "un1_ins_i_20" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
5) instance ext_ctl_1[1] work.decoder(verilog)-ext_ctl_1[1], output net "ext_ctl_1[1]" in work.decoder(verilog)
    input nets to instance:
        net "ext_ctl_2[1]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
6) instance ext_ctl_1[2] work.decoder(verilog)-ext_ctl_1[2], output net "ext_ctl_1[2]" in work.decoder(verilog)
    input nets to instance:
        net "ext_ctl_2[2]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
7) instance rd_sel_1[0] work.decoder(verilog)-rd_sel_1[0], output net "rd_sel_1[0]" in work.decoder(verilog)
    input nets to instance:
        net "rd_sel_2[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
8) instance rd_sel_1[1] work.decoder(verilog)-rd_sel_1[1], output net "rd_sel_1[1]" in work.decoder(verilog)
    input nets to instance:
        net "rd_sel_2[1]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_22" in work.decoder(verilog)
        net "fsm_dly373" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
9) instance cmp_ctl_1[0] work.decoder(verilog)-cmp_ctl_1[0], output net "cmp_ctl_1[0]" in work.decoder(verilog)
    input nets to instance:
        net "cmp_ctl_2[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
10) instance cmp_ctl_1[1] work.decoder(verilog)-cmp_ctl_1[1], output net "cmp_ctl_1[1]" in work.decoder(verilog)
    input nets to instance:
        net "cmp_ctl_2[1]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
11) instance cmp_ctl_1[2] work.decoder(verilog)-cmp_ctl_1[2], output net "cmp_ctl_1[2]" in work.decoder(verilog)
    input nets to instance:
        net "cmp_ctl_2[2]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
12) instance pc_gen_ctl_1[0] work.decoder(verilog)-pc_gen_ctl_1[0], output net "pc_gen_ctl_1[0]" in work.decoder(verilog)
    input nets to instance:
        net "pc_gen_ctl_2[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_23" in work.decoder(verilog)
        net "un1_ins_i_20" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
13) instance pc_gen_ctl_1[1] work.decoder(verilog)-pc_gen_ctl_1[1], output net "pc_gen_ctl_1[1]" in work.decoder(verilog)
    input nets to instance:
        net "pc_gen_ctl_2[1]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
14) instance pc_gen_ctl_1[2] work.decoder(verilog)-pc_gen_ctl_1[2], output net "pc_gen_ctl_1[2]" in work.decoder(verilog)
    input nets to instance:
        net "pc_gen_ctl_2[2]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_23" in work.decoder(verilog)
        net "un1_ins_i_20" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
15) instance muxa_ctl_1[0] work.decoder(verilog)-muxa_ctl_1[0], output net "muxa_ctl_1[0]" in work.decoder(verilog)
    input nets to instance:
        net "muxa_ctl_2[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
16) instance muxa_ctl_1[1] work.decoder(verilog)-muxa_ctl_1[1], output net "muxa_ctl_1[1]" in work.decoder(verilog)
    input nets to instance:
        net "muxa_ctl_2[1]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_23" in work.decoder(verilog)
        net "un1_ins_i_20" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
17) instance muxb_ctl_1[0] work.decoder(verilog)-muxb_ctl_1[0], output net "muxb_ctl_1[0]" in work.decoder(verilog)
    input nets to instance:
        net "muxb_ctl_2[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
18) instance muxb_ctl_1[1] work.decoder(verilog)-muxb_ctl_1[1], output net "muxb_ctl_1[1]" in work.decoder(verilog)
    input nets to instance:
        net "muxb_ctl_2[1]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_23" in work.decoder(verilog)
        net "un1_ins_i_20" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
19) instance alu_func_1[0] work.decoder(verilog)-alu_func_1[0], output net "alu_func_1[0]" in work.decoder(verilog)
    input nets to instance:
        net "alu_func_2[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
20) instance alu_func_1[1] work.decoder(verilog)-alu_func_1[1], output net "alu_func_1[1]" in work.decoder(verilog)
    input nets to instance:
        net "alu_func_2[1]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
21) instance alu_func_1[2] work.decoder(verilog)-alu_func_1[2], output net "alu_func_1[2]" in work.decoder(verilog)
    input nets to instance:
        net "alu_func_2[2]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_23" in work.decoder(verilog)
        net "un1_ins_i_20" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
22) instance alu_func_1[3] work.decoder(verilog)-alu_func_1[3], output net "alu_func_1[3]" in work.decoder(verilog)
    input nets to instance:
        net "alu_func_2[3]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_23" in work.decoder(verilog)
        net "un1_ins_i_20" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
23) instance alu_func_1[4] work.decoder(verilog)-alu_func_1[4], output net "alu_func_1[4]" in work.decoder(verilog)
    input nets to instance:
        net "alu_func_2[4]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
24) instance dmem_ctl_1[0] work.decoder(verilog)-dmem_ctl_1[0], output net "dmem_ctl_1[0]" in work.decoder(verilog)
    input nets to instance:
        net "dmem_ctl_2[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_23" in work.decoder(verilog)
        net "un1_ins_i_20" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
25) instance dmem_ctl_1[1] work.decoder(verilog)-dmem_ctl_1[1], output net "dmem_ctl_1[1]" in work.decoder(verilog)
    input nets to instance:
        net "dmem_ctl_2[1]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_22" in work.decoder(verilog)
        net "fsm_dly373" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
26) instance dmem_ctl_1[2] work.decoder(verilog)-dmem_ctl_1[2], output net "dmem_ctl_1[2]" in work.decoder(verilog)
    input nets to instance:
        net "dmem_ctl_2[2]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_24" in work.decoder(verilog)
        net "un1_ins_i_15" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
27) instance dmem_ctl_1[3] work.decoder(verilog)-dmem_ctl_1[3], output net "dmem_ctl_1[3]" in work.decoder(verilog)
    input nets to instance:
        net "dmem_ctl_2[3]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
28) instance alu_we[0] work.decoder(verilog)-alu_we[0], output net "alu_we[0]" in work.decoder(verilog)
    input nets to instance:
        net "alu_we_1[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
29) instance wb_mux[0] work.decoder(verilog)-wb_mux[0], output net "wb_mux[0]" in work.decoder(verilog)
    input nets to instance:
        net "wb_mux_1[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
30) instance wb_we[0] work.decoder(verilog)-wb_we[0], output net "wb_we[0]" in work.decoder(verilog)
    input nets to instance:
        net "wb_we_1[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
End of loops
Warning: Found 28 combinational loops!
         Each loop is reported with an instance in the loop
         and nets connected to that instance.
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
1) instance fsm_dly_2[2:0] work.decoder(verilog)-fsm_dly_2[2:0], output net "fsm_dly_2[0]" in work.decoder(verilog)
    input nets to instance:
        net "alu_func_0_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_1_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_2_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_3_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_4_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_5_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_6_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_7_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_8_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_9_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_10_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_11_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_12_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_13_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_14_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_15_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_16_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_17_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_18_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_19_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_20_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_21_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_22_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_23_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_24_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_25_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_26_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_27_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_28_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_0_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_1_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_2_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_3_sqmuxa" in work.decoder(verilog)
        net "fsm_dly_1[0]" in work.decoder(verilog)
        net "fsm_dly_1[1]" in work.decoder(verilog)
        net "fsm_dly_1[2]" in work.decoder(verilog)
        net "alu_we_4_sqmuxa" in work.decoder(verilog)
        net "fsm_dly_1[0]" in work.decoder(verilog)
        net "fsm_dly_1[1]" in work.decoder(verilog)
        net "fsm_dly_1[2]" in work.decoder(verilog)
        net "fsm_dly350" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly351" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly352" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly353" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly354" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly355" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly356" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly357" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly358" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly359" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly360" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly361" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly362" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly363" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
        net "fsm_dly_1[0]" in work.decoder(verilog)
        net "fsm_dly_1[1]" in work.decoder(verilog)
        net "fsm_dly_1[2]" in work.decoder(verilog)
        net "fsm_dly365" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly366" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly367" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly368" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly369" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly370" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
2) instance ext_ctl_1[0] work.decoder(verilog)-ext_ctl_1[0], output net "ext_ctl_1[0]" in work.decoder(verilog)
    input nets to instance:
        net "ext_ctl_2[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_23" in work.decoder(verilog)
        net "un1_ins_i_20" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
3) instance ext_ctl_1[1] work.decoder(verilog)-ext_ctl_1[1], output net "ext_ctl_1[1]" in work.decoder(verilog)
    input nets to instance:
        net "ext_ctl_2[1]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
4) instance ext_ctl_1[2] work.decoder(verilog)-ext_ctl_1[2], output net "ext_ctl_1[2]" in work.decoder(verilog)
    input nets to instance:
        net "ext_ctl_2[2]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
5) instance rd_sel_1[0] work.decoder(verilog)-rd_sel_1[0], output net "rd_sel_1[0]" in work.decoder(verilog)
    input nets to instance:
        net "rd_sel_2[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
6) instance rd_sel_1[1] work.decoder(verilog)-rd_sel_1[1], output net "rd_sel_1[1]" in work.decoder(verilog)
    input nets to instance:
        net "rd_sel_2[1]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_22" in work.decoder(verilog)
        net "fsm_dly373" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
7) instance cmp_ctl_1[0] work.decoder(verilog)-cmp_ctl_1[0], output net "cmp_ctl_1[0]" in work.decoder(verilog)
    input nets to instance:
        net "cmp_ctl_2[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
8) instance cmp_ctl_1[1] work.decoder(verilog)-cmp_ctl_1[1], output net "cmp_ctl_1[1]" in work.decoder(verilog)
    input nets to instance:
        net "cmp_ctl_2[1]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
9) instance cmp_ctl_1[2] work.decoder(verilog)-cmp_ctl_1[2], output net "cmp_ctl_1[2]" in work.decoder(verilog)
    input nets to instance:
        net "cmp_ctl_2[2]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
10) instance pc_gen_ctl_1[0] work.decoder(verilog)-pc_gen_ctl_1[0], output net "pc_gen_ctl_1[0]" in work.decoder(verilog)
    input nets to instance:
        net "pc_gen_ctl_2[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_23" in work.decoder(verilog)
        net "un1_ins_i_20" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
11) instance pc_gen_ctl_1[1] work.decoder(verilog)-pc_gen_ctl_1[1], output net "pc_gen_ctl_1[1]" in work.decoder(verilog)
    input nets to instance:
        net "pc_gen_ctl_2[1]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
12) instance pc_gen_ctl_1[2] work.decoder(verilog)-pc_gen_ctl_1[2], output net "pc_gen_ctl_1[2]" in work.decoder(verilog)
    input nets to instance:
        net "pc_gen_ctl_2[2]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_23" in work.decoder(verilog)
        net "un1_ins_i_20" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
13) instance muxa_ctl_1[0] work.decoder(verilog)-muxa_ctl_1[0], output net "muxa_ctl_1[0]" in work.decoder(verilog)
    input nets to instance:
        net "muxa_ctl_2[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
14) instance muxa_ctl_1[1] work.decoder(verilog)-muxa_ctl_1[1], output net "muxa_ctl_1[1]" in work.decoder(verilog)
    input nets to instance:
        net "muxa_ctl_2[1]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_23" in work.decoder(verilog)
        net "un1_ins_i_20" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
15) instance muxb_ctl_1[0] work.decoder(verilog)-muxb_ctl_1[0], output net "muxb_ctl_1[0]" in work.decoder(verilog)
    input nets to instance:
        net "muxb_ctl_2[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
16) instance muxb_ctl_1[1] work.decoder(verilog)-muxb_ctl_1[1], output net "muxb_ctl_1[1]" in work.decoder(verilog)
    input nets to instance:
        net "muxb_ctl_2[1]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_23" in work.decoder(verilog)
        net "un1_ins_i_20" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
17) instance alu_func_1[0] work.decoder(verilog)-alu_func_1[0], output net "alu_func_1[0]" in work.decoder(verilog)
    input nets to instance:
        net "alu_func_2[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
18) instance alu_func_1[1] work.decoder(verilog)-alu_func_1[1], output net "alu_func_1[1]" in work.decoder(verilog)
    input nets to instance:
        net "alu_func_2[1]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
19) instance alu_func_1[2] work.decoder(verilog)-alu_func_1[2], output net "alu_func_1[2]" in work.decoder(verilog)
    input nets to instance:
        net "alu_func_2[2]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_23" in work.decoder(verilog)
        net "un1_ins_i_20" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
20) instance alu_func_1[3] work.decoder(verilog)-alu_func_1[3], output net "alu_func_1[3]" in work.decoder(verilog)
    input nets to instance:
        net "alu_func_2[3]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_23" in work.decoder(verilog)
        net "un1_ins_i_20" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
21) instance alu_func_1[4] work.decoder(verilog)-alu_func_1[4], output net "alu_func_1[4]" in work.decoder(verilog)
    input nets to instance:
        net "alu_func_2[4]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
22) instance dmem_ctl_1[0] work.decoder(verilog)-dmem_ctl_1[0], output net "dmem_ctl_1[0]" in work.decoder(verilog)
    input nets to instance:
        net "dmem_ctl_2[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_23" in work.decoder(verilog)
        net "un1_ins_i_20" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
23) instance dmem_ctl_1[1] work.decoder(verilog)-dmem_ctl_1[1], output net "dmem_ctl_1[1]" in work.decoder(verilog)
    input nets to instance:
        net "dmem_ctl_2[1]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_22" in work.decoder(verilog)
        net "fsm_dly373" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
24) instance dmem_ctl_1[2] work.decoder(verilog)-dmem_ctl_1[2], output net "dmem_ctl_1[2]" in work.decoder(verilog)
    input nets to instance:
        net "dmem_ctl_2[2]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_24" in work.decoder(verilog)
        net "un1_ins_i_15" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
25) instance dmem_ctl_1[3] work.decoder(verilog)-dmem_ctl_1[3], output net "dmem_ctl_1[3]" in work.decoder(verilog)
    input nets to instance:
        net "dmem_ctl_2[3]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
26) instance alu_we[0] work.decoder(verilog)-alu_we[0], output net "alu_we[0]" in work.decoder(verilog)
    input nets to instance:
        net "alu_we_1[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
27) instance wb_mux[0] work.decoder(verilog)-wb_mux[0], output net "wb_mux[0]" in work.decoder(verilog)
    input nets to instance:
        net "wb_mux_1[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
28) instance wb_we[0] work.decoder(verilog)-wb_we[0], output net "wb_we[0]" in work.decoder(verilog)
    input nets to instance:
        net "wb_we_1[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
End of loops
@N:"e:\mips789\mips789\rtl\verilog\mips_uart.v":243:4:243:9|Found counter in view:work.uart_read(verilog) inst clk_ctr[15:0]
@N:"e:\mips789\mips789\rtl\verilog\mips_uart.v":256:4:256:9|Found counter in view:work.uart_read(verilog) inst bit_ctr[2:0]
@N:"e:\mips789\mips789\rtl\verilog\mips_uart.v":138:4:138:9|Found counter in view:work.uart_write(verilog) inst clk_ctr[15:0]
@N:"e:\mips789\mips789\rtl\verilog\mips_uart.v":151:4:151:9|Found counter in view:work.uart_write(verilog) inst bit_ctr[2:0]
@N: MO106 :"e:\mips789\mips789\rtl\verilog\dvc.v":67:12:67:15|Found ROM, 'seg_20[6:0]', 16 words by 7 bits 
@N: MO106 :"e:\mips789\mips789\rtl\verilog\dvc.v":67:12:67:15|Found ROM, 'seg[6:0]', 16 words by 7 bits 
@N:"e:\mips789\mips789\rtl\verilog\dvc.v":23:4:23:9|Found counter in view:work.tmr0(verilog) inst cntr[31:0]
Warning: Found 28 combinational loops!
         Each loop is reported with an instance in the loop
         and nets connected to that instance.
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
1) instance fsm_dly_2[0] work.decoder(verilog)-fsm_dly_2[0], output net "fsm_dly_2[0]" in work.decoder(verilog)
    input nets to instance:
        net "N_172" in work.decoder(verilog)
        net "fsm_dly_1[0]" in work.decoder(verilog)
        net "N_415" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
2) instance ext_ctl_1[0] work.decoder(verilog)-ext_ctl_1[0], output net "ext_ctl_1[0]" in work.decoder(verilog)
    input nets to instance:
        net "ext_ctl_2[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_23" in work.decoder(verilog)
        net "un1_ins_i_20" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
3) instance ext_ctl_1[1] work.decoder(verilog)-ext_ctl_1[1], output net "ext_ctl_1[1]" in work.decoder(verilog)
    input nets to instance:
        net "ext_ctl_2[1]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "N_436" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
4) instance ext_ctl_1[2] work.decoder(verilog)-ext_ctl_1[2], output net "ext_ctl_1[2]" in work.decoder(verilog)
    input nets to instance:
        net "ext_ctl_2[2]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "N_436" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
5) instance rd_sel_1[0] work.decoder(verilog)-rd_sel_1[0], output net "rd_sel_1[0]" in work.decoder(verilog)
    input nets to instance:
        net "rd_sel_2[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "N_436" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
6) instance rd_sel_1[1] work.decoder(verilog)-rd_sel_1[1], output net "rd_sel_1[1]" in work.decoder(verilog)
    input nets to instance:
        net "rd_sel_2[1]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "N_438" in work.decoder(verilog)
        net "fsm_dly373" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
7) instance cmp_ctl_1[0] work.decoder(verilog)-cmp_ctl_1[0], output net "cmp_ctl_1[0]" in work.decoder(verilog)
    input nets to instance:
        net "cmp_ctl_2[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "N_436" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
8) instance cmp_ctl_1[1] work.decoder(verilog)-cmp_ctl_1[1], output net "cmp_ctl_1[1]" in work.decoder(verilog)
    input nets to instance:
        net "cmp_ctl_2[1]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "N_436" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
9) instance cmp_ctl_1[2] work.decoder(verilog)-cmp_ctl_1[2], output net "cmp_ctl_1[2]" in work.decoder(verilog)
    input nets to instance:
        net "cmp_ctl_2[2]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "N_436" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
10) instance pc_gen_ctl_1[0] work.decoder(verilog)-pc_gen_ctl_1[0], output net "pc_gen_ctl_1[0]" in work.decoder(verilog)
    input nets to instance:
        net "pc_gen_ctl_2[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_23" in work.decoder(verilog)
        net "un1_ins_i_20" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
11) instance pc_gen_ctl_1[1] work.decoder(verilog)-pc_gen_ctl_1[1], output net "pc_gen_ctl_1[1]" in work.decoder(verilog)
    input nets to instance:
        net "pc_gen_ctl_2[1]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "N_436" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
12) instance pc_gen_ctl_1[2] work.decoder(verilog)-pc_gen_ctl_1[2], output net "pc_gen_ctl_1[2]" in work.decoder(verilog)
    input nets to instance:
        net "pc_gen_ctl_2[2]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_23" in work.decoder(verilog)
        net "un1_ins_i_20" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
13) instance muxa_ctl_1[0] work.decoder(verilog)-muxa_ctl_1[0], output net "muxa_ctl_1[0]" in work.decoder(verilog)
    input nets to instance:
        net "muxa_ctl_2[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "N_436" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
14) instance muxa_ctl_1[1] work.decoder(verilog)-muxa_ctl_1[1], output net "muxa_ctl_1[1]" in work.decoder(verilog)
    input nets to instance:
        net "muxa_ctl_2[1]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_23" in work.decoder(verilog)
        net "un1_ins_i_20" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
15) instance muxb_ctl_1[0] work.decoder(verilog)-muxb_ctl_1[0], output net "muxb_ctl_1[0]" in work.decoder(verilog)
    input nets to instance:
        net "muxb_ctl_2[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "N_436" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
16) instance muxb_ctl_1[1] work.decoder(verilog)-muxb_ctl_1[1], output net "muxb_ctl_1[1]" in work.decoder(verilog)
    input nets to instance:
        net "muxb_ctl_2[1]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_23" in work.decoder(verilog)
        net "un1_ins_i_20" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
17) instance alu_func_1[0] work.decoder(verilog)-alu_func_1[0], output net "alu_func_1[0]" in work.decoder(verilog)
    input nets to instance:
        net "alu_func_2[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "N_436" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
18) instance alu_func_1[1] work.decoder(verilog)-alu_func_1[1], output net "alu_func_1[1]" in work.decoder(verilog)
    input nets to instance:
        net "alu_func_2[1]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "N_436" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
19) instance alu_func_1[2] work.decoder(verilog)-alu_func_1[2], output net "alu_func_1[2]" in work.decoder(verilog)
    input nets to instance:
        net "alu_func_2[2]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_23" in work.decoder(verilog)
        net "un1_ins_i_20" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
20) instance alu_func_1[3] work.decoder(verilog)-alu_func_1[3], output net "alu_func_1[3]" in work.decoder(verilog)
    input nets to instance:
        net "alu_func_2[3]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_23" in work.decoder(verilog)
        net "un1_ins_i_20" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
21) instance alu_func_1[4] work.decoder(verilog)-alu_func_1[4], output net "alu_func_1[4]" in work.decoder(verilog)
    input nets to instance:
        net "alu_func_2[4]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "N_436" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
22) instance dmem_ctl_1[0] work.decoder(verilog)-dmem_ctl_1[0], output net "dmem_ctl_1[0]" in work.decoder(verilog)
    input nets to instance:
        net "dmem_ctl_2[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_23" in work.decoder(verilog)
        net "un1_ins_i_20" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
23) instance dmem_ctl_1[1] work.decoder(verilog)-dmem_ctl_1[1], output net "dmem_ctl_1[1]" in work.decoder(verilog)
    input nets to instance:
        net "dmem_ctl_2[1]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "N_438" in work.decoder(verilog)
        net "fsm_dly373" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
24) instance dmem_ctl_1[2] work.decoder(verilog)-dmem_ctl_1[2], output net "dmem_ctl_1[2]" in work.decoder(verilog)
    input nets to instance:
        net "dmem_ctl_2[2]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_24" in work.decoder(verilog)
        net "un1_ins_i_15" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
25) instance dmem_ctl_1[3] work.decoder(verilog)-dmem_ctl_1[3], output net "dmem_ctl_1[3]" in work.decoder(verilog)
    input nets to instance:
        net "dmem_ctl_2[3]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "N_436" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
26) instance alu_we[0] work.decoder(verilog)-alu_we[0], output net "alu_we[0]" in work.decoder(verilog)
    input nets to instance:
        net "alu_we_1[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "N_436" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
27) instance wb_mux[0] work.decoder(verilog)-wb_mux[0], output net "wb_mux[0]" in work.decoder(verilog)
    input nets to instance:
        net "wb_mux_1[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "N_436" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
28) instance wb_we[0] work.decoder(verilog)-wb_we[0], output net "wb_we[0]" in work.decoder(verilog)
    input nets to instance:
        net "wb_we_1[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "N_436" in work.decoder(verilog)
End of loops
Warning: Found 28 combinational loops!
         Each loop is reported with an instance in the loop
         and nets connected to that instance.
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
1) instance fsm_dly_2[0] work.decoder(verilog)-fsm_dly_2[0], output net "fsm_dly_2[0]" in work.decoder(verilog)
    input nets to instance:
        net "N_172" in work.decoder(verilog)
        net "fsm_dly_1[0]" in work.decoder(verilog)
        net "N_415" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
2) instance ext_ctl_1[0] work.decoder(verilog)-ext_ctl_1[0], output net "ext_ctl_1[0]" in work.decoder(verilog)
    input nets to instance:
        net "ext_ctl_2[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_23" in work.decoder(verilog)
        net "un1_ins_i_20" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
3) instance ext_ctl_1[1] work.decoder(verilog)-ext_ctl_1[1], output net "ext_ctl_1[1]" in work.decoder(verilog)
    input nets to instance:
        net "ext_ctl_2[1]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "N_436" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
4) instance ext_ctl_1[2] work.decoder(verilog)-ext_ctl_1[2], output net "ext_ctl_1[2]" in work.decoder(verilog)
    input nets to instance:
        net "ext_ctl_2[2]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "N_436" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
5) instance rd_sel_1[0] work.decoder(verilog)-rd_sel_1[0], output net "rd_sel_1[0]" in work.decoder(verilog)
    input nets to instance:
        net "rd_sel_2[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "N_436" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
6) instance rd_sel_1[1] work.decoder(verilog)-rd_sel_1[1], output net "rd_sel_1[1]" in work.decoder(verilog)
    input nets to instance:
        net "rd_sel_2[1]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "N_438" in work.decoder(verilog)
        net "fsm_dly373" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
7) instance cmp_ctl_1[0] work.decoder(verilog)-cmp_ctl_1[0], output net "cmp_ctl_1[0]" in work.decoder(verilog)
    input nets to instance:
        net "cmp_ctl_2[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "N_436" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
8) instance cmp_ctl_1[1] work.decoder(verilog)-cmp_ctl_1[1], output net "cmp_ctl_1[1]" in work.decoder(verilog)
    input nets to instance:
        net "cmp_ctl_2[1]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "N_436" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
9) instance cmp_ctl_1[2] work.decoder(verilog)-cmp_ctl_1[2], output net "cmp_ctl_1[2]" in work.decoder(verilog)
    input nets to instance:
        net "cmp_ctl_2[2]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "N_436" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
10) instance pc_gen_ctl_1[0] work.decoder(verilog)-pc_gen_ctl_1[0], output net "pc_gen_ctl_1[0]" in work.decoder(verilog)
    input nets to instance:
        net "pc_gen_ctl_2[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_23" in work.decoder(verilog)
        net "un1_ins_i_20" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
11) instance pc_gen_ctl_1[1] work.decoder(verilog)-pc_gen_ctl_1[1], output net "pc_gen_ctl_1[1]" in work.decoder(verilog)
    input nets to instance:
        net "pc_gen_ctl_2[1]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "N_436" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
12) instance pc_gen_ctl_1[2] work.decoder(verilog)-pc_gen_ctl_1[2], output net "pc_gen_ctl_1[2]" in work.decoder(verilog)
    input nets to instance:
        net "pc_gen_ctl_2[2]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_23" in work.decoder(verilog)
        net "un1_ins_i_20" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
13) instance muxa_ctl_1[0] work.decoder(verilog)-muxa_ctl_1[0], output net "muxa_ctl_1[0]" in work.decoder(verilog)
    input nets to instance:
        net "muxa_ctl_2[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "N_436" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
14) instance muxa_ctl_1[1] work.decoder(verilog)-muxa_ctl_1[1], output net "muxa_ctl_1[1]" in work.decoder(verilog)
    input nets to instance:
        net "muxa_ctl_2[1]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_23" in work.decoder(verilog)
        net "un1_ins_i_20" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
15) instance muxb_ctl_1[0] work.decoder(verilog)-muxb_ctl_1[0], output net "muxb_ctl_1[0]" in work.decoder(verilog)
    input nets to instance:
        net "muxb_ctl_2[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "N_436" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
16) instance muxb_ctl_1[1] work.decoder(verilog)-muxb_ctl_1[1], output net "muxb_ctl_1[1]" in work.decoder(verilog)
    input nets to instance:
        net "muxb_ctl_2[1]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_23" in work.decoder(verilog)
        net "un1_ins_i_20" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
17) instance alu_func_1[0] work.decoder(verilog)-alu_func_1[0], output net "alu_func_1[0]" in work.decoder(verilog)
    input nets to instance:
        net "alu_func_2[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "N_436" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
18) instance alu_func_1[1] work.decoder(verilog)-alu_func_1[1], output net "alu_func_1[1]" in work.decoder(verilog)
    input nets to instance:
        net "alu_func_2[1]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "N_436" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
19) instance alu_func_1[2] work.decoder(verilog)-alu_func_1[2], output net "alu_func_1[2]" in work.decoder(verilog)
    input nets to instance:
        net "alu_func_2[2]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_23" in work.decoder(verilog)
        net "un1_ins_i_20" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
20) instance alu_func_1[3] work.decoder(verilog)-alu_func_1[3], output net "alu_func_1[3]" in work.decoder(verilog)
    input nets to instance:
        net "alu_func_2[3]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_23" in work.decoder(verilog)
        net "un1_ins_i_20" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
21) instance alu_func_1[4] work.decoder(verilog)-alu_func_1[4], output net "alu_func_1[4]" in work.decoder(verilog)
    input nets to instance:
        net "alu_func_2[4]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "N_436" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
22) instance dmem_ctl_1[0] work.decoder(verilog)-dmem_ctl_1[0], output net "dmem_ctl_1[0]" in work.decoder(verilog)
    input nets to instance:
        net "dmem_ctl_2[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_23" in work.decoder(verilog)
        net "un1_ins_i_20" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
23) instance dmem_ctl_1[1] work.decoder(verilog)-dmem_ctl_1[1], output net "dmem_ctl_1[1]" in work.decoder(verilog)
    input nets to instance:
        net "dmem_ctl_2[1]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "N_438" in work.decoder(verilog)
        net "fsm_dly373" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
24) instance dmem_ctl_1[2] work.decoder(verilog)-dmem_ctl_1[2], output net "dmem_ctl_1[2]" in work.decoder(verilog)
    input nets to instance:
        net "dmem_ctl_2[2]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_24" in work.decoder(verilog)
        net "un1_ins_i_15" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
25) instance dmem_ctl_1[3] work.decoder(verilog)-dmem_ctl_1[3], output net "dmem_ctl_1[3]" in work.decoder(verilog)
    input nets to instance:
        net "dmem_ctl_2[3]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "N_436" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
26) instance alu_we[0] work.decoder(verilog)-alu_we[0], output net "alu_we[0]" in work.decoder(verilog)
    input nets to instance:
        net "alu_we_1[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "N_436" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
27) instance wb_mux[0] work.decoder(verilog)-wb_mux[0], output net "wb_mux[0]" in work.decoder(verilog)
    input nets to instance:
        net "wb_mux_1[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "N_436" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
28) instance wb_we[0] work.decoder(verilog)-wb_we[0], output net "wb_we[0]" in work.decoder(verilog)
    input nets to instance:
        net "wb_we_1[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "N_436" in work.decoder(verilog)
End of loops
Automatic dissolve during optimization of view:work.mips_core(verilog) of iRF_stage.reg_bank(reg_array)
Auto Dissolve of decoder_pipe (inst of view:work.decode_pipe(verilog))
Auto Dissolve of iRF_stage.i_cmp (inst of view:work.compare(verilog))
Auto Dissolve of mips_tmr0 (inst of view:work.tmr0(verilog))
Warning: Found 28 combinational loops!
         Each loop is reported with an instance in the loop
         and nets connected to that instance.
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
1) instance mips_core.decoder_pipe.idecoder.fsm_dly_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.fsm_dly_1[0], output net "mips_core.BUS197[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.fsm_dly_2[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
2) instance mips_core.decoder_pipe.idecoder.ext_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.ext_ctl_1[0], output net "mips_core.decoder_pipe.BUS2072[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.N_1345" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
3) instance mips_core.decoder_pipe.idecoder.ext_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.ext_ctl_1[1], output net "mips_core.decoder_pipe.BUS2072[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.N_1346" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
4) instance mips_core.decoder_pipe.idecoder.ext_ctl_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.ext_ctl_1[2], output net "mips_core.decoder_pipe.BUS2072[2]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.ext_ctl_2[2]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
5) instance mips_core.decoder_pipe.idecoder.rd_sel_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.rd_sel_1[0], output net "mips_core.decoder_pipe.BUS2110[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.rd_sel_2[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
6) instance mips_core.decoder_pipe.idecoder.rd_sel_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.rd_sel_1[1], output net "mips_core.decoder_pipe.BUS2110[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.rd_sel_2[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_438" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.fsm_dly373" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
7) instance mips_core.decoder_pipe.idecoder.cmp_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.cmp_ctl_1[0], output net "mips_core.decoder_pipe.BUS2056[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.cmp_ctl_2[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
8) instance mips_core.decoder_pipe.idecoder.cmp_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.cmp_ctl_1[1], output net "mips_core.decoder_pipe.BUS2056[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.cmp_ctl_2[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
9) instance mips_core.decoder_pipe.idecoder.cmp_ctl_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.cmp_ctl_1[2], output net "mips_core.decoder_pipe.BUS2056[2]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.cmp_ctl_2[2]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
10) instance mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[0], output net "mips_core.decoder_pipe.BUS2102[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.N_1348" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
11) instance mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[1], output net "mips_core.decoder_pipe.BUS2102[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.pc_gen_ctl_2[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
12) instance mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[2], output net "mips_core.decoder_pipe.BUS2102[2]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.N_1232_i" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
13) instance mips_core.decoder_pipe.idecoder.muxa_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxa_ctl_1[0], output net "mips_core.decoder_pipe.BUS2086[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.muxa_ctl_2[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
14) instance mips_core.decoder_pipe.idecoder.muxa_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxa_ctl_1[1], output net "mips_core.decoder_pipe.BUS2086[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.muxa_ctl_2[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
15) instance mips_core.decoder_pipe.idecoder.muxb_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxb_ctl_1[0], output net "mips_core.decoder_pipe.BUS2094[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.muxb_ctl_2[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
16) instance mips_core.decoder_pipe.idecoder.muxb_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxb_ctl_1[1], output net "mips_core.decoder_pipe.BUS2094[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.muxb_ctl_2[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
17) instance mips_core.decoder_pipe.idecoder.alu_func_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[0], output net "mips_core.decoder_pipe.BUS2040[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.alu_func_2[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
18) instance mips_core.decoder_pipe.idecoder.alu_func_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[1], output net "mips_core.decoder_pipe.BUS2040[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.alu_func_2[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
19) instance mips_core.decoder_pipe.idecoder.alu_func_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[2], output net "mips_core.decoder_pipe.BUS2040[2]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.N_1344" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
20) instance mips_core.decoder_pipe.idecoder.alu_func_1[3] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[3], output net "mips_core.decoder_pipe.BUS2040[3]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.alu_func_2[3]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
21) instance mips_core.decoder_pipe.idecoder.alu_func_1[4] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[4], output net "mips_core.decoder_pipe.BUS2040[4]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.alu_func_2[4]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
22) instance mips_core.decoder_pipe.idecoder.dmem_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[0], output net "mips_core.decoder_pipe.BUS2064[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
23) instance mips_core.decoder_pipe.idecoder.dmem_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[1], output net "mips_core.decoder_pipe.BUS2064[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_438" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.fsm_dly373" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
24) instance mips_core.decoder_pipe.idecoder.dmem_ctl_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[2], output net "mips_core.decoder_pipe.BUS2064[2]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[2]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_24" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_15" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
25) instance mips_core.decoder_pipe.idecoder.dmem_ctl_1[3] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[3], output net "mips_core.decoder_pipe.BUS2064[3]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[3]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
26) instance mips_core.decoder_pipe.idecoder.alu_we[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_we[0], output net "mips_core.decoder_pipe.BUS2048[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.alu_we_1[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
27) instance mips_core.decoder_pipe.idecoder.wb_mux[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.wb_mux[0], output net "mips_core.decoder_pipe.BUS2118[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.wb_mux_1[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
28) instance mips_core.decoder_pipe.idecoder.wb_we[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.wb_we[0], output net "mips_core.decoder_pipe.BUS2126[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.wb_we_1[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
End of loops
@W: BN116 :"e:\mips789\mips789\rtl\verilog\ulit.v":104:111:104:116|Removing sequential instance mips_core.iRF_stage.ins_reg.r32_o[31] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\ulit.v":104:111:104:116|Removing sequential instance mips_core.iRF_stage.ins_reg.r32_o[30] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\ulit.v":104:111:104:116|Removing sequential instance mips_core.iRF_stage.ins_reg.r32_o[29] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\ulit.v":104:111:104:116|Removing sequential instance mips_core.iRF_stage.ins_reg.r32_o[28] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\ulit.v":104:111:104:116|Removing sequential instance mips_core.iRF_stage.ins_reg.r32_o[27] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\ulit.v":104:111:104:116|Removing sequential instance mips_core.iRF_stage.ins_reg.r32_o[26] of view:PrimLib.dff(prim) because there are no references to its outputs 
Warning: Found 28 combinational loops!
         Each loop is reported with an instance in the loop
         and nets connected to that instance.
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
1) instance mips_core.decoder_pipe.idecoder.fsm_dly_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.fsm_dly_1[0], output net "mips_core.BUS197[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.fsm_dly_2[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
2) instance mips_core.decoder_pipe.idecoder.ext_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.ext_ctl_1[0], output net "mips_core.decoder_pipe.BUS2072[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.N_1345" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
3) instance mips_core.decoder_pipe.idecoder.ext_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.ext_ctl_1[1], output net "mips_core.decoder_pipe.BUS2072[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.N_1346" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
4) instance mips_core.decoder_pipe.idecoder.ext_ctl_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.ext_ctl_1[2], output net "mips_core.decoder_pipe.BUS2072[2]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.ext_ctl_2[2]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
5) instance mips_core.decoder_pipe.idecoder.rd_sel_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.rd_sel_1[0], output net "mips_core.decoder_pipe.BUS2110[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.rd_sel_2[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
6) instance mips_core.decoder_pipe.idecoder.rd_sel_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.rd_sel_1[1], output net "mips_core.decoder_pipe.BUS2110[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.rd_sel_2[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_438" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.fsm_dly373" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
7) instance mips_core.decoder_pipe.idecoder.cmp_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.cmp_ctl_1[0], output net "mips_core.decoder_pipe.BUS2056[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.cmp_ctl_2[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
8) instance mips_core.decoder_pipe.idecoder.cmp_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.cmp_ctl_1[1], output net "mips_core.decoder_pipe.BUS2056[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.cmp_ctl_2[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
9) instance mips_core.decoder_pipe.idecoder.cmp_ctl_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.cmp_ctl_1[2], output net "mips_core.decoder_pipe.BUS2056[2]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.cmp_ctl_2[2]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
10) instance mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[0], output net "mips_core.decoder_pipe.BUS2102[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.N_1348" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
11) instance mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[1], output net "mips_core.decoder_pipe.BUS2102[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.pc_gen_ctl_2[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
12) instance mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[2], output net "mips_core.decoder_pipe.BUS2102[2]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.N_1232_i" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
13) instance mips_core.decoder_pipe.idecoder.muxa_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxa_ctl_1[0], output net "mips_core.decoder_pipe.BUS2086[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.muxa_ctl_2[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
14) instance mips_core.decoder_pipe.idecoder.muxa_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxa_ctl_1[1], output net "mips_core.decoder_pipe.BUS2086[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.muxa_ctl_2[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
15) instance mips_core.decoder_pipe.idecoder.muxb_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxb_ctl_1[0], output net "mips_core.decoder_pipe.BUS2094[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.muxb_ctl_2[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
16) instance mips_core.decoder_pipe.idecoder.muxb_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxb_ctl_1[1], output net "mips_core.decoder_pipe.BUS2094[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.muxb_ctl_2[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
17) instance mips_core.decoder_pipe.idecoder.alu_func_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[0], output net "mips_core.decoder_pipe.BUS2040[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.alu_func_2[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
18) instance mips_core.decoder_pipe.idecoder.alu_func_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[1], output net "mips_core.decoder_pipe.BUS2040[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.alu_func_2[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
19) instance mips_core.decoder_pipe.idecoder.alu_func_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[2], output net "mips_core.decoder_pipe.BUS2040[2]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.N_1344" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
20) instance mips_core.decoder_pipe.idecoder.alu_func_1[3] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[3], output net "mips_core.decoder_pipe.BUS2040[3]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.alu_func_2[3]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
21) instance mips_core.decoder_pipe.idecoder.alu_func_1[4] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[4], output net "mips_core.decoder_pipe.BUS2040[4]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.alu_func_2[4]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
22) instance mips_core.decoder_pipe.idecoder.dmem_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[0], output net "mips_core.decoder_pipe.BUS2064[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
23) instance mips_core.decoder_pipe.idecoder.dmem_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[1], output net "mips_core.decoder_pipe.BUS2064[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_438" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.fsm_dly373" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
24) instance mips_core.decoder_pipe.idecoder.dmem_ctl_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[2], output net "mips_core.decoder_pipe.BUS2064[2]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[2]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_18_m" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_15" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
25) instance mips_core.decoder_pipe.idecoder.dmem_ctl_1[3] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[3], output net "mips_core.decoder_pipe.BUS2064[3]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[3]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
26) instance mips_core.decoder_pipe.idecoder.alu_we[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_we[0], output net "mips_core.decoder_pipe.BUS2048[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.alu_we_1[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
27) instance mips_core.decoder_pipe.idecoder.wb_mux[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.wb_mux[0], output net "mips_core.decoder_pipe.BUS2118[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.wb_mux_1[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
28) instance mips_core.decoder_pipe.idecoder.wb_we[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.wb_we[0], output net "mips_core.decoder_pipe.BUS2126[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.wb_we_1[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
End of loops
Warning: Found 28 combinational loops!
         Each loop is reported with an instance in the loop
         and nets connected to that instance.
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
1) instance mips_core.decoder_pipe.idecoder.fsm_dly_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.fsm_dly_1[0], output net "mips_core.BUS197[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.fsm_dly_2[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
2) instance mips_core.decoder_pipe.idecoder.ext_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.ext_ctl_1[0], output net "mips_core.decoder_pipe.BUS2072[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.N_1345" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
3) instance mips_core.decoder_pipe.idecoder.ext_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.ext_ctl_1[1], output net "mips_core.decoder_pipe.BUS2072[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.N_1346" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
4) instance mips_core.decoder_pipe.idecoder.ext_ctl_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.ext_ctl_1[2], output net "mips_core.decoder_pipe.BUS2072[2]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.ext_ctl_2[2]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
5) instance mips_core.decoder_pipe.idecoder.rd_sel_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.rd_sel_1[0], output net "mips_core.decoder_pipe.BUS2110[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.rd_sel_2[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
6) instance mips_core.decoder_pipe.idecoder.rd_sel_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.rd_sel_1[1], output net "mips_core.decoder_pipe.BUS2110[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.rd_sel_2[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_438" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.fsm_dly373" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
7) instance mips_core.decoder_pipe.idecoder.cmp_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.cmp_ctl_1[0], output net "mips_core.decoder_pipe.BUS2056[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.cmp_ctl_2[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
8) instance mips_core.decoder_pipe.idecoder.cmp_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.cmp_ctl_1[1], output net "mips_core.decoder_pipe.BUS2056[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.cmp_ctl_2[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
9) instance mips_core.decoder_pipe.idecoder.cmp_ctl_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.cmp_ctl_1[2], output net "mips_core.decoder_pipe.BUS2056[2]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.cmp_ctl_2[2]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
10) instance mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[0], output net "mips_core.decoder_pipe.BUS2102[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.N_1348" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
11) instance mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[1], output net "mips_core.decoder_pipe.BUS2102[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.pc_gen_ctl_2[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
12) instance mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[2], output net "mips_core.decoder_pipe.BUS2102[2]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.N_1232_i" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
13) instance mips_core.decoder_pipe.idecoder.muxa_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxa_ctl_1[0], output net "mips_core.decoder_pipe.BUS2086[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.muxa_ctl_2[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
14) instance mips_core.decoder_pipe.idecoder.muxa_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxa_ctl_1[1], output net "mips_core.decoder_pipe.BUS2086[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.muxa_ctl_2[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
15) instance mips_core.decoder_pipe.idecoder.muxb_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxb_ctl_1[0], output net "mips_core.decoder_pipe.BUS2094[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.muxb_ctl_2[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
16) instance mips_core.decoder_pipe.idecoder.muxb_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxb_ctl_1[1], output net "mips_core.decoder_pipe.BUS2094[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.muxb_ctl_2[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
17) instance mips_core.decoder_pipe.idecoder.alu_func_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[0], output net "mips_core.decoder_pipe.BUS2040[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.alu_func_2[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
18) instance mips_core.decoder_pipe.idecoder.alu_func_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[1], output net "mips_core.decoder_pipe.BUS2040[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.alu_func_2[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
19) instance mips_core.decoder_pipe.idecoder.alu_func_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[2], output net "mips_core.decoder_pipe.BUS2040[2]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.N_1344" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
20) instance mips_core.decoder_pipe.idecoder.alu_func_1[3] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[3], output net "mips_core.decoder_pipe.BUS2040[3]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.alu_func_2[3]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
21) instance mips_core.decoder_pipe.idecoder.alu_func_1[4] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[4], output net "mips_core.decoder_pipe.BUS2040[4]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.alu_func_2[4]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
22) instance mips_core.decoder_pipe.idecoder.dmem_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[0], output net "mips_core.decoder_pipe.BUS2064[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
23) instance mips_core.decoder_pipe.idecoder.dmem_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[1], output net "mips_core.decoder_pipe.BUS2064[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_438" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.fsm_dly373" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
24) instance mips_core.decoder_pipe.idecoder.dmem_ctl_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[2], output net "mips_core.decoder_pipe.BUS2064[2]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[2]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_18_m" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_15" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
25) instance mips_core.decoder_pipe.idecoder.dmem_ctl_1[3] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[3], output net "mips_core.decoder_pipe.BUS2064[3]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[3]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
26) instance mips_core.decoder_pipe.idecoder.alu_we[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_we[0], output net "mips_core.decoder_pipe.BUS2048[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.alu_we_1[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
27) instance mips_core.decoder_pipe.idecoder.wb_mux[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.wb_mux[0], output net "mips_core.decoder_pipe.BUS2118[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.wb_mux_1[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
28) instance mips_core.decoder_pipe.idecoder.wb_we[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.wb_we[0], output net "mips_core.decoder_pipe.BUS2126[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.wb_we_1[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
End of loops
Warning: Found 28 combinational loops!
         Each loop is reported with an instance in the loop
         and nets connected to that instance.
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
1) instance mips_core.decoder_pipe.idecoder.fsm_dly_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.fsm_dly_1[0], output net "mips_core.BUS197[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.fsm_dly_2[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
2) instance mips_core.decoder_pipe.idecoder.ext_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.ext_ctl_1[0], output net "mips_core.decoder_pipe.BUS2072[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.N_1345" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
3) instance mips_core.decoder_pipe.idecoder.ext_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.ext_ctl_1[1], output net "mips_core.decoder_pipe.BUS2072[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.N_1346" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
4) instance mips_core.decoder_pipe.idecoder.ext_ctl_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.ext_ctl_1[2], output net "mips_core.decoder_pipe.BUS2072[2]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.ext_ctl_2[2]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
5) instance mips_core.decoder_pipe.idecoder.rd_sel_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.rd_sel_1[0], output net "mips_core.decoder_pipe.BUS2110[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.rd_sel_2[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
6) instance mips_core.decoder_pipe.idecoder.rd_sel_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.rd_sel_1[1], output net "mips_core.decoder_pipe.BUS2110[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.rd_sel_2[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_438" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.fsm_dly373" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
7) instance mips_core.decoder_pipe.idecoder.cmp_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.cmp_ctl_1[0], output net "mips_core.decoder_pipe.BUS2056[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.cmp_ctl_2[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
8) instance mips_core.decoder_pipe.idecoder.cmp_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.cmp_ctl_1[1], output net "mips_core.decoder_pipe.BUS2056[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.cmp_ctl_2[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
9) instance mips_core.decoder_pipe.idecoder.cmp_ctl_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.cmp_ctl_1[2], output net "mips_core.decoder_pipe.BUS2056[2]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.cmp_ctl_2[2]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
10) instance mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[0], output net "mips_core.decoder_pipe.BUS2102[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.N_1348" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
11) instance mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[1], output net "mips_core.decoder_pipe.BUS2102[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.pc_gen_ctl_2[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
12) instance mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[2], output net "mips_core.decoder_pipe.BUS2102[2]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.N_1232_i" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
13) instance mips_core.decoder_pipe.idecoder.muxa_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxa_ctl_1[0], output net "mips_core.decoder_pipe.BUS2086[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.muxa_ctl_2[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
14) instance mips_core.decoder_pipe.idecoder.muxa_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxa_ctl_1[1], output net "mips_core.decoder_pipe.BUS2086[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.muxa_ctl_2[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
15) instance mips_core.decoder_pipe.idecoder.muxb_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxb_ctl_1[0], output net "mips_core.decoder_pipe.BUS2094[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.muxb_ctl_2[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
16) instance mips_core.decoder_pipe.idecoder.muxb_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxb_ctl_1[1], output net "mips_core.decoder_pipe.BUS2094[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.muxb_ctl_2[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
17) instance mips_core.decoder_pipe.idecoder.alu_func_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[0], output net "mips_core.decoder_pipe.BUS2040[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.alu_func_2[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
18) instance mips_core.decoder_pipe.idecoder.alu_func_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[1], output net "mips_core.decoder_pipe.BUS2040[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.alu_func_2[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
19) instance mips_core.decoder_pipe.idecoder.alu_func_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[2], output net "mips_core.decoder_pipe.BUS2040[2]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.N_1344" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
20) instance mips_core.decoder_pipe.idecoder.alu_func_1[3] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[3], output net "mips_core.decoder_pipe.BUS2040[3]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.alu_func_2[3]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
21) instance mips_core.decoder_pipe.idecoder.alu_func_1[4] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[4], output net "mips_core.decoder_pipe.BUS2040[4]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.alu_func_2[4]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
22) instance mips_core.decoder_pipe.idecoder.dmem_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[0], output net "mips_core.decoder_pipe.BUS2064[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
23) instance mips_core.decoder_pipe.idecoder.dmem_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[1], output net "mips_core.decoder_pipe.BUS2064[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_438" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.fsm_dly373" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
24) instance mips_core.decoder_pipe.idecoder.dmem_ctl_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[2], output net "mips_core.decoder_pipe.BUS2064[2]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[2]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_18_m" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_15" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
25) instance mips_core.decoder_pipe.idecoder.dmem_ctl_1[3] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[3], output net "mips_core.decoder_pipe.BUS2064[3]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[3]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
26) instance mips_core.decoder_pipe.idecoder.alu_we[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_we[0], output net "mips_core.decoder_pipe.BUS2048[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.alu_we_1[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
27) instance mips_core.decoder_pipe.idecoder.wb_mux[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.wb_mux[0], output net "mips_core.decoder_pipe.BUS2118[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.wb_mux_1[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
28) instance mips_core.decoder_pipe.idecoder.wb_we[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.wb_we[0], output net "mips_core.decoder_pipe.BUS2126[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.wb_we_1[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
End of loops
Encoding state machine ScratchLib.imips_dvc.iuart0.uart_txd.ua_state_7_0c(gate_dflt)-imips_dvc.iuart0.uart_txd.ua_state[7:0]
original code -> new code
   000 -> 00000000
   001 -> 00000011
   010 -> 00000101
   011 -> 00001001
   100 -> 00010001
   101 -> 00100001
   110 -> 01000001
   111 -> 10000001
Encoding state machine ScratchLib.imips_dvc.iuart0.uart_rd_tak.ua_state_4_0c(gate_dflt)-imips_dvc.iuart0.uart_rd_tak.ua_state[4:0]
original code -> new code
   000 -> 00000
   001 -> 00011
   010 -> 00101
   011 -> 01001
   100 -> 10001
Encoding state machine ScratchLib.mips_core.iRF_stage.MIAN_FSM.CurrState_Sreg0_8_0c(gate_dflt)-mips_core.iRF_stage.MIAN_FSM.CurrState_Sreg0[8:0]
original code -> new code
   0000 -> 000000000
   0001 -> 000000011
   0010 -> 000000101
   0011 -> 000001001
   0100 -> 000010001
   0101 -> 000100001
   0110 -> 001000001
   0111 -> 010000001
   1000 -> 100000001
@W: FA140 :"e:\mips789\mips789\rtl\verilog\ctl_fsm.v":126:16:126:16|DFF ScratchLib.mips_core.iRF_stage.MIAN_FSM.CurrState_Sreg0_8_0c(gate_dflt)-mips_core.iRF_stage.MIAN_FSM.CurrState_Sreg0[5] is stuck at '0', removing ... 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\ctl_fsm.v":126:16:126:16|Removing sequential instance mips_core.iRF_stage.MIAN_FSM.CurrState_Sreg0[5] of view:PrimLib.dff(prim) because there are no references to its outputs 
Warning: Found 27 combinational loops!
         Each loop is reported with an instance in the loop
         and nets connected to that instance.
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
1) instance mips_core.decoder_pipe.idecoder.ext_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.ext_ctl_1[0], output net "mips_core.decoder_pipe.BUS2072[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.N_1345" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
2) instance mips_core.decoder_pipe.idecoder.ext_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.ext_ctl_1[1], output net "mips_core.decoder_pipe.BUS2072[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.N_1346" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
3) instance mips_core.decoder_pipe.idecoder.ext_ctl_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.ext_ctl_1[2], output net "mips_core.decoder_pipe.BUS2072[2]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.ext_ctl_2[2]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
4) instance mips_core.decoder_pipe.idecoder.rd_sel_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.rd_sel_1[0], output net "mips_core.decoder_pipe.BUS2110[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.rd_sel_2[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
5) instance mips_core.decoder_pipe.idecoder.rd_sel_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.rd_sel_1[1], output net "mips_core.decoder_pipe.BUS2110[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.rd_sel_2[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_438" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.fsm_dly373" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
6) instance mips_core.decoder_pipe.idecoder.cmp_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.cmp_ctl_1[0], output net "mips_core.decoder_pipe.BUS2056[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.cmp_ctl_2[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
7) instance mips_core.decoder_pipe.idecoder.cmp_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.cmp_ctl_1[1], output net "mips_core.decoder_pipe.BUS2056[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.cmp_ctl_2[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
8) instance mips_core.decoder_pipe.idecoder.cmp_ctl_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.cmp_ctl_1[2], output net "mips_core.decoder_pipe.BUS2056[2]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.cmp_ctl_2[2]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
9) instance mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[0], output net "mips_core.decoder_pipe.BUS2102[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.N_1348" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
10) instance mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[1], output net "mips_core.decoder_pipe.BUS2102[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.pc_gen_ctl_2[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
11) instance mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[2], output net "mips_core.decoder_pipe.BUS2102[2]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.N_1232_i" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
12) instance mips_core.decoder_pipe.idecoder.muxa_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxa_ctl_1[0], output net "mips_core.decoder_pipe.BUS2086[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.muxa_ctl_2[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
13) instance mips_core.decoder_pipe.idecoder.muxa_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxa_ctl_1[1], output net "mips_core.decoder_pipe.BUS2086[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.muxa_ctl_2[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
14) instance mips_core.decoder_pipe.idecoder.muxb_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxb_ctl_1[0], output net "mips_core.decoder_pipe.BUS2094[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.muxb_ctl_2[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
15) instance mips_core.decoder_pipe.idecoder.muxb_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxb_ctl_1[1], output net "mips_core.decoder_pipe.BUS2094[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.muxb_ctl_2[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
16) instance mips_core.decoder_pipe.idecoder.alu_func_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[0], output net "mips_core.decoder_pipe.BUS2040[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.alu_func_2[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
17) instance mips_core.decoder_pipe.idecoder.alu_func_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[1], output net "mips_core.decoder_pipe.BUS2040[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.alu_func_2[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
18) instance mips_core.decoder_pipe.idecoder.alu_func_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[2], output net "mips_core.decoder_pipe.BUS2040[2]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.N_1344" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
19) instance mips_core.decoder_pipe.idecoder.alu_func_1[3] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[3], output net "mips_core.decoder_pipe.BUS2040[3]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.alu_func_2[3]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
20) instance mips_core.decoder_pipe.idecoder.alu_func_1[4] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[4], output net "mips_core.decoder_pipe.BUS2040[4]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.alu_func_2[4]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
21) instance mips_core.decoder_pipe.idecoder.dmem_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[0], output net "mips_core.decoder_pipe.BUS2064[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
22) instance mips_core.decoder_pipe.idecoder.dmem_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[1], output net "mips_core.decoder_pipe.BUS2064[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_438" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.fsm_dly373" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
23) instance mips_core.decoder_pipe.idecoder.dmem_ctl_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[2], output net "mips_core.decoder_pipe.BUS2064[2]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[2]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_18_m" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_15" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
24) instance mips_core.decoder_pipe.idecoder.dmem_ctl_1[3] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[3], output net "mips_core.decoder_pipe.BUS2064[3]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[3]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
25) instance mips_core.decoder_pipe.idecoder.alu_we[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_we[0], output net "mips_core.decoder_pipe.BUS2048[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.alu_we_1[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
26) instance mips_core.decoder_pipe.idecoder.wb_mux[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.wb_mux[0], output net "mips_core.decoder_pipe.BUS2118[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.wb_mux_1[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
27) instance mips_core.decoder_pipe.idecoder.wb_we[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.wb_we[0], output net "mips_core.decoder_pipe.BUS2126[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.wb_we_1[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
End of loops
Warning: Found 28 combinational loops!
         Each loop is reported with an instance in the loop
         and nets connected to that instance.
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.BUS197[0]
1) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.fsm_dly_1[0], output net "mips_core.BUS197[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.fsm_dly_2[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2072[0]
2) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.ext_ctl_1[0], output net "mips_core.decoder_pipe.BUS2072[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.N_1345" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2072[1]
3) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.ext_ctl_1[1], output net "mips_core.decoder_pipe.BUS2072[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.N_1346" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2072[2]
4) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.ext_ctl_1[2], output net "mips_core.decoder_pipe.BUS2072[2]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.ext_ctl_2[2]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2110[0]
5) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.rd_sel_1[0], output net "mips_core.decoder_pipe.BUS2110[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.rd_sel_2[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2110[1]
6) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.rd_sel_1[1], output net "mips_core.decoder_pipe.BUS2110[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.rd_sel_2[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_438" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.fsm_dly373" in work.mips_sys(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2056[0]
7) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.cmp_ctl_1[0], output net "mips_core.decoder_pipe.BUS2056[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.cmp_ctl_2[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2056[1]
8) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.cmp_ctl_1[1], output net "mips_core.decoder_pipe.BUS2056[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.cmp_ctl_2[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2056[2]
9) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.cmp_ctl_1[2], output net "mips_core.decoder_pipe.BUS2056[2]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.cmp_ctl_2[2]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2102[0]
10) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[0], output net "mips_core.decoder_pipe.BUS2102[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.N_1348" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2102[1]
11) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[1], output net "mips_core.decoder_pipe.BUS2102[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.pc_gen_ctl_2[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2102[2]
12) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[2], output net "mips_core.decoder_pipe.BUS2102[2]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.N_1232_i_0" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2086[0]
13) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxa_ctl_1[0], output net "mips_core.decoder_pipe.BUS2086[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.muxa_ctl_2[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2086[1]
14) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxa_ctl_1[1], output net "mips_core.decoder_pipe.BUS2086[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.muxa_ctl_2[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2094[0]
15) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxb_ctl_1[0], output net "mips_core.decoder_pipe.BUS2094[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.muxb_ctl_2[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2094[1]
16) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxb_ctl_1[1], output net "mips_core.decoder_pipe.BUS2094[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.muxb_ctl_2[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2040[0]
17) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[0], output net "mips_core.decoder_pipe.BUS2040[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.alu_func_2[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2040[1]
18) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[1], output net "mips_core.decoder_pipe.BUS2040[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.alu_func_2[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2040[2]
19) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[2], output net "mips_core.decoder_pipe.BUS2040[2]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.N_1344" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2040[3]
20) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[3], output net "mips_core.decoder_pipe.BUS2040[3]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.alu_func_2[3]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2040[4]
21) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[4], output net "mips_core.decoder_pipe.BUS2040[4]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.alu_func_2[4]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2064[0]
22) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[0], output net "mips_core.decoder_pipe.BUS2064[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2064[1]
23) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[1], output net "mips_core.decoder_pipe.BUS2064[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_438" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.fsm_dly373" in work.mips_sys(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2064[2]
24) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[2], output net "mips_core.decoder_pipe.BUS2064[2]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[2]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_18_m" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_15" in work.mips_sys(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2064[3]
25) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[3], output net "mips_core.decoder_pipe.BUS2064[3]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[3]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2048[0]
26) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_we[0], output net "mips_core.decoder_pipe.BUS2048[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.alu_we_1[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2118[0]
27) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.wb_mux[0], output net "mips_core.decoder_pipe.BUS2118[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.wb_mux_1[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2126[0]
28) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.wb_we[0], output net "mips_core.decoder_pipe.BUS2126[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.wb_we_1[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
End of loops
@N: MF197 |Retiming summary : 0 registers retimed to 0 

                #####  BEGIN RETIMING REPORT  #####

Retiming summary : 0 registers retimed to 0

Original and Pipelined registers replaced by retiming :
                None

New registers created by retiming :
                None


                #####   END RETIMING REPORT  #####

Warning: Found 28 combinational loops!
         Each loop is reported with an instance in the loop
         and nets connected to that instance.
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.idecoder.fsm_dly_2_0_0_i_a2_0_a2[0]
1) instance ScratchLib.mips_core.iRF_stage.MIAN_FSM.CurrState_Sreg0_8_0c(gate_dflt)-mips_core.decoder_pipe.idecoder.fsm_dly_2_0_0_i_a2_0_a2[0], output net "mips_core.decoder_pipe.idecoder.fsm_dly_2_0_0_i_a2_0_a2[0]" in ScratchLib.mips_core.iRF_stage.MIAN_FSM.CurrState_Sreg0_8_0c(gate_dflt)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.N_1594" in ScratchLib.mips_core.iRF_stage.MIAN_FSM.CurrState_Sreg0_8_0c(gate_dflt)
        net "mips_core.decoder_pipe.idecoder.N_1710" in ScratchLib.mips_core.iRF_stage.MIAN_FSM.CurrState_Sreg0_8_0c(gate_dflt)
        net "mips_core.BUS197[0]" in ScratchLib.mips_core.iRF_stage.MIAN_FSM.CurrState_Sreg0_8_0c(gate_dflt)
        net "mips_core.decoder_pipe.idecoder.N_1666_1" in ScratchLib.mips_core.iRF_stage.MIAN_FSM.CurrState_Sreg0_8_0c(gate_dflt)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.idecoder.wb_mux_1_0_0[0]
2) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.wb_mux_1_0_0[0], output net "mips_core.decoder_pipe.idecoder.wb_mux_1_0_0[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0_a2_0[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.BUS2118[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.wb_mux_1_0_0_a3[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.fsm_dly_2_0_0_o2_x[2]" in work.mips_sys(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.idecoder.wb_we_1_0_0_x[0]
3) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.wb_we_1_0_0_x[0], output net "mips_core.decoder_pipe.idecoder.wb_we_1_0_0_x[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.wb_mux_1_0_0_a3[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.wb_we_1_0_0_0[0]" in work.mips_sys(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.idecoder.alu_func_2_0_0[0]
4) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_2_0_0[0], output net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "zz_ins_i_c[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0_a3_0_0[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0_a3_0_1[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0_3[0]" in work.mips_sys(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.idecoder.alu_func_2_0_0_x[1]
5) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_2_0_0_x[1], output net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0_x[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0_a3_2[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0_a3_1[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0_3[1]" in work.mips_sys(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.idecoder.alu_func_2_0_0[3]
6) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_2_0_0[3], output net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0[3]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0_a3_0[3]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0_a3[3]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0_o3[3]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0_a3_1[3]" in work.mips_sys(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.idecoder.alu_func_2_0_0[4]
7) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_2_0_0[4], output net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0[4]" in work.mips_sys(verilog)
    input nets to instance:
        net "zz_ins_i_c[29]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0_a3_0[4]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0_a_x[4]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0_3[4]" in work.mips_sys(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.idecoder.alu_we_1_0_0[0]
8) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_we_1_0_0[0], output net "mips_core.decoder_pipe.idecoder.alu_we_1_0_0[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "zz_ins_i_c[29]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.alu_we_1_0_0_a3_0[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.alu_we_1_0_0_0[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.alu_we_1_0_0_a3_x[0]" in work.mips_sys(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.idecoder.ext_ctl_2_0_0[2]
9) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.ext_ctl_2_0_0[2], output net "mips_core.decoder_pipe.idecoder.ext_ctl_2_0_0[2]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.BUS2072[2]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.fsm_dly_2_0_0_a3_1[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.ext_ctl_2_0_0_o3[2]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.ext_ctl_2_0_0_0[2]" in work.mips_sys(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.idecoder.muxa_ctl_2_0_0[0]
10) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxa_ctl_2_0_0[0], output net "mips_core.decoder_pipe.idecoder.muxa_ctl_2_0_0[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.muxa_ctl_2_0_0_a3[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.muxa_ctl_2_0_0_a[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.muxa_ctl_2_0_0_a3_1[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.ext_ctl_2_0_0_a2_2_x[2]" in work.mips_sys(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.idecoder.muxa_ctl_2_0_0[1]
11) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxa_ctl_2_0_0[1], output net "mips_core.decoder_pipe.idecoder.muxa_ctl_2_0_0[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "zz_ins_i_c[29]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0_a3[3]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.muxa_ctl_2_0_0_0[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.muxa_ctl_2_0_0_a[1]" in work.mips_sys(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.idecoder.muxb_ctl_2_0_0[0]
12) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxb_ctl_2_0_0[0], output net "mips_core.decoder_pipe.idecoder.muxb_ctl_2_0_0[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0_a2_0[1]" in work.mips_sys(verilog)
        net "zz_ins_i_c[4]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.muxa_ctl_2_0_0_o2_0[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.muxb_ctl_2_0_0_1[0]" in work.mips_sys(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.idecoder.muxb_ctl_2_0_0[1]
13) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxb_ctl_2_0_0[1], output net "mips_core.decoder_pipe.idecoder.muxb_ctl_2_0_0[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "zz_ins_i_c[29]" in work.mips_sys(verilog)
        net "zz_ins_i_c[30]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.muxb_ctl_2_0_0_a[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.muxb_ctl_2_0_0_0[1]" in work.mips_sys(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.idecoder.pc_gen_ctl_2_0_0[1]
14) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.pc_gen_ctl_2_0_0[1], output net "mips_core.decoder_pipe.idecoder.pc_gen_ctl_2_0_0[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.BUS2102[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0_a2_0[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0_3_a_x[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.pc_gen_ctl_2_0_0_0[1]" in work.mips_sys(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.idecoder.rd_sel_2_0_0[0]
15) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.rd_sel_2_0_0[0], output net "mips_core.decoder_pipe.idecoder.rd_sel_2_0_0[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0_a2_0[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.rd_sel_2_0_0_a3_1[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0_a3_1[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.rd_sel_2_0_0_a[0]" in work.mips_sys(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.idecoder.rd_sel_2_0_0[1]
16) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.rd_sel_2_0_0[1], output net "mips_core.decoder_pipe.idecoder.rd_sel_2_0_0[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.BUS2110[1]" in work.mips_sys(verilog)
        net "zz_ins_i_c[31]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.rd_sel_2_0_0_0[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.rd_sel_2_0_0_a[1]" in work.mips_sys(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.idecoder.cmp_ctl_2_0_0[0]
17) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.cmp_ctl_2_0_0[0], output net "mips_core.decoder_pipe.idecoder.cmp_ctl_2_0_0[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0_a2_0[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.cmp_ctl_2_0_0_a2_1[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.BUS2056[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.cmp_ctl_2_0_0_1[0]" in work.mips_sys(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.idecoder.cmp_ctl_2_0_0[1]
18) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.cmp_ctl_2_0_0[1], output net "mips_core.decoder_pipe.idecoder.cmp_ctl_2_0_0[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0_a2_0[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.cmp_ctl_2_0_0_a2_0[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.BUS2056[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.cmp_ctl_2_0_0_2[1]" in work.mips_sys(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.idecoder.cmp_ctl_2_0_0[2]
19) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.cmp_ctl_2_0_0[2], output net "mips_core.decoder_pipe.idecoder.cmp_ctl_2_0_0[2]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.BUS2056[2]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0_a2_0[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.ext_ctl_2_0_0_o2[2]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.cmp_ctl_2_0_0_0[2]" in work.mips_sys(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.idecoder.dmem_ctl_2_0_0[0]
20) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_2_0_0[0], output net "mips_core.decoder_pipe.idecoder.dmem_ctl_2_0_0[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0_a2_0[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.BUS2064[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.fsm_dly_2_0_0_o2_x[2]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0_a3_1_x[4]" in work.mips_sys(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.idecoder.dmem_ctl_2_0_0[1]
21) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_2_0_0[1], output net "mips_core.decoder_pipe.idecoder.dmem_ctl_2_0_0[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.BUS2064[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0_a2_0[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0_3_a_x[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.dmem_ctl_2_0_0_1[1]" in work.mips_sys(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.idecoder.dmem_ctl_2_0_0[2]
22) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_2_0_0[2], output net "mips_core.decoder_pipe.idecoder.dmem_ctl_2_0_0[2]" in work.mips_sys(verilog)
    input nets to instance:
        net "zz_ins_i_c[29]" in work.mips_sys(verilog)
        net "zz_ins_i_c[30]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.dmem_ctl_2_0_0_a3[2]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.dmem_ctl_2_0_0_a[2]" in work.mips_sys(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.idecoder.dmem_ctl_2_0_0[3]
23) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_2_0_0[3], output net "mips_core.decoder_pipe.idecoder.dmem_ctl_2_0_0[3]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0_a2_0[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.BUS2064[3]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.dmem_ctl_2_0_0_a3_0[3]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.fsm_dly_2_0_0_o2_x[2]" in work.mips_sys(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.idecoder.pc_gen_ctl_2_i_0[2]
24) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.pc_gen_ctl_2_i_0[2], output net "mips_core.decoder_pipe.idecoder.pc_gen_ctl_2_i_0[2]" in work.mips_sys(verilog)
    input nets to instance:
        net "zz_ins_i_c[2]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.pc_gen_ctl_2_i_0_a3_0_0[2]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.pc_gen_ctl_2_i_0_a[2]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.pc_gen_ctl_2_i_0_4_x[2]" in work.mips_sys(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.idecoder.alu_func_2_i_m3_0[2]
25) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_2_i_m3_0[2], output net "mips_core.decoder_pipe.idecoder.alu_func_2_i_m3_0[2]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.alu_func_2_i_m3_0_a3_3[2]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.alu_func_2_i_m3_0_a3[2]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0_a3_1[3]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.alu_func_2_i_m3_0_4[2]" in work.mips_sys(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.idecoder.ext_ctl_2_i_m3_0[0]
26) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.ext_ctl_2_i_m3_0[0], output net "mips_core.decoder_pipe.idecoder.ext_ctl_2_i_m3_0[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.ext_ctl_2_i_m3_0_a3_0[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.fsm_dly_2_0_0_a3_0[2]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0_o3[3]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.ext_ctl_2_i_m3_0_2[0]" in work.mips_sys(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.idecoder.ext_ctl_2_i_m3_0[1]
27) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.ext_ctl_2_i_m3_0[1], output net "mips_core.decoder_pipe.idecoder.ext_ctl_2_i_m3_0[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "zz_ins_i_c[29]" in work.mips_sys(verilog)
        net "zz_ins_i_c[28]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0_a2_0_x[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.ext_ctl_2_i_m3_0_a[1]" in work.mips_sys(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.idecoder.pc_gen_ctl_2_i_m3_0_x[0]
28) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.pc_gen_ctl_2_i_m3_0_x[0], output net "mips_core.decoder_pipe.idecoder.pc_gen_ctl_2_i_m3_0_x[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "zz_ins_i_c[4]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.pc_gen_ctl_2_i_m3_0_5[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.pc_gen_ctl_2_i_m3_0_a3_0_1_x[0]" in work.mips_sys(verilog)
End of loops
FSM Explorer successful!
Process took 0h:1m:29s realtime, 0h:1m:29s cputime
###########################################################]
###########################################################[
Version 8.1
Synplicity Altera Technology Mapper, Version 8.1.0, Build 539R, Built May  6 2005
Copyright (C) 1994-2005, Synplicity Inc.  All Rights Reserved


Automatic dissolve at startup in view:work.mem_module(verilog) of i_mem_din_ctl(mem_din_ctl)
Automatic dissolve at startup in view:work.mem_module(verilog) of i_mem_addr_ctl(mem_addr_ctl)
Automatic dissolve at startup in view:work.mem_module(verilog) of dmem_ctl_post(infile_dmem_ctl_reg)
Automatic dissolve at startup in view:work.rf_stage(verilog) of rs_fwd_rs(fwd_mux)
Automatic dissolve at startup in view:work.rf_stage(verilog) of rf_fwd_rt(fwd_mux)
Automatic dissolve at startup in view:work.rf_stage(verilog) of jack2(jack)
Automatic dissolve at startup in view:work.rf_stage(verilog) of jack1(jack)
Automatic dissolve at startup in view:work.rf_stage(verilog) of ins_reg(r32_reg_clr_cls)
Automatic dissolve at startup in view:work.rf_stage(verilog) of i_pc_gen(pc_gen)
Automatic dissolve at startup in view:work.exec_stage(verilog) of spc(r32_reg_cls)
Automatic dissolve at startup in view:work.exec_stage(verilog) of pc_nxt(r32_reg)
Automatic dissolve at startup in view:work.exec_stage(verilog) of i_alu_muxb(alu_muxb)
Automatic dissolve at startup in view:work.exec_stage(verilog) of i_alu_muxa(alu_muxa)
Automatic dissolve at startup in view:work.exec_stage(verilog) of dmem_fw_mux(fwd_mux)
Automatic dissolve at startup in view:work.exec_stage(verilog) of add4(add32)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U9(dmem_ctl_reg)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U8(pc_gen_ctl_reg_clr_cls)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U7(muxa_ctl_reg_clr_cls)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U6(alu_we_reg_clr_cls)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U5(rd_sel_reg_clr_cls)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U4(ext_ctl_reg_clr_cls)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U3(dmem_ctl_reg_clr_cls)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U26(alu_func_reg_clr_cls)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U24(alu_we_reg_clr)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U22(wb_we_reg)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U21(wb_mux_ctl_reg)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U20(wb_we_reg)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U2(cmp_ctl_reg_clr_cls)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U19(wb_we_reg_clr)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U18(wb_mux_ctl_reg)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U17(muxa_ctl_reg_clr)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U16(alu_func_reg_clr)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U15(dmem_ctl_reg_clr)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U14(muxb_ctl_reg_clr)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U13(wb_mux_ctl_reg_clr)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U12(wb_we_reg)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U11(wb_we_reg_clr_cls)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U10(wb_mux_ctl_reg_clr_cls)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U1(muxb_ctl_reg_clr_cls)
Automatic dissolve at startup in view:work.decode_pipe(verilog) of pipereg(pipelinedregs)
Automatic dissolve at startup in view:work.forward(verilog) of fw_reg_rnt(fw_latch5)
Automatic dissolve at startup in view:work.forward(verilog) of fw_reg_rns(fw_latch5)
Automatic dissolve at startup in view:work.mips_core(verilog) of wb_mux(wb_mux)
Automatic dissolve at startup in view:work.mips_core(verilog) of rt_reg(r32_reg)
Automatic dissolve at startup in view:work.mips_core(verilog) of rs_reg(r32_reg)
Automatic dissolve at startup in view:work.mips_core(verilog) of rnd_pass2(r5_reg)
Automatic dissolve at startup in view:work.mips_core(verilog) of rnd_pass1(r5_reg)
Automatic dissolve at startup in view:work.mips_core(verilog) of rnd_pass0(r5_reg)
Automatic dissolve at startup in view:work.mips_core(verilog) of pc(r32_reg)
Automatic dissolve at startup in view:work.mips_core(verilog) of ext_reg(r32_reg)
Automatic dissolve at startup in view:work.mips_core(verilog) of cop_dout_reg(r32_reg)
Automatic dissolve at startup in view:work.mips_core(verilog) of cop_data_reg(r32_reg)
Automatic dissolve at startup in view:work.mips_core(verilog) of cop_data_or(or32)
Automatic dissolve at startup in view:work.mips_core(verilog) of alu_pass1(r32_reg)
Automatic dissolve at startup in view:work.mips_core(verilog) of alu_pass0(r32_reg)
Automatic dissolve at startup in view:work.mips_core(verilog) of iexec_stage(exec_stage)
Automatic dissolve at startup in view:work.mips_core(verilog) of iRF_stage(rf_stage)
Automatic dissolve at startup in view:work.mips_core(verilog) of MEM_CTL(mem_module)
Automatic dissolve at startup in view:work.uart_write(verilog) of fifo(fifo512_cyclone)
Automatic dissolve at startup in view:work.uart0(verilog) of rxd_rdy_hold_lw(rxd_d)
Automatic dissolve at startup in view:work.tmr0(verilog) of itmr_d(tmr_d)
Warning: Found 30 combinational loops!
         Each loop is reported with an instance in the loop
         and nets connected to that instance.
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net fsm_dly_1[0]
1) instance work.decoder(verilog)-fsm_dly_1[0], output net "fsm_dly_1[0]" in work.decoder(verilog)
    input nets to instance:
        net "fsm_dly_2[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net fsm_dly_1[1]
2) instance work.decoder(verilog)-fsm_dly_1[2:1], output net "fsm_dly_1[1]" in work.decoder(verilog)
    input nets to instance:
        net "fsm_dly_2[1]" in work.decoder(verilog)
        net "fsm_dly_2[2]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net fsm_dly_1[2]
3) instance work.decoder(verilog)-fsm_dly_1[2:1], output net "fsm_dly_1[2]" in work.decoder(verilog)
    input nets to instance:
        net "fsm_dly_2[1]" in work.decoder(verilog)
        net "fsm_dly_2[2]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net ext_ctl_1[0]
4) instance work.decoder(verilog)-ext_ctl_1[0], output net "ext_ctl_1[0]" in work.decoder(verilog)
    input nets to instance:
        net "ext_ctl_2[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_23" in work.decoder(verilog)
        net "un1_ins_i_20" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net ext_ctl_1[1]
5) instance work.decoder(verilog)-ext_ctl_1[1], output net "ext_ctl_1[1]" in work.decoder(verilog)
    input nets to instance:
        net "ext_ctl_2[1]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net ext_ctl_1[2]
6) instance work.decoder(verilog)-ext_ctl_1[2], output net "ext_ctl_1[2]" in work.decoder(verilog)
    input nets to instance:
        net "ext_ctl_2[2]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net rd_sel_1[0]
7) instance work.decoder(verilog)-rd_sel_1[0], output net "rd_sel_1[0]" in work.decoder(verilog)
    input nets to instance:
        net "rd_sel_2[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net rd_sel_1[1]
8) instance work.decoder(verilog)-rd_sel_1[1], output net "rd_sel_1[1]" in work.decoder(verilog)
    input nets to instance:
        net "rd_sel_2[1]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_22" in work.decoder(verilog)
        net "fsm_dly373" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net cmp_ctl_1[0]
9) instance work.decoder(verilog)-cmp_ctl_1[0], output net "cmp_ctl_1[0]" in work.decoder(verilog)
    input nets to instance:
        net "cmp_ctl_2[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net cmp_ctl_1[1]
10) instance work.decoder(verilog)-cmp_ctl_1[1], output net "cmp_ctl_1[1]" in work.decoder(verilog)
    input nets to instance:
        net "cmp_ctl_2[1]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net cmp_ctl_1[2]
11) instance work.decoder(verilog)-cmp_ctl_1[2], output net "cmp_ctl_1[2]" in work.decoder(verilog)
    input nets to instance:
        net "cmp_ctl_2[2]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net pc_gen_ctl_1[0]
12) instance work.decoder(verilog)-pc_gen_ctl_1[0], output net "pc_gen_ctl_1[0]" in work.decoder(verilog)
    input nets to instance:
        net "pc_gen_ctl_2[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_23" in work.decoder(verilog)
        net "un1_ins_i_20" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net pc_gen_ctl_1[1]
13) instance work.decoder(verilog)-pc_gen_ctl_1[1], output net "pc_gen_ctl_1[1]" in work.decoder(verilog)
    input nets to instance:
        net "pc_gen_ctl_2[1]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net pc_gen_ctl_1[2]
14) instance work.decoder(verilog)-pc_gen_ctl_1[2], output net "pc_gen_ctl_1[2]" in work.decoder(verilog)
    input nets to instance:
        net "pc_gen_ctl_2[2]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_23" in work.decoder(verilog)
        net "un1_ins_i_20" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net muxa_ctl_1[0]
15) instance work.decoder(verilog)-muxa_ctl_1[0], output net "muxa_ctl_1[0]" in work.decoder(verilog)
    input nets to instance:
        net "muxa_ctl_2[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net muxa_ctl_1[1]
16) instance work.decoder(verilog)-muxa_ctl_1[1], output net "muxa_ctl_1[1]" in work.decoder(verilog)
    input nets to instance:
        net "muxa_ctl_2[1]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_23" in work.decoder(verilog)
        net "un1_ins_i_20" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net muxb_ctl_1[0]
17) instance work.decoder(verilog)-muxb_ctl_1[0], output net "muxb_ctl_1[0]" in work.decoder(verilog)
    input nets to instance:
        net "muxb_ctl_2[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net muxb_ctl_1[1]
18) instance work.decoder(verilog)-muxb_ctl_1[1], output net "muxb_ctl_1[1]" in work.decoder(verilog)
    input nets to instance:
        net "muxb_ctl_2[1]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_23" in work.decoder(verilog)
        net "un1_ins_i_20" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net alu_func_1[0]
19) instance work.decoder(verilog)-alu_func_1[0], output net "alu_func_1[0]" in work.decoder(verilog)
    input nets to instance:
        net "alu_func_2[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net alu_func_1[1]
20) instance work.decoder(verilog)-alu_func_1[1], output net "alu_func_1[1]" in work.decoder(verilog)
    input nets to instance:
        net "alu_func_2[1]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net alu_func_1[2]
21) instance work.decoder(verilog)-alu_func_1[2], output net "alu_func_1[2]" in work.decoder(verilog)
    input nets to instance:
        net "alu_func_2[2]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_23" in work.decoder(verilog)
        net "un1_ins_i_20" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net alu_func_1[3]
22) instance work.decoder(verilog)-alu_func_1[3], output net "alu_func_1[3]" in work.decoder(verilog)
    input nets to instance:
        net "alu_func_2[3]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_23" in work.decoder(verilog)
        net "un1_ins_i_20" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net alu_func_1[4]
23) instance work.decoder(verilog)-alu_func_1[4], output net "alu_func_1[4]" in work.decoder(verilog)
    input nets to instance:
        net "alu_func_2[4]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net dmem_ctl_1[0]
24) instance work.decoder(verilog)-dmem_ctl_1[0], output net "dmem_ctl_1[0]" in work.decoder(verilog)
    input nets to instance:
        net "dmem_ctl_2[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_23" in work.decoder(verilog)
        net "un1_ins_i_20" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net dmem_ctl_1[1]
25) instance work.decoder(verilog)-dmem_ctl_1[1], output net "dmem_ctl_1[1]" in work.decoder(verilog)
    input nets to instance:
        net "dmem_ctl_2[1]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_22" in work.decoder(verilog)
        net "fsm_dly373" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net dmem_ctl_1[2]
26) instance work.decoder(verilog)-dmem_ctl_1[2], output net "dmem_ctl_1[2]" in work.decoder(verilog)
    input nets to instance:
        net "dmem_ctl_2[2]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_24" in work.decoder(verilog)
        net "un1_ins_i_15" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net dmem_ctl_1[3]
27) instance work.decoder(verilog)-dmem_ctl_1[3], output net "dmem_ctl_1[3]" in work.decoder(verilog)
    input nets to instance:
        net "dmem_ctl_2[3]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net alu_we[0]
28) instance work.decoder(verilog)-alu_we[0], output net "alu_we[0]" in work.decoder(verilog)
    input nets to instance:
        net "alu_we_1[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net wb_mux[0]
29) instance work.decoder(verilog)-wb_mux[0], output net "wb_mux[0]" in work.decoder(verilog)
    input nets to instance:
        net "wb_mux_1[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net wb_we[0]
30) instance work.decoder(verilog)-wb_we[0], output net "wb_we[0]" in work.decoder(verilog)
    input nets to instance:
        net "wb_we_1[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
End of loops
RTL optimization done.
Warning: Found 30 combinational loops!
         Each loop is reported with an instance in the loop
         and nets connected to that instance.
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net fsm_dly_1[0]
1) instance work.decoder(verilog)-fsm_dly_1[0], output net "fsm_dly_1[0]" in work.decoder(verilog)
    input nets to instance:
        net "fsm_dly_2[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net fsm_dly_1[1]
2) instance work.decoder(verilog)-fsm_dly_1[2:1], output net "fsm_dly_1[1]" in work.decoder(verilog)
    input nets to instance:
        net "fsm_dly_2[1]" in work.decoder(verilog)
        net "fsm_dly_2[2]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net fsm_dly_1[2]
3) instance work.decoder(verilog)-fsm_dly_1[2:1], output net "fsm_dly_1[2]" in work.decoder(verilog)
    input nets to instance:
        net "fsm_dly_2[1]" in work.decoder(verilog)
        net "fsm_dly_2[2]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net wb_mux_1[0]
4) instance work.decoder(verilog)-wb_mux_1[0], output net "wb_mux_1[0]" in work.decoder(verilog)
    input nets to instance:
        net "un1_alu_we_3_sqmuxa_4" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "un1_alu_we_3_sqmuxa" in work.decoder(verilog)
        net "wb_mux[0]" in work.decoder(verilog)
        net "un1_fsm_dly365" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net wb_we_1[0]
5) instance work.decoder(verilog)-wb_we_1[0], output net "wb_we_1[0]" in work.decoder(verilog)
    input nets to instance:
        net "un1_alu_we_3_sqmuxa_3" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "un1_alu_we_3_sqmuxa" in work.decoder(verilog)
        net "wb_we[0]" in work.decoder(verilog)
        net "un1_fsm_dly362" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net alu_func_2[0]
6) instance work.decoder(verilog)-alu_func_2[4:0], output net "alu_func_2[0]" in work.decoder(verilog)
    input nets to instance:
        net "alu_func_0_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_1_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_2_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_3_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_4_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_5_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_6_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_7_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_8_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_9_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_10_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_11_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_12_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_13_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_14_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_15_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_16_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_17_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_18_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_19_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_20_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_21_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_22_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_23_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_24_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_25_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_26_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_27_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_28_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_0_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_1_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_2_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_3_sqmuxa" in work.decoder(verilog)
        net "alu_func_1[0]" in work.decoder(verilog)
        net "alu_func_1[1]" in work.decoder(verilog)
        net "alu_func_1[2]" in work.decoder(verilog)
        net "alu_func_1[3]" in work.decoder(verilog)
        net "alu_func_1[4]" in work.decoder(verilog)
        net "alu_we_4_sqmuxa" in work.decoder(verilog)
        net "alu_func_1[0]" in work.decoder(verilog)
        net "alu_func_1[1]" in work.decoder(verilog)
        net "alu_func_1[2]" in work.decoder(verilog)
        net "alu_func_1[3]" in work.decoder(verilog)
        net "alu_func_1[4]" in work.decoder(verilog)
        net "fsm_dly350" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly351" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly352" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly353" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly354" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly355" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly356" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly357" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly358" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly359" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly360" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly361" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly362" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly363" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
        net "alu_func_1[0]" in work.decoder(verilog)
        net "alu_func_1[1]" in work.decoder(verilog)
        net "alu_func_1[2]" in work.decoder(verilog)
        net "alu_func_1[3]" in work.decoder(verilog)
        net "alu_func_1[4]" in work.decoder(verilog)
        net "fsm_dly365" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly366" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly367" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly368" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly369" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly370" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net alu_func_2[1]
7) instance work.decoder(verilog)-alu_func_2[4:0], output net "alu_func_2[1]" in work.decoder(verilog)
    input nets to instance:
        net "alu_func_0_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_1_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_2_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_3_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_4_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_5_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_6_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_7_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_8_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_9_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_10_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_11_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_12_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_13_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_14_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_15_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_16_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_17_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_18_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_19_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_20_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_21_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_22_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_23_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_24_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_25_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_26_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_27_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_28_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_0_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_1_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_2_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_3_sqmuxa" in work.decoder(verilog)
        net "alu_func_1[0]" in work.decoder(verilog)
        net "alu_func_1[1]" in work.decoder(verilog)
        net "alu_func_1[2]" in work.decoder(verilog)
        net "alu_func_1[3]" in work.decoder(verilog)
        net "alu_func_1[4]" in work.decoder(verilog)
        net "alu_we_4_sqmuxa" in work.decoder(verilog)
        net "alu_func_1[0]" in work.decoder(verilog)
        net "alu_func_1[1]" in work.decoder(verilog)
        net "alu_func_1[2]" in work.decoder(verilog)
        net "alu_func_1[3]" in work.decoder(verilog)
        net "alu_func_1[4]" in work.decoder(verilog)
        net "fsm_dly350" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly351" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly352" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly353" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly354" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly355" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly356" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly357" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly358" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly359" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly360" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly361" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly362" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly363" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
        net "alu_func_1[0]" in work.decoder(verilog)
        net "alu_func_1[1]" in work.decoder(verilog)
        net "alu_func_1[2]" in work.decoder(verilog)
        net "alu_func_1[3]" in work.decoder(verilog)
        net "alu_func_1[4]" in work.decoder(verilog)
        net "fsm_dly365" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly366" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly367" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly368" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly369" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly370" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net alu_func_2[2]
8) instance work.decoder(verilog)-alu_func_2[4:0], output net "alu_func_2[2]" in work.decoder(verilog)
    input nets to instance:
        net "alu_func_0_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_1_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_2_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_3_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_4_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_5_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_6_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_7_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_8_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_9_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_10_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_11_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_12_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_13_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_14_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_15_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_16_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_17_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_18_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_19_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_20_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_21_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_22_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_23_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_24_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_25_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_26_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_27_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_28_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_0_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_1_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_2_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_3_sqmuxa" in work.decoder(verilog)
        net "alu_func_1[0]" in work.decoder(verilog)
        net "alu_func_1[1]" in work.decoder(verilog)
        net "alu_func_1[2]" in work.decoder(verilog)
        net "alu_func_1[3]" in work.decoder(verilog)
        net "alu_func_1[4]" in work.decoder(verilog)
        net "alu_we_4_sqmuxa" in work.decoder(verilog)
        net "alu_func_1[0]" in work.decoder(verilog)
        net "alu_func_1[1]" in work.decoder(verilog)
        net "alu_func_1[2]" in work.decoder(verilog)
        net "alu_func_1[3]" in work.decoder(verilog)
        net "alu_func_1[4]" in work.decoder(verilog)
        net "fsm_dly350" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly351" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly352" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly353" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly354" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly355" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly356" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly357" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly358" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly359" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly360" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly361" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly362" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly363" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
        net "alu_func_1[0]" in work.decoder(verilog)
        net "alu_func_1[1]" in work.decoder(verilog)
        net "alu_func_1[2]" in work.decoder(verilog)
        net "alu_func_1[3]" in work.decoder(verilog)
        net "alu_func_1[4]" in work.decoder(verilog)
        net "fsm_dly365" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly366" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly367" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly368" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly369" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly370" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net alu_func_2[3]
9) instance work.decoder(verilog)-alu_func_2[4:0], output net "alu_func_2[3]" in work.decoder(verilog)
    input nets to instance:
        net "alu_func_0_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_1_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_2_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_3_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_4_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_5_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_6_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_7_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_8_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_9_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_10_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_11_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_12_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_13_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_14_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_15_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_16_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_17_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_18_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_19_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_20_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_21_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_22_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_23_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_24_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_25_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_26_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_27_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_28_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_0_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_1_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_2_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_3_sqmuxa" in work.decoder(verilog)
        net "alu_func_1[0]" in work.decoder(verilog)
        net "alu_func_1[1]" in work.decoder(verilog)
        net "alu_func_1[2]" in work.decoder(verilog)
        net "alu_func_1[3]" in work.decoder(verilog)
        net "alu_func_1[4]" in work.decoder(verilog)
        net "alu_we_4_sqmuxa" in work.decoder(verilog)
        net "alu_func_1[0]" in work.decoder(verilog)
        net "alu_func_1[1]" in work.decoder(verilog)
        net "alu_func_1[2]" in work.decoder(verilog)
        net "alu_func_1[3]" in work.decoder(verilog)
        net "alu_func_1[4]" in work.decoder(verilog)
        net "fsm_dly350" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly351" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly352" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly353" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly354" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly355" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly356" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly357" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly358" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly359" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly360" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly361" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly362" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly363" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
        net "alu_func_1[0]" in work.decoder(verilog)
        net "alu_func_1[1]" in work.decoder(verilog)
        net "alu_func_1[2]" in work.decoder(verilog)
        net "alu_func_1[3]" in work.decoder(verilog)
        net "alu_func_1[4]" in work.decoder(verilog)
        net "fsm_dly365" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly366" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly367" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly368" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly369" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly370" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net alu_func_2[4]
10) instance work.decoder(verilog)-alu_func_2[4:0], output net "alu_func_2[4]" in work.decoder(verilog)
    input nets to instance:
        net "alu_func_0_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_1_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_2_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_3_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_4_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_5_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_6_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_7_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_8_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_9_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_10_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_11_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_12_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_13_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_14_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_15_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_16_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_17_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_18_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_19_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_20_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_21_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_22_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_23_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_24_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_25_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_26_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_27_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_28_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_0_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_1_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_2_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_3_sqmuxa" in work.decoder(verilog)
        net "alu_func_1[0]" in work.decoder(verilog)
        net "alu_func_1[1]" in work.decoder(verilog)
        net "alu_func_1[2]" in work.decoder(verilog)
        net "alu_func_1[3]" in work.decoder(verilog)
        net "alu_func_1[4]" in work.decoder(verilog)
        net "alu_we_4_sqmuxa" in work.decoder(verilog)
        net "alu_func_1[0]" in work.decoder(verilog)
        net "alu_func_1[1]" in work.decoder(verilog)
        net "alu_func_1[2]" in work.decoder(verilog)
        net "alu_func_1[3]" in work.decoder(verilog)
        net "alu_func_1[4]" in work.decoder(verilog)
        net "fsm_dly350" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly351" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly352" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly353" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly354" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly355" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly356" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly357" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly358" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly359" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly360" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly361" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly362" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly363" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
        net "alu_func_1[0]" in work.decoder(verilog)
        net "alu_func_1[1]" in work.decoder(verilog)
        net "alu_func_1[2]" in work.decoder(verilog)
        net "alu_func_1[3]" in work.decoder(verilog)
        net "alu_func_1[4]" in work.decoder(verilog)
        net "fsm_dly365" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly366" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly367" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly368" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly369" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly370" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net alu_we_1[0]
11) instance work.decoder(verilog)-alu_we_1[0], output net "alu_we_1[0]" in work.decoder(verilog)
    input nets to instance:
        net "alu_func_0_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_1_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_2_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_3_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_4_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_5_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_6_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_7_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_8_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_9_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_10_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_11_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_12_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_13_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_14_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_15_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_16_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_17_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_18_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_19_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_20_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_21_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_22_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_23_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_24_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_25_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_26_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_27_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_28_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_0_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_1_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_2_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_3_sqmuxa" in work.decoder(verilog)
        net "alu_we[0]" in work.decoder(verilog)
        net "alu_we_4_sqmuxa" in work.decoder(verilog)
        net "alu_we[0]" in work.decoder(verilog)
        net "fsm_dly350" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly351" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly352" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly353" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly354" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly355" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly356" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly357" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly358" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly359" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly360" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly361" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly362" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly363" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
        net "alu_we[0]" in work.decoder(verilog)
        net "fsm_dly365" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly366" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly367" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly368" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly369" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly370" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net ext_ctl_2[0]
12) instance work.decoder(verilog)-ext_ctl_2[2:0], output net "ext_ctl_2[0]" in work.decoder(verilog)
    input nets to instance:
        net "alu_func_0_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_1_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_2_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_3_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_4_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_5_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_6_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_7_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_8_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_9_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_10_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_11_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_12_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_13_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_14_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_15_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_16_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_17_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_18_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_19_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_20_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_21_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_22_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_23_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_24_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_25_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_26_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_27_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_28_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_0_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_we_1_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_we_2_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_3_sqmuxa" in work.decoder(verilog)
        net "ext_ctl_1[0]" in work.decoder(verilog)
        net "ext_ctl_1[1]" in work.decoder(verilog)
        net "ext_ctl_1[2]" in work.decoder(verilog)
        net "alu_we_4_sqmuxa" in work.decoder(verilog)
        net "ext_ctl_1[0]" in work.decoder(verilog)
        net "ext_ctl_1[1]" in work.decoder(verilog)
        net "ext_ctl_1[2]" in work.decoder(verilog)
        net "fsm_dly350" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly351" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly352" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly353" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly354" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly355" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly356" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly357" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly358" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly359" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly360" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly361" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly362" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly363" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
        net "ext_ctl_1[0]" in work.decoder(verilog)
        net "ext_ctl_1[1]" in work.decoder(verilog)
        net "ext_ctl_1[2]" in work.decoder(verilog)
        net "fsm_dly365" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly366" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly367" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly368" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly369" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly370" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net ext_ctl_2[1]
13) instance work.decoder(verilog)-ext_ctl_2[2:0], output net "ext_ctl_2[1]" in work.decoder(verilog)
    input nets to instance:
        net "alu_func_0_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_1_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_2_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_3_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_4_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_5_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_6_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_7_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_8_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_9_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_10_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_11_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_12_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_13_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_14_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_15_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_16_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_17_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_18_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_19_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_20_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_21_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_22_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_23_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_24_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_25_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_26_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_27_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_28_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_0_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_we_1_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_we_2_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_3_sqmuxa" in work.decoder(verilog)
        net "ext_ctl_1[0]" in work.decoder(verilog)
        net "ext_ctl_1[1]" in work.decoder(verilog)
        net "ext_ctl_1[2]" in work.decoder(verilog)
        net "alu_we_4_sqmuxa" in work.decoder(verilog)
        net "ext_ctl_1[0]" in work.decoder(verilog)
        net "ext_ctl_1[1]" in work.decoder(verilog)
        net "ext_ctl_1[2]" in work.decoder(verilog)
        net "fsm_dly350" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly351" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly352" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly353" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly354" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly355" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly356" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly357" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly358" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly359" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly360" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly361" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly362" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly363" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
        net "ext_ctl_1[0]" in work.decoder(verilog)
        net "ext_ctl_1[1]" in work.decoder(verilog)
        net "ext_ctl_1[2]" in work.decoder(verilog)
        net "fsm_dly365" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly366" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly367" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly368" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly369" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly370" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net ext_ctl_2[2]
14) instance work.decoder(verilog)-ext_ctl_2[2:0], output net "ext_ctl_2[2]" in work.decoder(verilog)
    input nets to instance:
        net "alu_func_0_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_1_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_2_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_3_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_4_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_5_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_6_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_7_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_8_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_9_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_10_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_11_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_12_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_13_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_14_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_15_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_16_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_17_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_18_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_19_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_20_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_21_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_22_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_23_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_24_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_25_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_26_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_27_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_28_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_0_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_we_1_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_we_2_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_3_sqmuxa" in work.decoder(verilog)
        net "ext_ctl_1[0]" in work.decoder(verilog)
        net "ext_ctl_1[1]" in work.decoder(verilog)
        net "ext_ctl_1[2]" in work.decoder(verilog)
        net "alu_we_4_sqmuxa" in work.decoder(verilog)
        net "ext_ctl_1[0]" in work.decoder(verilog)
        net "ext_ctl_1[1]" in work.decoder(verilog)
        net "ext_ctl_1[2]" in work.decoder(verilog)
        net "fsm_dly350" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly351" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly352" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly353" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly354" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly355" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly356" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly357" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly358" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly359" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly360" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly361" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly362" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly363" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
        net "ext_ctl_1[0]" in work.decoder(verilog)
        net "ext_ctl_1[1]" in work.decoder(verilog)
        net "ext_ctl_1[2]" in work.decoder(verilog)
        net "fsm_dly365" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly366" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly367" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly368" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly369" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly370" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net muxa_ctl_2[0]
15) instance work.decoder(verilog)-muxa_ctl_2[1:0], output net "muxa_ctl_2[0]" in work.decoder(verilog)
    input nets to instance:
        net "alu_func_0_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_1_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_2_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_3_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_4_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_5_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_6_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_7_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_8_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_9_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_10_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_11_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_12_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_13_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_14_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_15_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_16_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_17_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_18_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_19_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_20_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_21_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_22_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_23_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_24_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_25_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_26_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_27_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_28_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_0_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_1_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_2_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_3_sqmuxa" in work.decoder(verilog)
        net "muxa_ctl_1[0]" in work.decoder(verilog)
        net "muxa_ctl_1[1]" in work.decoder(verilog)
        net "alu_we_4_sqmuxa" in work.decoder(verilog)
        net "muxa_ctl_1[0]" in work.decoder(verilog)
        net "muxa_ctl_1[1]" in work.decoder(verilog)
        net "fsm_dly350" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly351" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly352" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly353" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly354" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly355" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly356" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly357" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly358" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly359" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly360" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly361" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly362" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly363" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
        net "muxa_ctl_1[0]" in work.decoder(verilog)
        net "muxa_ctl_1[1]" in work.decoder(verilog)
        net "fsm_dly365" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly366" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly367" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly368" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly369" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly370" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net muxa_ctl_2[1]
16) instance work.decoder(verilog)-muxa_ctl_2[1:0], output net "muxa_ctl_2[1]" in work.decoder(verilog)
    input nets to instance:
        net "alu_func_0_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_1_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_2_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_3_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_4_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_5_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_6_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_7_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_8_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_9_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_10_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_11_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_12_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_13_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_14_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_15_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_16_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_17_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_18_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_19_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_20_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_21_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_22_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_23_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_24_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_25_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_26_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_27_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_28_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_0_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_1_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_2_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_3_sqmuxa" in work.decoder(verilog)
        net "muxa_ctl_1[0]" in work.decoder(verilog)
        net "muxa_ctl_1[1]" in work.decoder(verilog)
        net "alu_we_4_sqmuxa" in work.decoder(verilog)
        net "muxa_ctl_1[0]" in work.decoder(verilog)
        net "muxa_ctl_1[1]" in work.decoder(verilog)
        net "fsm_dly350" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly351" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly352" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly353" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly354" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly355" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly356" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly357" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly358" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly359" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly360" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly361" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly362" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly363" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
        net "muxa_ctl_1[0]" in work.decoder(verilog)
        net "muxa_ctl_1[1]" in work.decoder(verilog)
        net "fsm_dly365" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly366" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly367" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly368" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly369" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly370" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net muxb_ctl_2[0]
17) instance work.decoder(verilog)-muxb_ctl_2[1:0], output net "muxb_ctl_2[0]" in work.decoder(verilog)
    input nets to instance:
        net "alu_func_0_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_1_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_2_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_3_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_4_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_5_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_6_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_7_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_8_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_9_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_10_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_11_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_12_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_13_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_14_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_15_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_16_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_17_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_18_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_19_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_20_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_21_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_22_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_23_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_24_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_25_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_26_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_27_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_28_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_0_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_1_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_2_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_3_sqmuxa" in work.decoder(verilog)
        net "muxb_ctl_1[0]" in work.decoder(verilog)
        net "muxb_ctl_1[1]" in work.decoder(verilog)
        net "alu_we_4_sqmuxa" in work.decoder(verilog)
        net "muxb_ctl_1[0]" in work.decoder(verilog)
        net "muxb_ctl_1[1]" in work.decoder(verilog)
        net "fsm_dly350" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly351" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly352" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly353" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly354" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly355" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly356" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly357" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly358" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly359" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly360" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly361" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly362" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly363" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
        net "muxb_ctl_1[0]" in work.decoder(verilog)
        net "muxb_ctl_1[1]" in work.decoder(verilog)
        net "fsm_dly365" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly366" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly367" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly368" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly369" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly370" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net muxb_ctl_2[1]
18) instance work.decoder(verilog)-muxb_ctl_2[1:0], output net "muxb_ctl_2[1]" in work.decoder(verilog)
    input nets to instance:
        net "alu_func_0_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_1_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_2_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_3_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_4_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_5_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_6_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_7_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_8_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_9_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_10_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_11_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_12_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_13_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_14_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_15_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_16_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_17_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_18_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_19_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_20_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_21_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_22_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_23_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_24_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_25_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_26_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_27_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_28_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_0_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_1_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_2_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_3_sqmuxa" in work.decoder(verilog)
        net "muxb_ctl_1[0]" in work.decoder(verilog)
        net "muxb_ctl_1[1]" in work.decoder(verilog)
        net "alu_we_4_sqmuxa" in work.decoder(verilog)
        net "muxb_ctl_1[0]" in work.decoder(verilog)
        net "muxb_ctl_1[1]" in work.decoder(verilog)
        net "fsm_dly350" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly351" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly352" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly353" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly354" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly355" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly356" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly357" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly358" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly359" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly360" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly361" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly362" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly363" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
        net "muxb_ctl_1[0]" in work.decoder(verilog)
        net "muxb_ctl_1[1]" in work.decoder(verilog)
        net "fsm_dly365" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly366" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly367" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly368" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly369" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly370" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net pc_gen_ctl_2[0]
19) instance work.decoder(verilog)-pc_gen_ctl_2[2:0], output net "pc_gen_ctl_2[0]" in work.decoder(verilog)
    input nets to instance:
        net "alu_func_0_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_1_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_2_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_3_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_4_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_5_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_6_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_7_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_8_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_9_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_10_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_11_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_12_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_13_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_14_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_15_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_16_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_17_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_18_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_19_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_20_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_21_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_22_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_23_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_24_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_25_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_26_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_27_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_28_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_0_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_we_1_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_we_2_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_3_sqmuxa" in work.decoder(verilog)
        net "pc_gen_ctl_1[0]" in work.decoder(verilog)
        net "pc_gen_ctl_1[1]" in work.decoder(verilog)
        net "pc_gen_ctl_1[2]" in work.decoder(verilog)
        net "alu_we_4_sqmuxa" in work.decoder(verilog)
        net "pc_gen_ctl_1[0]" in work.decoder(verilog)
        net "pc_gen_ctl_1[1]" in work.decoder(verilog)
        net "pc_gen_ctl_1[2]" in work.decoder(verilog)
        net "fsm_dly350" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly351" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly352" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly353" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly354" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly355" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly356" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly357" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly358" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly359" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly360" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly361" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly362" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly363" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
        net "pc_gen_ctl_1[0]" in work.decoder(verilog)
        net "pc_gen_ctl_1[1]" in work.decoder(verilog)
        net "pc_gen_ctl_1[2]" in work.decoder(verilog)
        net "fsm_dly365" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly366" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly367" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly368" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly369" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly370" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net pc_gen_ctl_2[1]
20) instance work.decoder(verilog)-pc_gen_ctl_2[2:0], output net "pc_gen_ctl_2[1]" in work.decoder(verilog)
    input nets to instance:
        net "alu_func_0_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_1_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_2_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_3_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_4_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_5_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_6_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_7_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_8_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_9_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_10_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_11_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_12_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_13_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_14_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_15_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_16_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_17_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_18_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_19_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_20_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_21_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_22_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_23_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_24_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_25_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_26_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_27_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_28_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_0_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_we_1_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_we_2_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_3_sqmuxa" in work.decoder(verilog)
        net "pc_gen_ctl_1[0]" in work.decoder(verilog)
        net "pc_gen_ctl_1[1]" in work.decoder(verilog)
        net "pc_gen_ctl_1[2]" in work.decoder(verilog)
        net "alu_we_4_sqmuxa" in work.decoder(verilog)
        net "pc_gen_ctl_1[0]" in work.decoder(verilog)
        net "pc_gen_ctl_1[1]" in work.decoder(verilog)
        net "pc_gen_ctl_1[2]" in work.decoder(verilog)
        net "fsm_dly350" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly351" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly352" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly353" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly354" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly355" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly356" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly357" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly358" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly359" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly360" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly361" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly362" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly363" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
        net "pc_gen_ctl_1[0]" in work.decoder(verilog)
        net "pc_gen_ctl_1[1]" in work.decoder(verilog)
        net "pc_gen_ctl_1[2]" in work.decoder(verilog)
        net "fsm_dly365" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly366" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly367" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly368" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly369" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly370" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net pc_gen_ctl_2[2]
21) instance work.decoder(verilog)-pc_gen_ctl_2[2:0], output net "pc_gen_ctl_2[2]" in work.decoder(verilog)
    input nets to instance:
        net "alu_func_0_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_1_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_2_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_3_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_4_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_5_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_6_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_7_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_8_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_9_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_10_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_11_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_12_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_13_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_14_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_15_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_16_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_17_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_18_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_19_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_20_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_21_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_22_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_23_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_24_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_25_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_26_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_27_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_func_28_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_0_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_we_1_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_we_2_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_3_sqmuxa" in work.decoder(verilog)
        net "pc_gen_ctl_1[0]" in work.decoder(verilog)
        net "pc_gen_ctl_1[1]" in work.decoder(verilog)
        net "pc_gen_ctl_1[2]" in work.decoder(verilog)
        net "alu_we_4_sqmuxa" in work.decoder(verilog)
        net "pc_gen_ctl_1[0]" in work.decoder(verilog)
        net "pc_gen_ctl_1[1]" in work.decoder(verilog)
        net "pc_gen_ctl_1[2]" in work.decoder(verilog)
        net "fsm_dly350" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly351" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly352" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly353" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly354" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly355" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly356" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly357" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly358" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly359" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly360" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly361" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly362" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly363" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
        net "pc_gen_ctl_1[0]" in work.decoder(verilog)
        net "pc_gen_ctl_1[1]" in work.decoder(verilog)
        net "pc_gen_ctl_1[2]" in work.decoder(verilog)
        net "fsm_dly365" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly366" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly367" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly368" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly369" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly370" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net rd_sel_2[0]
22) instance work.decoder(verilog)-rd_sel_2[1:0], output net "rd_sel_2[0]" in work.decoder(verilog)
    input nets to instance:
        net "alu_func_0_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_1_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_2_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_3_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_4_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_5_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_6_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_7_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_8_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_9_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_10_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_11_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_12_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_13_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_14_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_15_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_16_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_17_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_18_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_19_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_20_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_21_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_22_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_23_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_24_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_25_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_26_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_27_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_28_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_0_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_1_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_2_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_3_sqmuxa" in work.decoder(verilog)
        net "rd_sel_1[0]" in work.decoder(verilog)
        net "rd_sel_1[1]" in work.decoder(verilog)
        net "alu_we_4_sqmuxa" in work.decoder(verilog)
        net "rd_sel_1[0]" in work.decoder(verilog)
        net "rd_sel_1[1]" in work.decoder(verilog)
        net "fsm_dly350" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly351" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly352" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly353" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly354" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly355" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly356" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly357" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly358" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly359" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly360" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly361" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly362" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly363" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
        net "rd_sel_1[0]" in work.decoder(verilog)
        net "rd_sel_1[1]" in work.decoder(verilog)
        net "fsm_dly365" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly366" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly367" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly368" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly369" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly370" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net rd_sel_2[1]
23) instance work.decoder(verilog)-rd_sel_2[1:0], output net "rd_sel_2[1]" in work.decoder(verilog)
    input nets to instance:
        net "alu_func_0_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_1_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_2_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_3_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_4_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_5_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_6_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_7_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_8_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_9_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_10_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_11_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_12_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_13_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_14_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_15_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_16_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_17_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_18_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_19_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_20_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_21_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_22_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_23_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_24_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_25_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_26_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_27_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_28_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_0_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_1_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_2_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_3_sqmuxa" in work.decoder(verilog)
        net "rd_sel_1[0]" in work.decoder(verilog)
        net "rd_sel_1[1]" in work.decoder(verilog)
        net "alu_we_4_sqmuxa" in work.decoder(verilog)
        net "rd_sel_1[0]" in work.decoder(verilog)
        net "rd_sel_1[1]" in work.decoder(verilog)
        net "fsm_dly350" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly351" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly352" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly353" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly354" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly355" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly356" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly357" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly358" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly359" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly360" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly361" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly362" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly363" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
        net "rd_sel_1[0]" in work.decoder(verilog)
        net "rd_sel_1[1]" in work.decoder(verilog)
        net "fsm_dly365" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly366" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly367" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly368" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly369" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly370" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net cmp_ctl_2[0]
24) instance work.decoder(verilog)-cmp_ctl_2[2:0], output net "cmp_ctl_2[0]" in work.decoder(verilog)
    input nets to instance:
        net "un1_fsm_dly352_1" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_0_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_we_1_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "un1_alu_we_3_sqmuxa" in work.decoder(verilog)
        net "cmp_ctl_1[0]" in work.decoder(verilog)
        net "cmp_ctl_1[1]" in work.decoder(verilog)
        net "cmp_ctl_1[2]" in work.decoder(verilog)
        net "fsm_dly352" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly353" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly354" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly355" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net cmp_ctl_2[1]
25) instance work.decoder(verilog)-cmp_ctl_2[2:0], output net "cmp_ctl_2[1]" in work.decoder(verilog)
    input nets to instance:
        net "un1_fsm_dly352_1" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_0_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_we_1_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "un1_alu_we_3_sqmuxa" in work.decoder(verilog)
        net "cmp_ctl_1[0]" in work.decoder(verilog)
        net "cmp_ctl_1[1]" in work.decoder(verilog)
        net "cmp_ctl_1[2]" in work.decoder(verilog)
        net "fsm_dly352" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly353" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly354" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly355" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net cmp_ctl_2[2]
26) instance work.decoder(verilog)-cmp_ctl_2[2:0], output net "cmp_ctl_2[2]" in work.decoder(verilog)
    input nets to instance:
        net "un1_fsm_dly352_1" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_0_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_we_1_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "un1_alu_we_3_sqmuxa" in work.decoder(verilog)
        net "cmp_ctl_1[0]" in work.decoder(verilog)
        net "cmp_ctl_1[1]" in work.decoder(verilog)
        net "cmp_ctl_1[2]" in work.decoder(verilog)
        net "fsm_dly352" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly353" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly354" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly355" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net dmem_ctl_2[0]
27) instance work.decoder(verilog)-dmem_ctl_2[3:0], output net "dmem_ctl_2[0]" in work.decoder(verilog)
    input nets to instance:
        net "un1_fsm_dly365_2" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "un1_alu_we_3_sqmuxa" in work.decoder(verilog)
        net "dmem_ctl_1[0]" in work.decoder(verilog)
        net "dmem_ctl_1[1]" in work.decoder(verilog)
        net "dmem_ctl_1[2]" in work.decoder(verilog)
        net "dmem_ctl_1[3]" in work.decoder(verilog)
        net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly365" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly366" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly368" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly369" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly370" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net dmem_ctl_2[1]
28) instance work.decoder(verilog)-dmem_ctl_2[3:0], output net "dmem_ctl_2[1]" in work.decoder(verilog)
    input nets to instance:
        net "un1_fsm_dly365_2" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "un1_alu_we_3_sqmuxa" in work.decoder(verilog)
        net "dmem_ctl_1[0]" in work.decoder(verilog)
        net "dmem_ctl_1[1]" in work.decoder(verilog)
        net "dmem_ctl_1[2]" in work.decoder(verilog)
        net "dmem_ctl_1[3]" in work.decoder(verilog)
        net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly365" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly366" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly368" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly369" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly370" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net dmem_ctl_2[2]
29) instance work.decoder(verilog)-dmem_ctl_2[3:0], output net "dmem_ctl_2[2]" in work.decoder(verilog)
    input nets to instance:
        net "un1_fsm_dly365_2" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "un1_alu_we_3_sqmuxa" in work.decoder(verilog)
        net "dmem_ctl_1[0]" in work.decoder(verilog)
        net "dmem_ctl_1[1]" in work.decoder(verilog)
        net "dmem_ctl_1[2]" in work.decoder(verilog)
        net "dmem_ctl_1[3]" in work.decoder(verilog)
        net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly365" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly366" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly368" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly369" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly370" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net dmem_ctl_2[3]
30) instance work.decoder(verilog)-dmem_ctl_2[3:0], output net "dmem_ctl_2[3]" in work.decoder(verilog)
    input nets to instance:
        net "un1_fsm_dly365_2" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "un1_alu_we_3_sqmuxa" in work.decoder(verilog)
        net "dmem_ctl_1[0]" in work.decoder(verilog)
        net "dmem_ctl_1[1]" in work.decoder(verilog)
        net "dmem_ctl_1[2]" in work.decoder(verilog)
        net "dmem_ctl_1[3]" in work.decoder(verilog)
        net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly365" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly366" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly368" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly369" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly370" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
End of loops
@W: BN132 :"e:\mips789\mips789\rtl\verilog\ulit.v":150:83:150:88|Removing sequential instance mips_core.alu_pass0.r32_o[0],  because it is equivalent to instance mips_core.MEM_CTL.dmem_ctl_post.byte_addr_o[0]
@W: BN132 :"e:\mips789\mips789\rtl\verilog\ulit.v":150:83:150:88|Removing sequential instance mips_core.alu_pass0.r32_o[1],  because it is equivalent to instance mips_core.MEM_CTL.dmem_ctl_post.byte_addr_o[1]
Encoding state machine work.ctl_FSM(verilog)-CurrState_Sreg0[8:0]
original code -> new code
   0000 -> 000000000
   0001 -> 000000011
   0010 -> 000000101
   0011 -> 000001001
   0100 -> 000010001
   0101 -> 000100001
   0110 -> 001000001
   0111 -> 010000001
   1000 -> 100000001
@W: FA140 :"e:\mips789\mips789\rtl\verilog\ctl_fsm.v":126:16:126:16|DFF work.ctl_FSM(verilog)-CurrState_Sreg0[5] is stuck at '0', removing ... 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\ctl_fsm.v":126:16:126:16|Removing sequential instance CurrState_Sreg0[5] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: MO127 :"e:\mips789\mips789\rtl\verilog\ctl_fsm.v":58:8:58:11|Sequential instance mips_core.iRF_stage.MIAN_FSM.iack_1 has been reduced to a combinational gate by constant propagation
@N:"e:\mips789\mips789\rtl\verilog\exec_stage.v":572:4:572:9|Found counter in view:work.muldiv_ff(verilog) inst count[5:0]
Warning: Found 30 combinational loops!
         Each loop is reported with an instance in the loop
         and nets connected to that instance.
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
1) instance fsm_dly_2[2:0] work.decoder(verilog)-fsm_dly_2[2:0], output net "fsm_dly_2[0]" in work.decoder(verilog)
    input nets to instance:
        net "alu_func_0_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_1_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_2_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_3_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_4_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_5_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_6_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_7_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_8_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_9_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_10_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_11_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_12_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_13_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_14_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_15_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_16_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_17_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_18_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_19_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_20_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_21_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_22_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_23_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_24_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_25_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_26_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_27_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_28_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_0_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_1_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_2_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_3_sqmuxa" in work.decoder(verilog)
        net "fsm_dly_1[0]" in work.decoder(verilog)
        net "fsm_dly_1[1]" in work.decoder(verilog)
        net "fsm_dly_1[2]" in work.decoder(verilog)
        net "alu_we_4_sqmuxa" in work.decoder(verilog)
        net "fsm_dly_1[0]" in work.decoder(verilog)
        net "fsm_dly_1[1]" in work.decoder(verilog)
        net "fsm_dly_1[2]" in work.decoder(verilog)
        net "fsm_dly350" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly351" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly352" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly353" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly354" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly355" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly356" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly357" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly358" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly359" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly360" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly361" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly362" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly363" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
        net "fsm_dly_1[0]" in work.decoder(verilog)
        net "fsm_dly_1[1]" in work.decoder(verilog)
        net "fsm_dly_1[2]" in work.decoder(verilog)
        net "fsm_dly365" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly366" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly367" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly368" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly369" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly370" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
2) instance fsm_dly_2[2:0] work.decoder(verilog)-fsm_dly_2[2:0], output net "fsm_dly_2[1]" in work.decoder(verilog)
    input nets to instance:
        net "alu_func_0_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_1_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_2_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_3_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_4_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_5_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_6_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_7_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_8_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_9_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_10_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_11_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_12_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_13_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_14_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_15_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_16_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_17_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_18_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_19_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_20_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_21_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_22_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_23_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_24_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_25_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_26_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_27_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_28_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_0_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_1_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_2_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_3_sqmuxa" in work.decoder(verilog)
        net "fsm_dly_1[0]" in work.decoder(verilog)
        net "fsm_dly_1[1]" in work.decoder(verilog)
        net "fsm_dly_1[2]" in work.decoder(verilog)
        net "alu_we_4_sqmuxa" in work.decoder(verilog)
        net "fsm_dly_1[0]" in work.decoder(verilog)
        net "fsm_dly_1[1]" in work.decoder(verilog)
        net "fsm_dly_1[2]" in work.decoder(verilog)
        net "fsm_dly350" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly351" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly352" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly353" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly354" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly355" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly356" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly357" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly358" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly359" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly360" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly361" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly362" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly363" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
        net "fsm_dly_1[0]" in work.decoder(verilog)
        net "fsm_dly_1[1]" in work.decoder(verilog)
        net "fsm_dly_1[2]" in work.decoder(verilog)
        net "fsm_dly365" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly366" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly367" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly368" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly369" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly370" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
3) instance fsm_dly_2[2:0] work.decoder(verilog)-fsm_dly_2[2:0], output net "fsm_dly_2[2]" in work.decoder(verilog)
    input nets to instance:
        net "alu_func_0_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_1_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_2_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_3_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_4_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_5_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_6_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_7_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_8_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_9_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_10_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_11_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_12_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_13_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_14_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_15_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_16_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_17_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_18_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_19_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_20_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_21_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_22_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_23_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_24_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_25_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_26_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_27_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_28_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_0_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_1_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_2_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_3_sqmuxa" in work.decoder(verilog)
        net "fsm_dly_1[0]" in work.decoder(verilog)
        net "fsm_dly_1[1]" in work.decoder(verilog)
        net "fsm_dly_1[2]" in work.decoder(verilog)
        net "alu_we_4_sqmuxa" in work.decoder(verilog)
        net "fsm_dly_1[0]" in work.decoder(verilog)
        net "fsm_dly_1[1]" in work.decoder(verilog)
        net "fsm_dly_1[2]" in work.decoder(verilog)
        net "fsm_dly350" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly351" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly352" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly353" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly354" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly355" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly356" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly357" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly358" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly359" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly360" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly361" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly362" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly363" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
        net "fsm_dly_1[0]" in work.decoder(verilog)
        net "fsm_dly_1[1]" in work.decoder(verilog)
        net "fsm_dly_1[2]" in work.decoder(verilog)
        net "fsm_dly365" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly366" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly367" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly368" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly369" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly370" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
4) instance ext_ctl_1[0] work.decoder(verilog)-ext_ctl_1[0], output net "ext_ctl_1[0]" in work.decoder(verilog)
    input nets to instance:
        net "ext_ctl_2[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_23" in work.decoder(verilog)
        net "un1_ins_i_20" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
5) instance ext_ctl_1[1] work.decoder(verilog)-ext_ctl_1[1], output net "ext_ctl_1[1]" in work.decoder(verilog)
    input nets to instance:
        net "ext_ctl_2[1]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
6) instance ext_ctl_1[2] work.decoder(verilog)-ext_ctl_1[2], output net "ext_ctl_1[2]" in work.decoder(verilog)
    input nets to instance:
        net "ext_ctl_2[2]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
7) instance rd_sel_1[0] work.decoder(verilog)-rd_sel_1[0], output net "rd_sel_1[0]" in work.decoder(verilog)
    input nets to instance:
        net "rd_sel_2[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
8) instance rd_sel_1[1] work.decoder(verilog)-rd_sel_1[1], output net "rd_sel_1[1]" in work.decoder(verilog)
    input nets to instance:
        net "rd_sel_2[1]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_22" in work.decoder(verilog)
        net "fsm_dly373" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
9) instance cmp_ctl_1[0] work.decoder(verilog)-cmp_ctl_1[0], output net "cmp_ctl_1[0]" in work.decoder(verilog)
    input nets to instance:
        net "cmp_ctl_2[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
10) instance cmp_ctl_1[1] work.decoder(verilog)-cmp_ctl_1[1], output net "cmp_ctl_1[1]" in work.decoder(verilog)
    input nets to instance:
        net "cmp_ctl_2[1]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
11) instance cmp_ctl_1[2] work.decoder(verilog)-cmp_ctl_1[2], output net "cmp_ctl_1[2]" in work.decoder(verilog)
    input nets to instance:
        net "cmp_ctl_2[2]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
12) instance pc_gen_ctl_1[0] work.decoder(verilog)-pc_gen_ctl_1[0], output net "pc_gen_ctl_1[0]" in work.decoder(verilog)
    input nets to instance:
        net "pc_gen_ctl_2[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_23" in work.decoder(verilog)
        net "un1_ins_i_20" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
13) instance pc_gen_ctl_1[1] work.decoder(verilog)-pc_gen_ctl_1[1], output net "pc_gen_ctl_1[1]" in work.decoder(verilog)
    input nets to instance:
        net "pc_gen_ctl_2[1]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
14) instance pc_gen_ctl_1[2] work.decoder(verilog)-pc_gen_ctl_1[2], output net "pc_gen_ctl_1[2]" in work.decoder(verilog)
    input nets to instance:
        net "pc_gen_ctl_2[2]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_23" in work.decoder(verilog)
        net "un1_ins_i_20" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
15) instance muxa_ctl_1[0] work.decoder(verilog)-muxa_ctl_1[0], output net "muxa_ctl_1[0]" in work.decoder(verilog)
    input nets to instance:
        net "muxa_ctl_2[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
16) instance muxa_ctl_1[1] work.decoder(verilog)-muxa_ctl_1[1], output net "muxa_ctl_1[1]" in work.decoder(verilog)
    input nets to instance:
        net "muxa_ctl_2[1]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_23" in work.decoder(verilog)
        net "un1_ins_i_20" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
17) instance muxb_ctl_1[0] work.decoder(verilog)-muxb_ctl_1[0], output net "muxb_ctl_1[0]" in work.decoder(verilog)
    input nets to instance:
        net "muxb_ctl_2[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
18) instance muxb_ctl_1[1] work.decoder(verilog)-muxb_ctl_1[1], output net "muxb_ctl_1[1]" in work.decoder(verilog)
    input nets to instance:
        net "muxb_ctl_2[1]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_23" in work.decoder(verilog)
        net "un1_ins_i_20" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
19) instance alu_func_1[0] work.decoder(verilog)-alu_func_1[0], output net "alu_func_1[0]" in work.decoder(verilog)
    input nets to instance:
        net "alu_func_2[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
20) instance alu_func_1[1] work.decoder(verilog)-alu_func_1[1], output net "alu_func_1[1]" in work.decoder(verilog)
    input nets to instance:
        net "alu_func_2[1]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
21) instance alu_func_1[2] work.decoder(verilog)-alu_func_1[2], output net "alu_func_1[2]" in work.decoder(verilog)
    input nets to instance:
        net "alu_func_2[2]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_23" in work.decoder(verilog)
        net "un1_ins_i_20" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
22) instance alu_func_1[3] work.decoder(verilog)-alu_func_1[3], output net "alu_func_1[3]" in work.decoder(verilog)
    input nets to instance:
        net "alu_func_2[3]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_23" in work.decoder(verilog)
        net "un1_ins_i_20" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
23) instance alu_func_1[4] work.decoder(verilog)-alu_func_1[4], output net "alu_func_1[4]" in work.decoder(verilog)
    input nets to instance:
        net "alu_func_2[4]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
24) instance dmem_ctl_1[0] work.decoder(verilog)-dmem_ctl_1[0], output net "dmem_ctl_1[0]" in work.decoder(verilog)
    input nets to instance:
        net "dmem_ctl_2[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_23" in work.decoder(verilog)
        net "un1_ins_i_20" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
25) instance dmem_ctl_1[1] work.decoder(verilog)-dmem_ctl_1[1], output net "dmem_ctl_1[1]" in work.decoder(verilog)
    input nets to instance:
        net "dmem_ctl_2[1]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_22" in work.decoder(verilog)
        net "fsm_dly373" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
26) instance dmem_ctl_1[2] work.decoder(verilog)-dmem_ctl_1[2], output net "dmem_ctl_1[2]" in work.decoder(verilog)
    input nets to instance:
        net "dmem_ctl_2[2]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_24" in work.decoder(verilog)
        net "un1_ins_i_15" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
27) instance dmem_ctl_1[3] work.decoder(verilog)-dmem_ctl_1[3], output net "dmem_ctl_1[3]" in work.decoder(verilog)
    input nets to instance:
        net "dmem_ctl_2[3]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
28) instance alu_we[0] work.decoder(verilog)-alu_we[0], output net "alu_we[0]" in work.decoder(verilog)
    input nets to instance:
        net "alu_we_1[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
29) instance wb_mux[0] work.decoder(verilog)-wb_mux[0], output net "wb_mux[0]" in work.decoder(verilog)
    input nets to instance:
        net "wb_mux_1[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
30) instance wb_we[0] work.decoder(verilog)-wb_we[0], output net "wb_we[0]" in work.decoder(verilog)
    input nets to instance:
        net "wb_we_1[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
End of loops
Warning: Found 28 combinational loops!
         Each loop is reported with an instance in the loop
         and nets connected to that instance.
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
1) instance fsm_dly_2[2:0] work.decoder(verilog)-fsm_dly_2[2:0], output net "fsm_dly_2[0]" in work.decoder(verilog)
    input nets to instance:
        net "alu_func_0_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_1_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_2_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_3_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_4_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_5_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_6_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_7_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_8_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_9_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_10_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_11_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_12_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_13_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_14_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_15_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_16_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_17_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_18_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_19_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_20_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_21_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_22_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_23_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_24_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_25_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_26_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_27_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_func_28_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_0_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_1_sqmuxa" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_2_sqmuxa" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_3_sqmuxa" in work.decoder(verilog)
        net "fsm_dly_1[0]" in work.decoder(verilog)
        net "fsm_dly_1[1]" in work.decoder(verilog)
        net "fsm_dly_1[2]" in work.decoder(verilog)
        net "alu_we_4_sqmuxa" in work.decoder(verilog)
        net "fsm_dly_1[0]" in work.decoder(verilog)
        net "fsm_dly_1[1]" in work.decoder(verilog)
        net "fsm_dly_1[2]" in work.decoder(verilog)
        net "fsm_dly350" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly351" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "fsm_dly352" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly353" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly354" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly355" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly356" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly357" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly358" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly359" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly360" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly361" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly362" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly363" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "VCC" in work.decoder(verilog)
        net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
        net "fsm_dly_1[0]" in work.decoder(verilog)
        net "fsm_dly_1[1]" in work.decoder(verilog)
        net "fsm_dly_1[2]" in work.decoder(verilog)
        net "fsm_dly365" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly366" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly367" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly368" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly369" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "fsm_dly370" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
        net "GND" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
2) instance ext_ctl_1[0] work.decoder(verilog)-ext_ctl_1[0], output net "ext_ctl_1[0]" in work.decoder(verilog)
    input nets to instance:
        net "ext_ctl_2[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_23" in work.decoder(verilog)
        net "un1_ins_i_20" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
3) instance ext_ctl_1[1] work.decoder(verilog)-ext_ctl_1[1], output net "ext_ctl_1[1]" in work.decoder(verilog)
    input nets to instance:
        net "ext_ctl_2[1]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
4) instance ext_ctl_1[2] work.decoder(verilog)-ext_ctl_1[2], output net "ext_ctl_1[2]" in work.decoder(verilog)
    input nets to instance:
        net "ext_ctl_2[2]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
5) instance rd_sel_1[0] work.decoder(verilog)-rd_sel_1[0], output net "rd_sel_1[0]" in work.decoder(verilog)
    input nets to instance:
        net "rd_sel_2[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
6) instance rd_sel_1[1] work.decoder(verilog)-rd_sel_1[1], output net "rd_sel_1[1]" in work.decoder(verilog)
    input nets to instance:
        net "rd_sel_2[1]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_22" in work.decoder(verilog)
        net "fsm_dly373" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
7) instance cmp_ctl_1[0] work.decoder(verilog)-cmp_ctl_1[0], output net "cmp_ctl_1[0]" in work.decoder(verilog)
    input nets to instance:
        net "cmp_ctl_2[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
8) instance cmp_ctl_1[1] work.decoder(verilog)-cmp_ctl_1[1], output net "cmp_ctl_1[1]" in work.decoder(verilog)
    input nets to instance:
        net "cmp_ctl_2[1]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
9) instance cmp_ctl_1[2] work.decoder(verilog)-cmp_ctl_1[2], output net "cmp_ctl_1[2]" in work.decoder(verilog)
    input nets to instance:
        net "cmp_ctl_2[2]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
10) instance pc_gen_ctl_1[0] work.decoder(verilog)-pc_gen_ctl_1[0], output net "pc_gen_ctl_1[0]" in work.decoder(verilog)
    input nets to instance:
        net "pc_gen_ctl_2[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_23" in work.decoder(verilog)
        net "un1_ins_i_20" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
11) instance pc_gen_ctl_1[1] work.decoder(verilog)-pc_gen_ctl_1[1], output net "pc_gen_ctl_1[1]" in work.decoder(verilog)
    input nets to instance:
        net "pc_gen_ctl_2[1]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
12) instance pc_gen_ctl_1[2] work.decoder(verilog)-pc_gen_ctl_1[2], output net "pc_gen_ctl_1[2]" in work.decoder(verilog)
    input nets to instance:
        net "pc_gen_ctl_2[2]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_23" in work.decoder(verilog)
        net "un1_ins_i_20" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
13) instance muxa_ctl_1[0] work.decoder(verilog)-muxa_ctl_1[0], output net "muxa_ctl_1[0]" in work.decoder(verilog)
    input nets to instance:
        net "muxa_ctl_2[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
14) instance muxa_ctl_1[1] work.decoder(verilog)-muxa_ctl_1[1], output net "muxa_ctl_1[1]" in work.decoder(verilog)
    input nets to instance:
        net "muxa_ctl_2[1]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_23" in work.decoder(verilog)
        net "un1_ins_i_20" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
15) instance muxb_ctl_1[0] work.decoder(verilog)-muxb_ctl_1[0], output net "muxb_ctl_1[0]" in work.decoder(verilog)
    input nets to instance:
        net "muxb_ctl_2[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
16) instance muxb_ctl_1[1] work.decoder(verilog)-muxb_ctl_1[1], output net "muxb_ctl_1[1]" in work.decoder(verilog)
    input nets to instance:
        net "muxb_ctl_2[1]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_23" in work.decoder(verilog)
        net "un1_ins_i_20" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
17) instance alu_func_1[0] work.decoder(verilog)-alu_func_1[0], output net "alu_func_1[0]" in work.decoder(verilog)
    input nets to instance:
        net "alu_func_2[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
18) instance alu_func_1[1] work.decoder(verilog)-alu_func_1[1], output net "alu_func_1[1]" in work.decoder(verilog)
    input nets to instance:
        net "alu_func_2[1]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
19) instance alu_func_1[2] work.decoder(verilog)-alu_func_1[2], output net "alu_func_1[2]" in work.decoder(verilog)
    input nets to instance:
        net "alu_func_2[2]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_23" in work.decoder(verilog)
        net "un1_ins_i_20" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
20) instance alu_func_1[3] work.decoder(verilog)-alu_func_1[3], output net "alu_func_1[3]" in work.decoder(verilog)
    input nets to instance:
        net "alu_func_2[3]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_23" in work.decoder(verilog)
        net "un1_ins_i_20" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
21) instance alu_func_1[4] work.decoder(verilog)-alu_func_1[4], output net "alu_func_1[4]" in work.decoder(verilog)
    input nets to instance:
        net "alu_func_2[4]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
22) instance dmem_ctl_1[0] work.decoder(verilog)-dmem_ctl_1[0], output net "dmem_ctl_1[0]" in work.decoder(verilog)
    input nets to instance:
        net "dmem_ctl_2[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_23" in work.decoder(verilog)
        net "un1_ins_i_20" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
23) instance dmem_ctl_1[1] work.decoder(verilog)-dmem_ctl_1[1], output net "dmem_ctl_1[1]" in work.decoder(verilog)
    input nets to instance:
        net "dmem_ctl_2[1]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_22" in work.decoder(verilog)
        net "fsm_dly373" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
24) instance dmem_ctl_1[2] work.decoder(verilog)-dmem_ctl_1[2], output net "dmem_ctl_1[2]" in work.decoder(verilog)
    input nets to instance:
        net "dmem_ctl_2[2]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_24" in work.decoder(verilog)
        net "un1_ins_i_15" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
25) instance dmem_ctl_1[3] work.decoder(verilog)-dmem_ctl_1[3], output net "dmem_ctl_1[3]" in work.decoder(verilog)
    input nets to instance:
        net "dmem_ctl_2[3]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
26) instance alu_we[0] work.decoder(verilog)-alu_we[0], output net "alu_we[0]" in work.decoder(verilog)
    input nets to instance:
        net "alu_we_1[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
27) instance wb_mux[0] work.decoder(verilog)-wb_mux[0], output net "wb_mux[0]" in work.decoder(verilog)
    input nets to instance:
        net "wb_mux_1[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
28) instance wb_we[0] work.decoder(verilog)-wb_we[0], output net "wb_we[0]" in work.decoder(verilog)
    input nets to instance:
        net "wb_we_1[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_21" in work.decoder(verilog)
End of loops
@N:"e:\mips789\mips789\rtl\verilog\mips_uart.v":243:4:243:9|Found counter in view:work.uart_read(verilog) inst clk_ctr[15:0]
@N:"e:\mips789\mips789\rtl\verilog\mips_uart.v":256:4:256:9|Found counter in view:work.uart_read(verilog) inst bit_ctr[2:0]
Encoding state machine work.uart_read(verilog)-ua_state[4:0]
original code -> new code
   000 -> 00000
   001 -> 00011
   010 -> 00101
   011 -> 01001
   100 -> 10001
@N:"e:\mips789\mips789\rtl\verilog\mips_uart.v":138:4:138:9|Found counter in view:work.uart_write(verilog) inst clk_ctr[15:0]
@N:"e:\mips789\mips789\rtl\verilog\mips_uart.v":151:4:151:9|Found counter in view:work.uart_write(verilog) inst bit_ctr[2:0]
Encoding state machine work.uart_write(verilog)-ua_state[7:0]
original code -> new code
   000 -> 00000000
   001 -> 00000011
   010 -> 00000101
   011 -> 00001001
   100 -> 00010001
   101 -> 00100001
   110 -> 01000001
   111 -> 10000001
@N: MO106 :"e:\mips789\mips789\rtl\verilog\dvc.v":67:12:67:15|Found ROM, 'seg_20[6:0]', 16 words by 7 bits 
@N: MO106 :"e:\mips789\mips789\rtl\verilog\dvc.v":67:12:67:15|Found ROM, 'seg[6:0]', 16 words by 7 bits 
@N:"e:\mips789\mips789\rtl\verilog\dvc.v":23:4:23:9|Found counter in view:work.tmr0(verilog) inst cntr[31:0]
Warning: Found 28 combinational loops!
         Each loop is reported with an instance in the loop
         and nets connected to that instance.
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
1) instance fsm_dly_2[0] work.decoder(verilog)-fsm_dly_2[0], output net "fsm_dly_2[0]" in work.decoder(verilog)
    input nets to instance:
        net "N_172" in work.decoder(verilog)
        net "fsm_dly_1[0]" in work.decoder(verilog)
        net "N_415" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
2) instance ext_ctl_1[0] work.decoder(verilog)-ext_ctl_1[0], output net "ext_ctl_1[0]" in work.decoder(verilog)
    input nets to instance:
        net "ext_ctl_2[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_23" in work.decoder(verilog)
        net "un1_ins_i_20" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
3) instance ext_ctl_1[1] work.decoder(verilog)-ext_ctl_1[1], output net "ext_ctl_1[1]" in work.decoder(verilog)
    input nets to instance:
        net "ext_ctl_2[1]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "N_436" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
4) instance ext_ctl_1[2] work.decoder(verilog)-ext_ctl_1[2], output net "ext_ctl_1[2]" in work.decoder(verilog)
    input nets to instance:
        net "ext_ctl_2[2]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "N_436" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
5) instance rd_sel_1[0] work.decoder(verilog)-rd_sel_1[0], output net "rd_sel_1[0]" in work.decoder(verilog)
    input nets to instance:
        net "rd_sel_2[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "N_436" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
6) instance rd_sel_1[1] work.decoder(verilog)-rd_sel_1[1], output net "rd_sel_1[1]" in work.decoder(verilog)
    input nets to instance:
        net "rd_sel_2[1]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "N_438" in work.decoder(verilog)
        net "fsm_dly373" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
7) instance cmp_ctl_1[0] work.decoder(verilog)-cmp_ctl_1[0], output net "cmp_ctl_1[0]" in work.decoder(verilog)
    input nets to instance:
        net "cmp_ctl_2[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "N_436" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
8) instance cmp_ctl_1[1] work.decoder(verilog)-cmp_ctl_1[1], output net "cmp_ctl_1[1]" in work.decoder(verilog)
    input nets to instance:
        net "cmp_ctl_2[1]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "N_436" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
9) instance cmp_ctl_1[2] work.decoder(verilog)-cmp_ctl_1[2], output net "cmp_ctl_1[2]" in work.decoder(verilog)
    input nets to instance:
        net "cmp_ctl_2[2]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "N_436" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
10) instance pc_gen_ctl_1[0] work.decoder(verilog)-pc_gen_ctl_1[0], output net "pc_gen_ctl_1[0]" in work.decoder(verilog)
    input nets to instance:
        net "pc_gen_ctl_2[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_23" in work.decoder(verilog)
        net "un1_ins_i_20" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
11) instance pc_gen_ctl_1[1] work.decoder(verilog)-pc_gen_ctl_1[1], output net "pc_gen_ctl_1[1]" in work.decoder(verilog)
    input nets to instance:
        net "pc_gen_ctl_2[1]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "N_436" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
12) instance pc_gen_ctl_1[2] work.decoder(verilog)-pc_gen_ctl_1[2], output net "pc_gen_ctl_1[2]" in work.decoder(verilog)
    input nets to instance:
        net "pc_gen_ctl_2[2]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_23" in work.decoder(verilog)
        net "un1_ins_i_20" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
13) instance muxa_ctl_1[0] work.decoder(verilog)-muxa_ctl_1[0], output net "muxa_ctl_1[0]" in work.decoder(verilog)
    input nets to instance:
        net "muxa_ctl_2[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "N_436" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
14) instance muxa_ctl_1[1] work.decoder(verilog)-muxa_ctl_1[1], output net "muxa_ctl_1[1]" in work.decoder(verilog)
    input nets to instance:
        net "muxa_ctl_2[1]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_23" in work.decoder(verilog)
        net "un1_ins_i_20" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
15) instance muxb_ctl_1[0] work.decoder(verilog)-muxb_ctl_1[0], output net "muxb_ctl_1[0]" in work.decoder(verilog)
    input nets to instance:
        net "muxb_ctl_2[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "N_436" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
16) instance muxb_ctl_1[1] work.decoder(verilog)-muxb_ctl_1[1], output net "muxb_ctl_1[1]" in work.decoder(verilog)
    input nets to instance:
        net "muxb_ctl_2[1]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_23" in work.decoder(verilog)
        net "un1_ins_i_20" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
17) instance alu_func_1[0] work.decoder(verilog)-alu_func_1[0], output net "alu_func_1[0]" in work.decoder(verilog)
    input nets to instance:
        net "alu_func_2[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "N_436" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
18) instance alu_func_1[1] work.decoder(verilog)-alu_func_1[1], output net "alu_func_1[1]" in work.decoder(verilog)
    input nets to instance:
        net "alu_func_2[1]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "N_436" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
19) instance alu_func_1[2] work.decoder(verilog)-alu_func_1[2], output net "alu_func_1[2]" in work.decoder(verilog)
    input nets to instance:
        net "alu_func_2[2]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_23" in work.decoder(verilog)
        net "un1_ins_i_20" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
20) instance alu_func_1[3] work.decoder(verilog)-alu_func_1[3], output net "alu_func_1[3]" in work.decoder(verilog)
    input nets to instance:
        net "alu_func_2[3]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_23" in work.decoder(verilog)
        net "un1_ins_i_20" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
21) instance alu_func_1[4] work.decoder(verilog)-alu_func_1[4], output net "alu_func_1[4]" in work.decoder(verilog)
    input nets to instance:
        net "alu_func_2[4]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "N_436" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
22) instance dmem_ctl_1[0] work.decoder(verilog)-dmem_ctl_1[0], output net "dmem_ctl_1[0]" in work.decoder(verilog)
    input nets to instance:
        net "dmem_ctl_2[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_23" in work.decoder(verilog)
        net "un1_ins_i_20" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
23) instance dmem_ctl_1[1] work.decoder(verilog)-dmem_ctl_1[1], output net "dmem_ctl_1[1]" in work.decoder(verilog)
    input nets to instance:
        net "dmem_ctl_2[1]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "N_438" in work.decoder(verilog)
        net "fsm_dly373" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
24) instance dmem_ctl_1[2] work.decoder(verilog)-dmem_ctl_1[2], output net "dmem_ctl_1[2]" in work.decoder(verilog)
    input nets to instance:
        net "dmem_ctl_2[2]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_24" in work.decoder(verilog)
        net "un1_ins_i_15" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
25) instance dmem_ctl_1[3] work.decoder(verilog)-dmem_ctl_1[3], output net "dmem_ctl_1[3]" in work.decoder(verilog)
    input nets to instance:
        net "dmem_ctl_2[3]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "N_436" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
26) instance alu_we[0] work.decoder(verilog)-alu_we[0], output net "alu_we[0]" in work.decoder(verilog)
    input nets to instance:
        net "alu_we_1[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "N_436" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
27) instance wb_mux[0] work.decoder(verilog)-wb_mux[0], output net "wb_mux[0]" in work.decoder(verilog)
    input nets to instance:
        net "wb_mux_1[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "N_436" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
28) instance wb_we[0] work.decoder(verilog)-wb_we[0], output net "wb_we[0]" in work.decoder(verilog)
    input nets to instance:
        net "wb_we_1[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "N_436" in work.decoder(verilog)
End of loops
Warning: Found 28 combinational loops!
         Each loop is reported with an instance in the loop
         and nets connected to that instance.
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
1) instance fsm_dly_2[0] work.decoder(verilog)-fsm_dly_2[0], output net "fsm_dly_2[0]" in work.decoder(verilog)
    input nets to instance:
        net "N_172" in work.decoder(verilog)
        net "fsm_dly_1[0]" in work.decoder(verilog)
        net "N_415" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
2) instance ext_ctl_1[0] work.decoder(verilog)-ext_ctl_1[0], output net "ext_ctl_1[0]" in work.decoder(verilog)
    input nets to instance:
        net "ext_ctl_2[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_23" in work.decoder(verilog)
        net "un1_ins_i_20" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
3) instance ext_ctl_1[1] work.decoder(verilog)-ext_ctl_1[1], output net "ext_ctl_1[1]" in work.decoder(verilog)
    input nets to instance:
        net "ext_ctl_2[1]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "N_436" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
4) instance ext_ctl_1[2] work.decoder(verilog)-ext_ctl_1[2], output net "ext_ctl_1[2]" in work.decoder(verilog)
    input nets to instance:
        net "ext_ctl_2[2]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "N_436" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
5) instance rd_sel_1[0] work.decoder(verilog)-rd_sel_1[0], output net "rd_sel_1[0]" in work.decoder(verilog)
    input nets to instance:
        net "rd_sel_2[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "N_436" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
6) instance rd_sel_1[1] work.decoder(verilog)-rd_sel_1[1], output net "rd_sel_1[1]" in work.decoder(verilog)
    input nets to instance:
        net "rd_sel_2[1]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "N_438" in work.decoder(verilog)
        net "fsm_dly373" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
7) instance cmp_ctl_1[0] work.decoder(verilog)-cmp_ctl_1[0], output net "cmp_ctl_1[0]" in work.decoder(verilog)
    input nets to instance:
        net "cmp_ctl_2[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "N_436" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
8) instance cmp_ctl_1[1] work.decoder(verilog)-cmp_ctl_1[1], output net "cmp_ctl_1[1]" in work.decoder(verilog)
    input nets to instance:
        net "cmp_ctl_2[1]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "N_436" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
9) instance cmp_ctl_1[2] work.decoder(verilog)-cmp_ctl_1[2], output net "cmp_ctl_1[2]" in work.decoder(verilog)
    input nets to instance:
        net "cmp_ctl_2[2]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "N_436" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
10) instance pc_gen_ctl_1[0] work.decoder(verilog)-pc_gen_ctl_1[0], output net "pc_gen_ctl_1[0]" in work.decoder(verilog)
    input nets to instance:
        net "pc_gen_ctl_2[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_23" in work.decoder(verilog)
        net "un1_ins_i_20" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
11) instance pc_gen_ctl_1[1] work.decoder(verilog)-pc_gen_ctl_1[1], output net "pc_gen_ctl_1[1]" in work.decoder(verilog)
    input nets to instance:
        net "pc_gen_ctl_2[1]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "N_436" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
12) instance pc_gen_ctl_1[2] work.decoder(verilog)-pc_gen_ctl_1[2], output net "pc_gen_ctl_1[2]" in work.decoder(verilog)
    input nets to instance:
        net "pc_gen_ctl_2[2]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_23" in work.decoder(verilog)
        net "un1_ins_i_20" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
13) instance muxa_ctl_1[0] work.decoder(verilog)-muxa_ctl_1[0], output net "muxa_ctl_1[0]" in work.decoder(verilog)
    input nets to instance:
        net "muxa_ctl_2[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "N_436" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
14) instance muxa_ctl_1[1] work.decoder(verilog)-muxa_ctl_1[1], output net "muxa_ctl_1[1]" in work.decoder(verilog)
    input nets to instance:
        net "muxa_ctl_2[1]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_23" in work.decoder(verilog)
        net "un1_ins_i_20" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
15) instance muxb_ctl_1[0] work.decoder(verilog)-muxb_ctl_1[0], output net "muxb_ctl_1[0]" in work.decoder(verilog)
    input nets to instance:
        net "muxb_ctl_2[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "N_436" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
16) instance muxb_ctl_1[1] work.decoder(verilog)-muxb_ctl_1[1], output net "muxb_ctl_1[1]" in work.decoder(verilog)
    input nets to instance:
        net "muxb_ctl_2[1]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_23" in work.decoder(verilog)
        net "un1_ins_i_20" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
17) instance alu_func_1[0] work.decoder(verilog)-alu_func_1[0], output net "alu_func_1[0]" in work.decoder(verilog)
    input nets to instance:
        net "alu_func_2[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "N_436" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
18) instance alu_func_1[1] work.decoder(verilog)-alu_func_1[1], output net "alu_func_1[1]" in work.decoder(verilog)
    input nets to instance:
        net "alu_func_2[1]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "N_436" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
19) instance alu_func_1[2] work.decoder(verilog)-alu_func_1[2], output net "alu_func_1[2]" in work.decoder(verilog)
    input nets to instance:
        net "alu_func_2[2]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_23" in work.decoder(verilog)
        net "un1_ins_i_20" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
20) instance alu_func_1[3] work.decoder(verilog)-alu_func_1[3], output net "alu_func_1[3]" in work.decoder(verilog)
    input nets to instance:
        net "alu_func_2[3]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_23" in work.decoder(verilog)
        net "un1_ins_i_20" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
21) instance alu_func_1[4] work.decoder(verilog)-alu_func_1[4], output net "alu_func_1[4]" in work.decoder(verilog)
    input nets to instance:
        net "alu_func_2[4]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "N_436" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
22) instance dmem_ctl_1[0] work.decoder(verilog)-dmem_ctl_1[0], output net "dmem_ctl_1[0]" in work.decoder(verilog)
    input nets to instance:
        net "dmem_ctl_2[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_23" in work.decoder(verilog)
        net "un1_ins_i_20" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
23) instance dmem_ctl_1[1] work.decoder(verilog)-dmem_ctl_1[1], output net "dmem_ctl_1[1]" in work.decoder(verilog)
    input nets to instance:
        net "dmem_ctl_2[1]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "N_438" in work.decoder(verilog)
        net "fsm_dly373" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
24) instance dmem_ctl_1[2] work.decoder(verilog)-dmem_ctl_1[2], output net "dmem_ctl_1[2]" in work.decoder(verilog)
    input nets to instance:
        net "dmem_ctl_2[2]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_24" in work.decoder(verilog)
        net "un1_ins_i_15" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
25) instance dmem_ctl_1[3] work.decoder(verilog)-dmem_ctl_1[3], output net "dmem_ctl_1[3]" in work.decoder(verilog)
    input nets to instance:
        net "dmem_ctl_2[3]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "N_436" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
26) instance alu_we[0] work.decoder(verilog)-alu_we[0], output net "alu_we[0]" in work.decoder(verilog)
    input nets to instance:
        net "alu_we_1[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "N_436" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
27) instance wb_mux[0] work.decoder(verilog)-wb_mux[0], output net "wb_mux[0]" in work.decoder(verilog)
    input nets to instance:
        net "wb_mux_1[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "N_436" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
28) instance wb_we[0] work.decoder(verilog)-wb_we[0], output net "wb_we[0]" in work.decoder(verilog)
    input nets to instance:
        net "wb_we_1[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "N_436" in work.decoder(verilog)
End of loops
Warning: Found 28 combinational loops!
         Each loop is reported with an instance in the loop
         and nets connected to that instance.
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
1) instance fsm_dly_2[0] work.decoder(verilog)-fsm_dly_2[0], output net "fsm_dly_2[0]" in work.decoder(verilog)
    input nets to instance:
        net "N_172" in work.decoder(verilog)
        net "fsm_dly_1[0]" in work.decoder(verilog)
        net "N_415" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
2) instance ext_ctl_1[0] work.decoder(verilog)-ext_ctl_1[0], output net "ext_ctl_1[0]" in work.decoder(verilog)
    input nets to instance:
        net "ext_ctl_2[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_23" in work.decoder(verilog)
        net "un1_ins_i_20" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
3) instance ext_ctl_1[1] work.decoder(verilog)-ext_ctl_1[1], output net "ext_ctl_1[1]" in work.decoder(verilog)
    input nets to instance:
        net "ext_ctl_2[1]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "N_436" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
4) instance ext_ctl_1[2] work.decoder(verilog)-ext_ctl_1[2], output net "ext_ctl_1[2]" in work.decoder(verilog)
    input nets to instance:
        net "ext_ctl_2[2]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "N_436" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
5) instance rd_sel_1[0] work.decoder(verilog)-rd_sel_1[0], output net "rd_sel_1[0]" in work.decoder(verilog)
    input nets to instance:
        net "rd_sel_2[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "N_436" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
6) instance rd_sel_1[1] work.decoder(verilog)-rd_sel_1[1], output net "rd_sel_1[1]" in work.decoder(verilog)
    input nets to instance:
        net "rd_sel_2[1]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "N_438" in work.decoder(verilog)
        net "fsm_dly373" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
7) instance cmp_ctl_1[0] work.decoder(verilog)-cmp_ctl_1[0], output net "cmp_ctl_1[0]" in work.decoder(verilog)
    input nets to instance:
        net "cmp_ctl_2[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "N_436" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
8) instance cmp_ctl_1[1] work.decoder(verilog)-cmp_ctl_1[1], output net "cmp_ctl_1[1]" in work.decoder(verilog)
    input nets to instance:
        net "cmp_ctl_2[1]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "N_436" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
9) instance cmp_ctl_1[2] work.decoder(verilog)-cmp_ctl_1[2], output net "cmp_ctl_1[2]" in work.decoder(verilog)
    input nets to instance:
        net "cmp_ctl_2[2]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "N_436" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
10) instance pc_gen_ctl_1[0] work.decoder(verilog)-pc_gen_ctl_1[0], output net "pc_gen_ctl_1[0]" in work.decoder(verilog)
    input nets to instance:
        net "pc_gen_ctl_2[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_23" in work.decoder(verilog)
        net "un1_ins_i_20" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
11) instance pc_gen_ctl_1[1] work.decoder(verilog)-pc_gen_ctl_1[1], output net "pc_gen_ctl_1[1]" in work.decoder(verilog)
    input nets to instance:
        net "pc_gen_ctl_2[1]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "N_436" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
12) instance pc_gen_ctl_1[2] work.decoder(verilog)-pc_gen_ctl_1[2], output net "pc_gen_ctl_1[2]" in work.decoder(verilog)
    input nets to instance:
        net "pc_gen_ctl_2[2]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_23" in work.decoder(verilog)
        net "un1_ins_i_20" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
13) instance muxa_ctl_1[0] work.decoder(verilog)-muxa_ctl_1[0], output net "muxa_ctl_1[0]" in work.decoder(verilog)
    input nets to instance:
        net "muxa_ctl_2[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "N_436" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
14) instance muxa_ctl_1[1] work.decoder(verilog)-muxa_ctl_1[1], output net "muxa_ctl_1[1]" in work.decoder(verilog)
    input nets to instance:
        net "muxa_ctl_2[1]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_23" in work.decoder(verilog)
        net "un1_ins_i_20" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
15) instance muxb_ctl_1[0] work.decoder(verilog)-muxb_ctl_1[0], output net "muxb_ctl_1[0]" in work.decoder(verilog)
    input nets to instance:
        net "muxb_ctl_2[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "N_436" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
16) instance muxb_ctl_1[1] work.decoder(verilog)-muxb_ctl_1[1], output net "muxb_ctl_1[1]" in work.decoder(verilog)
    input nets to instance:
        net "muxb_ctl_2[1]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_23" in work.decoder(verilog)
        net "un1_ins_i_20" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
17) instance alu_func_1[0] work.decoder(verilog)-alu_func_1[0], output net "alu_func_1[0]" in work.decoder(verilog)
    input nets to instance:
        net "alu_func_2[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "N_436" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
18) instance alu_func_1[1] work.decoder(verilog)-alu_func_1[1], output net "alu_func_1[1]" in work.decoder(verilog)
    input nets to instance:
        net "alu_func_2[1]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "N_436" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
19) instance alu_func_1[2] work.decoder(verilog)-alu_func_1[2], output net "alu_func_1[2]" in work.decoder(verilog)
    input nets to instance:
        net "alu_func_2[2]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_23" in work.decoder(verilog)
        net "un1_ins_i_20" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
20) instance alu_func_1[3] work.decoder(verilog)-alu_func_1[3], output net "alu_func_1[3]" in work.decoder(verilog)
    input nets to instance:
        net "alu_func_2[3]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_23" in work.decoder(verilog)
        net "un1_ins_i_20" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
21) instance alu_func_1[4] work.decoder(verilog)-alu_func_1[4], output net "alu_func_1[4]" in work.decoder(verilog)
    input nets to instance:
        net "alu_func_2[4]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "N_436" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
22) instance dmem_ctl_1[0] work.decoder(verilog)-dmem_ctl_1[0], output net "dmem_ctl_1[0]" in work.decoder(verilog)
    input nets to instance:
        net "dmem_ctl_2[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_23" in work.decoder(verilog)
        net "un1_ins_i_20" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
23) instance dmem_ctl_1[1] work.decoder(verilog)-dmem_ctl_1[1], output net "dmem_ctl_1[1]" in work.decoder(verilog)
    input nets to instance:
        net "dmem_ctl_2[1]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "N_438" in work.decoder(verilog)
        net "fsm_dly373" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
24) instance dmem_ctl_1[2] work.decoder(verilog)-dmem_ctl_1[2], output net "dmem_ctl_1[2]" in work.decoder(verilog)
    input nets to instance:
        net "dmem_ctl_2[2]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "un1_ins_i_24" in work.decoder(verilog)
        net "un1_ins_i_15" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
25) instance dmem_ctl_1[3] work.decoder(verilog)-dmem_ctl_1[3], output net "dmem_ctl_1[3]" in work.decoder(verilog)
    input nets to instance:
        net "dmem_ctl_2[3]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "N_436" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
26) instance alu_we[0] work.decoder(verilog)-alu_we[0], output net "alu_we[0]" in work.decoder(verilog)
    input nets to instance:
        net "alu_we_1[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "N_436" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
27) instance wb_mux[0] work.decoder(verilog)-wb_mux[0], output net "wb_mux[0]" in work.decoder(verilog)
    input nets to instance:
        net "wb_mux_1[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "N_436" in work.decoder(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
28) instance wb_we[0] work.decoder(verilog)-wb_we[0], output net "wb_we[0]" in work.decoder(verilog)
    input nets to instance:
        net "wb_we_1[0]" in work.decoder(verilog)
        net "un1_fsm_dly370" in work.decoder(verilog)
        net "N_436" in work.decoder(verilog)
End of loops
Automatic dissolve during optimization of view:work.mips_core(verilog) of iRF_stage.reg_bank(reg_array)
Auto Dissolve of decoder_pipe (inst of view:work.decode_pipe(verilog))
Auto Dissolve of iRF_stage.i_cmp (inst of view:work.compare(verilog))
Auto Dissolve of mips_tmr0 (inst of view:work.tmr0(verilog))
Warning: Found 28 combinational loops!
         Each loop is reported with an instance in the loop
         and nets connected to that instance.
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
1) instance mips_core.decoder_pipe.idecoder.fsm_dly_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.fsm_dly_1[0], output net "mips_core.BUS197[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.fsm_dly_2[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
2) instance mips_core.decoder_pipe.idecoder.ext_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.ext_ctl_1[0], output net "mips_core.decoder_pipe.BUS2072[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.N_1373" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
3) instance mips_core.decoder_pipe.idecoder.ext_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.ext_ctl_1[1], output net "mips_core.decoder_pipe.BUS2072[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.N_1374" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
4) instance mips_core.decoder_pipe.idecoder.ext_ctl_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.ext_ctl_1[2], output net "mips_core.decoder_pipe.BUS2072[2]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.ext_ctl_2[2]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
5) instance mips_core.decoder_pipe.idecoder.rd_sel_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.rd_sel_1[0], output net "mips_core.decoder_pipe.BUS2110[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.rd_sel_2[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
6) instance mips_core.decoder_pipe.idecoder.rd_sel_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.rd_sel_1[1], output net "mips_core.decoder_pipe.BUS2110[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.rd_sel_2[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_438" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.fsm_dly373" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
7) instance mips_core.decoder_pipe.idecoder.cmp_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.cmp_ctl_1[0], output net "mips_core.decoder_pipe.BUS2056[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.cmp_ctl_2[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
8) instance mips_core.decoder_pipe.idecoder.cmp_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.cmp_ctl_1[1], output net "mips_core.decoder_pipe.BUS2056[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.cmp_ctl_2[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
9) instance mips_core.decoder_pipe.idecoder.cmp_ctl_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.cmp_ctl_1[2], output net "mips_core.decoder_pipe.BUS2056[2]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.cmp_ctl_2[2]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
10) instance mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[0], output net "mips_core.decoder_pipe.BUS2102[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.N_1376" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
11) instance mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[1], output net "mips_core.decoder_pipe.BUS2102[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.pc_gen_ctl_2[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
12) instance mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[2], output net "mips_core.decoder_pipe.BUS2102[2]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.N_1260_i" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
13) instance mips_core.decoder_pipe.idecoder.muxa_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxa_ctl_1[0], output net "mips_core.decoder_pipe.BUS2086[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.muxa_ctl_2[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
14) instance mips_core.decoder_pipe.idecoder.muxa_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxa_ctl_1[1], output net "mips_core.decoder_pipe.BUS2086[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.muxa_ctl_2[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
15) instance mips_core.decoder_pipe.idecoder.muxb_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxb_ctl_1[0], output net "mips_core.decoder_pipe.BUS2094[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.muxb_ctl_2[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
16) instance mips_core.decoder_pipe.idecoder.muxb_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxb_ctl_1[1], output net "mips_core.decoder_pipe.BUS2094[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.muxb_ctl_2[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
17) instance mips_core.decoder_pipe.idecoder.alu_func_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[0], output net "mips_core.decoder_pipe.BUS2040[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.alu_func_2[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
18) instance mips_core.decoder_pipe.idecoder.alu_func_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[1], output net "mips_core.decoder_pipe.BUS2040[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.alu_func_2[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
19) instance mips_core.decoder_pipe.idecoder.alu_func_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[2], output net "mips_core.decoder_pipe.BUS2040[2]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.N_1372" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
20) instance mips_core.decoder_pipe.idecoder.alu_func_1[3] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[3], output net "mips_core.decoder_pipe.BUS2040[3]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.alu_func_2[3]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
21) instance mips_core.decoder_pipe.idecoder.alu_func_1[4] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[4], output net "mips_core.decoder_pipe.BUS2040[4]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.alu_func_2[4]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
22) instance mips_core.decoder_pipe.idecoder.dmem_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[0], output net "mips_core.decoder_pipe.BUS2064[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
23) instance mips_core.decoder_pipe.idecoder.dmem_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[1], output net "mips_core.decoder_pipe.BUS2064[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_438" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.fsm_dly373" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
24) instance mips_core.decoder_pipe.idecoder.dmem_ctl_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[2], output net "mips_core.decoder_pipe.BUS2064[2]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[2]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_24" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_15" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
25) instance mips_core.decoder_pipe.idecoder.dmem_ctl_1[3] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[3], output net "mips_core.decoder_pipe.BUS2064[3]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[3]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
26) instance mips_core.decoder_pipe.idecoder.alu_we[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_we[0], output net "mips_core.decoder_pipe.BUS2048[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.alu_we_1[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
27) instance mips_core.decoder_pipe.idecoder.wb_mux[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.wb_mux[0], output net "mips_core.decoder_pipe.BUS2118[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.wb_mux_1[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
28) instance mips_core.decoder_pipe.idecoder.wb_we[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.wb_we[0], output net "mips_core.decoder_pipe.BUS2126[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.wb_we_1[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
End of loops
@W: BN116 :"e:\mips789\mips789\rtl\verilog\mips_dvc.v":117:4:117:9|Removing sequential instance imips_dvc.key2_addr[31] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\mips_dvc.v":117:4:117:9|Removing sequential instance imips_dvc.key2_addr[30] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\mips_dvc.v":117:4:117:9|Removing sequential instance imips_dvc.key2_addr[29] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\mips_dvc.v":117:4:117:9|Removing sequential instance imips_dvc.key2_addr[28] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\mips_dvc.v":117:4:117:9|Removing sequential instance imips_dvc.key2_addr[27] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\mips_dvc.v":117:4:117:9|Removing sequential instance imips_dvc.key2_addr[26] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\mips_dvc.v":117:4:117:9|Removing sequential instance imips_dvc.key2_addr[25] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\mips_dvc.v":117:4:117:9|Removing sequential instance imips_dvc.key2_addr[24] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\mips_dvc.v":117:4:117:9|Removing sequential instance imips_dvc.key2_addr[23] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\mips_dvc.v":117:4:117:9|Removing sequential instance imips_dvc.key2_addr[22] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\mips_dvc.v":117:4:117:9|Removing sequential instance imips_dvc.key2_addr[21] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\mips_dvc.v":117:4:117:9|Removing sequential instance imips_dvc.key2_addr[20] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\mips_dvc.v":117:4:117:9|Removing sequential instance imips_dvc.key2_addr[19] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\mips_dvc.v":117:4:117:9|Removing sequential instance imips_dvc.key2_addr[18] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\mips_dvc.v":117:4:117:9|Removing sequential instance imips_dvc.key2_addr[17] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\mips_dvc.v":117:4:117:9|Removing sequential instance imips_dvc.key2_addr[16] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\mips_dvc.v":117:4:117:9|Removing sequential instance imips_dvc.key2_addr[15] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\mips_dvc.v":117:4:117:9|Removing sequential instance imips_dvc.key2_addr[14] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\mips_dvc.v":117:4:117:9|Removing sequential instance imips_dvc.key2_addr[13] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\mips_dvc.v":117:4:117:9|Removing sequential instance imips_dvc.key2_addr[12] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\mips_dvc.v":117:4:117:9|Removing sequential instance imips_dvc.key2_addr[11] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\mips_dvc.v":117:4:117:9|Removing sequential instance imips_dvc.key2_addr[10] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\mips_dvc.v":117:4:117:9|Removing sequential instance imips_dvc.key2_addr[9] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\mips_dvc.v":117:4:117:9|Removing sequential instance imips_dvc.key2_addr[8] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\mips_dvc.v":117:4:117:9|Removing sequential instance imips_dvc.key2_addr[7] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\mips_dvc.v":117:4:117:9|Removing sequential instance imips_dvc.key2_addr[6] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\mips_dvc.v":117:4:117:9|Removing sequential instance imips_dvc.key2_addr[5] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\mips_dvc.v":117:4:117:9|Removing sequential instance imips_dvc.key2_addr[4] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\mips_dvc.v":117:4:117:9|Removing sequential instance imips_dvc.key2_addr[3] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\mips_dvc.v":117:4:117:9|Removing sequential instance imips_dvc.key2_addr[2] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\mips_dvc.v":117:4:117:9|Removing sequential instance imips_dvc.key2_addr[1] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\mips_dvc.v":117:4:117:9|Removing sequential instance imips_dvc.key2_addr[0] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\mips_dvc.v":117:4:117:9|Removing sequential instance imips_dvc.key1_addr[31] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\mips_dvc.v":117:4:117:9|Removing sequential instance imips_dvc.key1_addr[30] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\mips_dvc.v":117:4:117:9|Removing sequential instance imips_dvc.key1_addr[29] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\mips_dvc.v":117:4:117:9|Removing sequential instance imips_dvc.key1_addr[28] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\mips_dvc.v":117:4:117:9|Removing sequential instance imips_dvc.key1_addr[27] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\mips_dvc.v":117:4:117:9|Removing sequential instance imips_dvc.key1_addr[26] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\mips_dvc.v":117:4:117:9|Removing sequential instance imips_dvc.key1_addr[25] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\mips_dvc.v":117:4:117:9|Removing sequential instance imips_dvc.key1_addr[24] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\mips_dvc.v":117:4:117:9|Removing sequential instance imips_dvc.key1_addr[23] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\mips_dvc.v":117:4:117:9|Removing sequential instance imips_dvc.key1_addr[22] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\mips_dvc.v":117:4:117:9|Removing sequential instance imips_dvc.key1_addr[21] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\mips_dvc.v":117:4:117:9|Removing sequential instance imips_dvc.key1_addr[20] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\mips_dvc.v":117:4:117:9|Removing sequential instance imips_dvc.key1_addr[19] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\mips_dvc.v":117:4:117:9|Removing sequential instance imips_dvc.key1_addr[18] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\mips_dvc.v":117:4:117:9|Removing sequential instance imips_dvc.key1_addr[17] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\mips_dvc.v":117:4:117:9|Removing sequential instance imips_dvc.key1_addr[16] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\mips_dvc.v":117:4:117:9|Removing sequential instance imips_dvc.key1_addr[15] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\mips_dvc.v":117:4:117:9|Removing sequential instance imips_dvc.key1_addr[14] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\mips_dvc.v":117:4:117:9|Removing sequential instance imips_dvc.key1_addr[13] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\mips_dvc.v":117:4:117:9|Removing sequential instance imips_dvc.key1_addr[12] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\mips_dvc.v":117:4:117:9|Removing sequential instance imips_dvc.key1_addr[11] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\mips_dvc.v":117:4:117:9|Removing sequential instance imips_dvc.key1_addr[10] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\mips_dvc.v":117:4:117:9|Removing sequential instance imips_dvc.key1_addr[9] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\mips_dvc.v":117:4:117:9|Removing sequential instance imips_dvc.key1_addr[8] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\mips_dvc.v":117:4:117:9|Removing sequential instance imips_dvc.key1_addr[7] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\mips_dvc.v":117:4:117:9|Removing sequential instance imips_dvc.key1_addr[6] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\mips_dvc.v":117:4:117:9|Removing sequential instance imips_dvc.key1_addr[5] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\mips_dvc.v":117:4:117:9|Removing sequential instance imips_dvc.key1_addr[4] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\mips_dvc.v":117:4:117:9|Removing sequential instance imips_dvc.key1_addr[3] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\mips_dvc.v":117:4:117:9|Removing sequential instance imips_dvc.key1_addr[2] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\mips_dvc.v":117:4:117:9|Removing sequential instance imips_dvc.key1_addr[1] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\mips_dvc.v":117:4:117:9|Removing sequential instance imips_dvc.key1_addr[0] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\mips_dvc.v":117:4:117:9|Removing sequential instance imips_dvc.tmr_addr[31] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\mips_dvc.v":117:4:117:9|Removing sequential instance imips_dvc.tmr_addr[30] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\mips_dvc.v":117:4:117:9|Removing sequential instance imips_dvc.tmr_addr[29] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\mips_dvc.v":117:4:117:9|Removing sequential instance imips_dvc.tmr_addr[28] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\mips_dvc.v":117:4:117:9|Removing sequential instance imips_dvc.tmr_addr[27] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\mips_dvc.v":117:4:117:9|Removing sequential instance imips_dvc.tmr_addr[26] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\mips_dvc.v":117:4:117:9|Removing sequential instance imips_dvc.tmr_addr[25] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\mips_dvc.v":117:4:117:9|Removing sequential instance imips_dvc.tmr_addr[24] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\mips_dvc.v":117:4:117:9|Removing sequential instance imips_dvc.tmr_addr[23] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\mips_dvc.v":117:4:117:9|Removing sequential instance imips_dvc.tmr_addr[22] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\mips_dvc.v":117:4:117:9|Removing sequential instance imips_dvc.tmr_addr[21] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\mips_dvc.v":117:4:117:9|Removing sequential instance imips_dvc.tmr_addr[20] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\mips_dvc.v":117:4:117:9|Removing sequential instance imips_dvc.tmr_addr[19] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\mips_dvc.v":117:4:117:9|Removing sequential instance imips_dvc.tmr_addr[18] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\mips_dvc.v":117:4:117:9|Removing sequential instance imips_dvc.tmr_addr[17] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\mips_dvc.v":117:4:117:9|Removing sequential instance imips_dvc.tmr_addr[16] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\mips_dvc.v":117:4:117:9|Removing sequential instance imips_dvc.tmr_addr[15] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\mips_dvc.v":117:4:117:9|Removing sequential instance imips_dvc.tmr_addr[14] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\mips_dvc.v":117:4:117:9|Removing sequential instance imips_dvc.tmr_addr[13] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\mips_dvc.v":117:4:117:9|Removing sequential instance imips_dvc.tmr_addr[12] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\mips_dvc.v":117:4:117:9|Removing sequential instance imips_dvc.tmr_addr[11] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\mips_dvc.v":117:4:117:9|Removing sequential instance imips_dvc.tmr_addr[10] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\mips_dvc.v":117:4:117:9|Removing sequential instance imips_dvc.tmr_addr[9] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\mips_dvc.v":117:4:117:9|Removing sequential instance imips_dvc.tmr_addr[8] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\mips_dvc.v":117:4:117:9|Removing sequential instance imips_dvc.tmr_addr[7] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\mips_dvc.v":117:4:117:9|Removing sequential instance imips_dvc.tmr_addr[6] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\mips_dvc.v":117:4:117:9|Removing sequential instance imips_dvc.tmr_addr[5] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\mips_dvc.v":117:4:117:9|Removing sequential instance imips_dvc.tmr_addr[4] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\mips_dvc.v":117:4:117:9|Removing sequential instance imips_dvc.tmr_addr[3] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\mips_dvc.v":117:4:117:9|Removing sequential instance imips_dvc.tmr_addr[2] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\mips_dvc.v":117:4:117:9|Removing sequential instance imips_dvc.tmr_addr[1] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\mips_dvc.v":117:4:117:9|Removing sequential instance imips_dvc.tmr_addr[0] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\dvc.v":45:4:45:9|Removing sequential instance imips_dvc.mips_tmr0.itmr_d.q of view:PrimLib.dffr(prim) because there are no references to its outputs 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\ulit.v":104:111:104:116|Removing sequential instance mips_core.iRF_stage.ins_reg.r32_o[31] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\ulit.v":104:111:104:116|Removing sequential instance mips_core.iRF_stage.ins_reg.r32_o[30] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\ulit.v":104:111:104:116|Removing sequential instance mips_core.iRF_stage.ins_reg.r32_o[29] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\ulit.v":104:111:104:116|Removing sequential instance mips_core.iRF_stage.ins_reg.r32_o[28] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\ulit.v":104:111:104:116|Removing sequential instance mips_core.iRF_stage.ins_reg.r32_o[27] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\ulit.v":104:111:104:116|Removing sequential instance mips_core.iRF_stage.ins_reg.r32_o[26] of view:PrimLib.dff(prim) because there are no references to its outputs 
Warning: Found 28 combinational loops!
         Each loop is reported with an instance in the loop
         and nets connected to that instance.
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
1) instance mips_core.decoder_pipe.idecoder.fsm_dly_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.fsm_dly_1[0], output net "mips_core.BUS197[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.fsm_dly_2[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
2) instance mips_core.decoder_pipe.idecoder.ext_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.ext_ctl_1[0], output net "mips_core.decoder_pipe.BUS2072[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.N_1373" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
3) instance mips_core.decoder_pipe.idecoder.ext_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.ext_ctl_1[1], output net "mips_core.decoder_pipe.BUS2072[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.N_1374" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
4) instance mips_core.decoder_pipe.idecoder.ext_ctl_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.ext_ctl_1[2], output net "mips_core.decoder_pipe.BUS2072[2]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.ext_ctl_2[2]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
5) instance mips_core.decoder_pipe.idecoder.rd_sel_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.rd_sel_1[0], output net "mips_core.decoder_pipe.BUS2110[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.rd_sel_2[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
6) instance mips_core.decoder_pipe.idecoder.rd_sel_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.rd_sel_1[1], output net "mips_core.decoder_pipe.BUS2110[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.rd_sel_2[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_438" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.fsm_dly373" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
7) instance mips_core.decoder_pipe.idecoder.cmp_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.cmp_ctl_1[0], output net "mips_core.decoder_pipe.BUS2056[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.cmp_ctl_2[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
8) instance mips_core.decoder_pipe.idecoder.cmp_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.cmp_ctl_1[1], output net "mips_core.decoder_pipe.BUS2056[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.cmp_ctl_2[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
9) instance mips_core.decoder_pipe.idecoder.cmp_ctl_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.cmp_ctl_1[2], output net "mips_core.decoder_pipe.BUS2056[2]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.cmp_ctl_2[2]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
10) instance mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[0], output net "mips_core.decoder_pipe.BUS2102[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.N_1376" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
11) instance mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[1], output net "mips_core.decoder_pipe.BUS2102[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.pc_gen_ctl_2[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
12) instance mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[2], output net "mips_core.decoder_pipe.BUS2102[2]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.N_1260_i" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
13) instance mips_core.decoder_pipe.idecoder.muxa_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxa_ctl_1[0], output net "mips_core.decoder_pipe.BUS2086[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.muxa_ctl_2[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
14) instance mips_core.decoder_pipe.idecoder.muxa_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxa_ctl_1[1], output net "mips_core.decoder_pipe.BUS2086[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.muxa_ctl_2[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
15) instance mips_core.decoder_pipe.idecoder.muxb_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxb_ctl_1[0], output net "mips_core.decoder_pipe.BUS2094[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.muxb_ctl_2[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
16) instance mips_core.decoder_pipe.idecoder.muxb_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxb_ctl_1[1], output net "mips_core.decoder_pipe.BUS2094[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.muxb_ctl_2[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
17) instance mips_core.decoder_pipe.idecoder.alu_func_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[0], output net "mips_core.decoder_pipe.BUS2040[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.alu_func_2[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
18) instance mips_core.decoder_pipe.idecoder.alu_func_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[1], output net "mips_core.decoder_pipe.BUS2040[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.alu_func_2[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
19) instance mips_core.decoder_pipe.idecoder.alu_func_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[2], output net "mips_core.decoder_pipe.BUS2040[2]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.N_1372" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
20) instance mips_core.decoder_pipe.idecoder.alu_func_1[3] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[3], output net "mips_core.decoder_pipe.BUS2040[3]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.alu_func_2[3]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
21) instance mips_core.decoder_pipe.idecoder.alu_func_1[4] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[4], output net "mips_core.decoder_pipe.BUS2040[4]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.alu_func_2[4]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
22) instance mips_core.decoder_pipe.idecoder.dmem_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[0], output net "mips_core.decoder_pipe.BUS2064[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
23) instance mips_core.decoder_pipe.idecoder.dmem_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[1], output net "mips_core.decoder_pipe.BUS2064[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_438" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.fsm_dly373" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
24) instance mips_core.decoder_pipe.idecoder.dmem_ctl_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[2], output net "mips_core.decoder_pipe.BUS2064[2]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[2]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_18_m" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_15" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
25) instance mips_core.decoder_pipe.idecoder.dmem_ctl_1[3] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[3], output net "mips_core.decoder_pipe.BUS2064[3]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[3]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
26) instance mips_core.decoder_pipe.idecoder.alu_we[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_we[0], output net "mips_core.decoder_pipe.BUS2048[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.alu_we_1[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
27) instance mips_core.decoder_pipe.idecoder.wb_mux[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.wb_mux[0], output net "mips_core.decoder_pipe.BUS2118[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.wb_mux_1[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
28) instance mips_core.decoder_pipe.idecoder.wb_we[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.wb_we[0], output net "mips_core.decoder_pipe.BUS2126[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.wb_we_1[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
End of loops
Warning: Found 28 combinational loops!
         Each loop is reported with an instance in the loop
         and nets connected to that instance.
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
1) instance mips_core.decoder_pipe.idecoder.fsm_dly_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.fsm_dly_1[0], output net "mips_core.BUS197[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.fsm_dly_2[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
2) instance mips_core.decoder_pipe.idecoder.ext_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.ext_ctl_1[0], output net "mips_core.decoder_pipe.BUS2072[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.N_1373" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
3) instance mips_core.decoder_pipe.idecoder.ext_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.ext_ctl_1[1], output net "mips_core.decoder_pipe.BUS2072[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.N_1374" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
4) instance mips_core.decoder_pipe.idecoder.ext_ctl_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.ext_ctl_1[2], output net "mips_core.decoder_pipe.BUS2072[2]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.ext_ctl_2[2]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
5) instance mips_core.decoder_pipe.idecoder.rd_sel_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.rd_sel_1[0], output net "mips_core.decoder_pipe.BUS2110[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.rd_sel_2[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
6) instance mips_core.decoder_pipe.idecoder.rd_sel_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.rd_sel_1[1], output net "mips_core.decoder_pipe.BUS2110[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.rd_sel_2[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_438" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.fsm_dly373" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
7) instance mips_core.decoder_pipe.idecoder.cmp_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.cmp_ctl_1[0], output net "mips_core.decoder_pipe.BUS2056[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.cmp_ctl_2[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
8) instance mips_core.decoder_pipe.idecoder.cmp_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.cmp_ctl_1[1], output net "mips_core.decoder_pipe.BUS2056[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.cmp_ctl_2[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
9) instance mips_core.decoder_pipe.idecoder.cmp_ctl_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.cmp_ctl_1[2], output net "mips_core.decoder_pipe.BUS2056[2]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.cmp_ctl_2[2]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
10) instance mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[0], output net "mips_core.decoder_pipe.BUS2102[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.N_1376" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
11) instance mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[1], output net "mips_core.decoder_pipe.BUS2102[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.pc_gen_ctl_2[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
12) instance mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[2], output net "mips_core.decoder_pipe.BUS2102[2]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.N_1260_i" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
13) instance mips_core.decoder_pipe.idecoder.muxa_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxa_ctl_1[0], output net "mips_core.decoder_pipe.BUS2086[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.muxa_ctl_2[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
14) instance mips_core.decoder_pipe.idecoder.muxa_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxa_ctl_1[1], output net "mips_core.decoder_pipe.BUS2086[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.muxa_ctl_2[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
15) instance mips_core.decoder_pipe.idecoder.muxb_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxb_ctl_1[0], output net "mips_core.decoder_pipe.BUS2094[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.muxb_ctl_2[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
16) instance mips_core.decoder_pipe.idecoder.muxb_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxb_ctl_1[1], output net "mips_core.decoder_pipe.BUS2094[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.muxb_ctl_2[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
17) instance mips_core.decoder_pipe.idecoder.alu_func_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[0], output net "mips_core.decoder_pipe.BUS2040[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.alu_func_2[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
18) instance mips_core.decoder_pipe.idecoder.alu_func_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[1], output net "mips_core.decoder_pipe.BUS2040[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.alu_func_2[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
19) instance mips_core.decoder_pipe.idecoder.alu_func_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[2], output net "mips_core.decoder_pipe.BUS2040[2]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.N_1372" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
20) instance mips_core.decoder_pipe.idecoder.alu_func_1[3] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[3], output net "mips_core.decoder_pipe.BUS2040[3]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.alu_func_2[3]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
21) instance mips_core.decoder_pipe.idecoder.alu_func_1[4] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[4], output net "mips_core.decoder_pipe.BUS2040[4]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.alu_func_2[4]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
22) instance mips_core.decoder_pipe.idecoder.dmem_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[0], output net "mips_core.decoder_pipe.BUS2064[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
23) instance mips_core.decoder_pipe.idecoder.dmem_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[1], output net "mips_core.decoder_pipe.BUS2064[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_438" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.fsm_dly373" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
24) instance mips_core.decoder_pipe.idecoder.dmem_ctl_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[2], output net "mips_core.decoder_pipe.BUS2064[2]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[2]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_18_m" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_15" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
25) instance mips_core.decoder_pipe.idecoder.dmem_ctl_1[3] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[3], output net "mips_core.decoder_pipe.BUS2064[3]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[3]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
26) instance mips_core.decoder_pipe.idecoder.alu_we[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_we[0], output net "mips_core.decoder_pipe.BUS2048[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.alu_we_1[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
27) instance mips_core.decoder_pipe.idecoder.wb_mux[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.wb_mux[0], output net "mips_core.decoder_pipe.BUS2118[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.wb_mux_1[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
28) instance mips_core.decoder_pipe.idecoder.wb_we[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.wb_we[0], output net "mips_core.decoder_pipe.BUS2126[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.wb_we_1[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
End of loops
Warning: Found 28 combinational loops!
         Each loop is reported with an instance in the loop
         and nets connected to that instance.
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
1) instance mips_core.decoder_pipe.idecoder.fsm_dly_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.fsm_dly_1[0], output net "mips_core.BUS197[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.fsm_dly_2[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
2) instance mips_core.decoder_pipe.idecoder.ext_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.ext_ctl_1[0], output net "mips_core.decoder_pipe.BUS2072[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.N_1373" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
3) instance mips_core.decoder_pipe.idecoder.ext_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.ext_ctl_1[1], output net "mips_core.decoder_pipe.BUS2072[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.N_1374" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
4) instance mips_core.decoder_pipe.idecoder.ext_ctl_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.ext_ctl_1[2], output net "mips_core.decoder_pipe.BUS2072[2]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.ext_ctl_2[2]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
5) instance mips_core.decoder_pipe.idecoder.rd_sel_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.rd_sel_1[0], output net "mips_core.decoder_pipe.BUS2110[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.rd_sel_2[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
6) instance mips_core.decoder_pipe.idecoder.rd_sel_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.rd_sel_1[1], output net "mips_core.decoder_pipe.BUS2110[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.rd_sel_2[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_438" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.fsm_dly373" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
7) instance mips_core.decoder_pipe.idecoder.cmp_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.cmp_ctl_1[0], output net "mips_core.decoder_pipe.BUS2056[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.cmp_ctl_2[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
8) instance mips_core.decoder_pipe.idecoder.cmp_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.cmp_ctl_1[1], output net "mips_core.decoder_pipe.BUS2056[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.cmp_ctl_2[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
9) instance mips_core.decoder_pipe.idecoder.cmp_ctl_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.cmp_ctl_1[2], output net "mips_core.decoder_pipe.BUS2056[2]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.cmp_ctl_2[2]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
10) instance mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[0], output net "mips_core.decoder_pipe.BUS2102[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.N_1376" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
11) instance mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[1], output net "mips_core.decoder_pipe.BUS2102[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.pc_gen_ctl_2[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
12) instance mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[2], output net "mips_core.decoder_pipe.BUS2102[2]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.N_1260_i" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
13) instance mips_core.decoder_pipe.idecoder.muxa_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxa_ctl_1[0], output net "mips_core.decoder_pipe.BUS2086[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.muxa_ctl_2[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
14) instance mips_core.decoder_pipe.idecoder.muxa_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxa_ctl_1[1], output net "mips_core.decoder_pipe.BUS2086[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.muxa_ctl_2[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
15) instance mips_core.decoder_pipe.idecoder.muxb_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxb_ctl_1[0], output net "mips_core.decoder_pipe.BUS2094[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.muxb_ctl_2[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
16) instance mips_core.decoder_pipe.idecoder.muxb_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxb_ctl_1[1], output net "mips_core.decoder_pipe.BUS2094[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.muxb_ctl_2[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
17) instance mips_core.decoder_pipe.idecoder.alu_func_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[0], output net "mips_core.decoder_pipe.BUS2040[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.alu_func_2[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
18) instance mips_core.decoder_pipe.idecoder.alu_func_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[1], output net "mips_core.decoder_pipe.BUS2040[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.alu_func_2[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
19) instance mips_core.decoder_pipe.idecoder.alu_func_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[2], output net "mips_core.decoder_pipe.BUS2040[2]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.N_1372" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
20) instance mips_core.decoder_pipe.idecoder.alu_func_1[3] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[3], output net "mips_core.decoder_pipe.BUS2040[3]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.alu_func_2[3]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
21) instance mips_core.decoder_pipe.idecoder.alu_func_1[4] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[4], output net "mips_core.decoder_pipe.BUS2040[4]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.alu_func_2[4]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
22) instance mips_core.decoder_pipe.idecoder.dmem_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[0], output net "mips_core.decoder_pipe.BUS2064[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
23) instance mips_core.decoder_pipe.idecoder.dmem_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[1], output net "mips_core.decoder_pipe.BUS2064[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_438" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.fsm_dly373" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
24) instance mips_core.decoder_pipe.idecoder.dmem_ctl_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[2], output net "mips_core.decoder_pipe.BUS2064[2]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[2]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_18_m" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_15" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
25) instance mips_core.decoder_pipe.idecoder.dmem_ctl_1[3] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[3], output net "mips_core.decoder_pipe.BUS2064[3]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[3]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
26) instance mips_core.decoder_pipe.idecoder.alu_we[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_we[0], output net "mips_core.decoder_pipe.BUS2048[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.alu_we_1[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
27) instance mips_core.decoder_pipe.idecoder.wb_mux[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.wb_mux[0], output net "mips_core.decoder_pipe.BUS2118[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.wb_mux_1[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
28) instance mips_core.decoder_pipe.idecoder.wb_we[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.wb_we[0], output net "mips_core.decoder_pipe.BUS2126[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.wb_we_1[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
End of loops
Warning: Found 28 combinational loops!
         Each loop is reported with an instance in the loop
         and nets connected to that instance.
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
1) instance mips_core.decoder_pipe.idecoder.fsm_dly_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.fsm_dly_1[0], output net "mips_core.BUS197[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.fsm_dly_2[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
2) instance mips_core.decoder_pipe.idecoder.ext_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.ext_ctl_1[0], output net "mips_core.decoder_pipe.BUS2072[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.N_1373" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
3) instance mips_core.decoder_pipe.idecoder.ext_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.ext_ctl_1[1], output net "mips_core.decoder_pipe.BUS2072[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.N_1374" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
4) instance mips_core.decoder_pipe.idecoder.ext_ctl_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.ext_ctl_1[2], output net "mips_core.decoder_pipe.BUS2072[2]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.ext_ctl_2[2]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
5) instance mips_core.decoder_pipe.idecoder.rd_sel_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.rd_sel_1[0], output net "mips_core.decoder_pipe.BUS2110[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.rd_sel_2[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
6) instance mips_core.decoder_pipe.idecoder.rd_sel_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.rd_sel_1[1], output net "mips_core.decoder_pipe.BUS2110[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.rd_sel_2[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_438" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.fsm_dly373" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
7) instance mips_core.decoder_pipe.idecoder.cmp_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.cmp_ctl_1[0], output net "mips_core.decoder_pipe.BUS2056[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.cmp_ctl_2[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
8) instance mips_core.decoder_pipe.idecoder.cmp_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.cmp_ctl_1[1], output net "mips_core.decoder_pipe.BUS2056[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.cmp_ctl_2[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
9) instance mips_core.decoder_pipe.idecoder.cmp_ctl_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.cmp_ctl_1[2], output net "mips_core.decoder_pipe.BUS2056[2]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.cmp_ctl_2[2]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
10) instance mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[0], output net "mips_core.decoder_pipe.BUS2102[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.N_1376" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
11) instance mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[1], output net "mips_core.decoder_pipe.BUS2102[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.pc_gen_ctl_2[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
12) instance mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[2], output net "mips_core.decoder_pipe.BUS2102[2]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.N_1260_i" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
13) instance mips_core.decoder_pipe.idecoder.muxa_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxa_ctl_1[0], output net "mips_core.decoder_pipe.BUS2086[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.muxa_ctl_2[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
14) instance mips_core.decoder_pipe.idecoder.muxa_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxa_ctl_1[1], output net "mips_core.decoder_pipe.BUS2086[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.muxa_ctl_2[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
15) instance mips_core.decoder_pipe.idecoder.muxb_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxb_ctl_1[0], output net "mips_core.decoder_pipe.BUS2094[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.muxb_ctl_2[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
16) instance mips_core.decoder_pipe.idecoder.muxb_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxb_ctl_1[1], output net "mips_core.decoder_pipe.BUS2094[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.muxb_ctl_2[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
17) instance mips_core.decoder_pipe.idecoder.alu_func_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[0], output net "mips_core.decoder_pipe.BUS2040[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.alu_func_2[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
18) instance mips_core.decoder_pipe.idecoder.alu_func_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[1], output net "mips_core.decoder_pipe.BUS2040[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.alu_func_2[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
19) instance mips_core.decoder_pipe.idecoder.alu_func_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[2], output net "mips_core.decoder_pipe.BUS2040[2]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.N_1372" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
20) instance mips_core.decoder_pipe.idecoder.alu_func_1[3] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[3], output net "mips_core.decoder_pipe.BUS2040[3]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.alu_func_2[3]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
21) instance mips_core.decoder_pipe.idecoder.alu_func_1[4] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[4], output net "mips_core.decoder_pipe.BUS2040[4]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.alu_func_2[4]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
22) instance mips_core.decoder_pipe.idecoder.dmem_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[0], output net "mips_core.decoder_pipe.BUS2064[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
23) instance mips_core.decoder_pipe.idecoder.dmem_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[1], output net "mips_core.decoder_pipe.BUS2064[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_438" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.fsm_dly373" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
24) instance mips_core.decoder_pipe.idecoder.dmem_ctl_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[2], output net "mips_core.decoder_pipe.BUS2064[2]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[2]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_18_m" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_15" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
25) instance mips_core.decoder_pipe.idecoder.dmem_ctl_1[3] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[3], output net "mips_core.decoder_pipe.BUS2064[3]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[3]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
26) instance mips_core.decoder_pipe.idecoder.alu_we[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_we[0], output net "mips_core.decoder_pipe.BUS2048[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.alu_we_1[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
27) instance mips_core.decoder_pipe.idecoder.wb_mux[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.wb_mux[0], output net "mips_core.decoder_pipe.BUS2118[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.wb_mux_1[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping
28) instance mips_core.decoder_pipe.idecoder.wb_we[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.wb_we[0], output net "mips_core.decoder_pipe.BUS2126[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.wb_we_1[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
End of loops
Warning: Found 28 combinational loops!
         Each loop is reported with an instance in the loop
         and nets connected to that instance.
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.BUS197[0]
1) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.fsm_dly_1[0], output net "mips_core.BUS197[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.fsm_dly_2[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2072[0]
2) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.ext_ctl_1[0], output net "mips_core.decoder_pipe.BUS2072[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.N_1373" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2072[1]
3) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.ext_ctl_1[1], output net "mips_core.decoder_pipe.BUS2072[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.N_1374" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2072[2]
4) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.ext_ctl_1[2], output net "mips_core.decoder_pipe.BUS2072[2]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.ext_ctl_2[2]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2110[0]
5) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.rd_sel_1[0], output net "mips_core.decoder_pipe.BUS2110[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.rd_sel_2[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2110[1]
6) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.rd_sel_1[1], output net "mips_core.decoder_pipe.BUS2110[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.rd_sel_2[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_438" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.fsm_dly373" in work.mips_sys(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2056[0]
7) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.cmp_ctl_1[0], output net "mips_core.decoder_pipe.BUS2056[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.cmp_ctl_2[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2056[1]
8) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.cmp_ctl_1[1], output net "mips_core.decoder_pipe.BUS2056[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.cmp_ctl_2[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2056[2]
9) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.cmp_ctl_1[2], output net "mips_core.decoder_pipe.BUS2056[2]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.cmp_ctl_2[2]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2102[0]
10) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[0], output net "mips_core.decoder_pipe.BUS2102[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.N_1376" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2102[1]
11) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[1], output net "mips_core.decoder_pipe.BUS2102[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.pc_gen_ctl_2[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2102[2]
12) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[2], output net "mips_core.decoder_pipe.BUS2102[2]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.N_1260_i_0" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2086[0]
13) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxa_ctl_1[0], output net "mips_core.decoder_pipe.BUS2086[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.muxa_ctl_2[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2086[1]
14) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxa_ctl_1[1], output net "mips_core.decoder_pipe.BUS2086[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.muxa_ctl_2[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2094[0]
15) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxb_ctl_1[0], output net "mips_core.decoder_pipe.BUS2094[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.muxb_ctl_2[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2094[1]
16) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxb_ctl_1[1], output net "mips_core.decoder_pipe.BUS2094[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.muxb_ctl_2[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2040[0]
17) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[0], output net "mips_core.decoder_pipe.BUS2040[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.alu_func_2[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2040[1]
18) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[1], output net "mips_core.decoder_pipe.BUS2040[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.alu_func_2[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2040[2]
19) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[2], output net "mips_core.decoder_pipe.BUS2040[2]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.N_1372" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2040[3]
20) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[3], output net "mips_core.decoder_pipe.BUS2040[3]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.alu_func_2[3]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2040[4]
21) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[4], output net "mips_core.decoder_pipe.BUS2040[4]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.alu_func_2[4]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2064[0]
22) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[0], output net "mips_core.decoder_pipe.BUS2064[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2064[1]
23) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[1], output net "mips_core.decoder_pipe.BUS2064[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_438" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.fsm_dly373" in work.mips_sys(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2064[2]
24) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[2], output net "mips_core.decoder_pipe.BUS2064[2]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[2]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_18_m" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_15" in work.mips_sys(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2064[3]
25) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[3], output net "mips_core.decoder_pipe.BUS2064[3]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[3]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2048[0]
26) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_we[0], output net "mips_core.decoder_pipe.BUS2048[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.alu_we_1[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2118[0]
27) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.wb_mux[0], output net "mips_core.decoder_pipe.BUS2118[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.wb_mux_1[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2126[0]
28) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.wb_we[0], output net "mips_core.decoder_pipe.BUS2126[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.wb_we_1[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
End of loops
@N: MF197 |Retiming summary : 0 registers retimed to 0 

                #####  BEGIN RETIMING REPORT  #####

Retiming summary : 0 registers retimed to 0

Original and Pipelined registers replaced by retiming :
                None

New registers created by retiming :
                None


                #####   END RETIMING REPORT  #####

Warning: Found 28 combinational loops!
         Each loop is reported with an instance in the loop
         and nets connected to that instance.
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.idecoder.fsm_dly_2_0_0[0]
1) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.fsm_dly_2_0_0[0], output net "mips_core.decoder_pipe.idecoder.fsm_dly_2_0_0[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.BUS197[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.ext_ctl_2_0_0_a3_1_0[2]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.ext_ctl_2_0_0_o3[2]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.fsm_dly_2_0_0_a[0]" in work.mips_sys(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.idecoder.wb_mux_1_0_0[0]
2) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.wb_mux_1_0_0[0], output net "mips_core.decoder_pipe.idecoder.wb_mux_1_0_0[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0_a2_0[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.BUS2118[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.wb_mux_1_0_0_a3[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.fsm_dly_2_0_0_o2_x[2]" in work.mips_sys(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.idecoder.wb_we_1_0_0[0]
3) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.wb_we_1_0_0[0], output net "mips_core.decoder_pipe.idecoder.wb_we_1_0_0[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.wb_we_1_0_0_a[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.wb_mux_1_0_0_a3[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.ext_ctl_2_i_m3_0_a2_x[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.fsm_dly350_1_0_a2_0_a3_0_o2_x" in work.mips_sys(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.idecoder.alu_func_2_0_0[0]
4) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_2_0_0[0], output net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "zz_ins_i_c[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0_a[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0_3[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0_o2_x[0]" in work.mips_sys(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.idecoder.alu_func_2_0_0[1]
5) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_2_0_0[1], output net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0_a2_x[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0_a3_1[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0_o2_x[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0_a[1]" in work.mips_sys(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.idecoder.alu_func_2_0_0_x[3]
6) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_2_0_0_x[3], output net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0_x[3]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0_a3_1[3]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0_1[3]" in work.mips_sys(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.idecoder.alu_func_2_0_0[4]
7) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_2_0_0[4], output net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0[4]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.BUS2040[4]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0_a2_3[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0_2[4]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0_a[4]" in work.mips_sys(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.idecoder.alu_we_1_0_0[0]
8) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_we_1_0_0[0], output net "mips_core.decoder_pipe.idecoder.alu_we_1_0_0[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "zz_ins_i_c[29]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.alu_we_1_0_0_0[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.alu_we_1_0_0_a3[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.alu_we_1_0_0_a[0]" in work.mips_sys(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.idecoder.ext_ctl_2_0_0[2]
9) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.ext_ctl_2_0_0[2], output net "mips_core.decoder_pipe.idecoder.ext_ctl_2_0_0[2]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.BUS2072[2]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.ext_ctl_2_0_0_a3_1_0[2]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.ext_ctl_2_0_0_o3[2]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.ext_ctl_2_0_0_a[2]" in work.mips_sys(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.idecoder.muxa_ctl_2_0_0[0]
10) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxa_ctl_2_0_0[0], output net "mips_core.decoder_pipe.idecoder.muxa_ctl_2_0_0[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0_a2_0[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0_o2_x[3]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.ext_ctl_2_0_0_a2_2[2]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.muxa_ctl_2_0_0_a[0]" in work.mips_sys(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.idecoder.muxa_ctl_2_0_0[1]
11) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxa_ctl_2_0_0[1], output net "mips_core.decoder_pipe.idecoder.muxa_ctl_2_0_0[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "zz_ins_i_c[29]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0_o2_x[4]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.muxa_ctl_2_0_0_0[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.muxa_ctl_2_0_0_a[1]" in work.mips_sys(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.idecoder.muxb_ctl_2_0_0[0]
12) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxb_ctl_2_0_0[0], output net "mips_core.decoder_pipe.idecoder.muxb_ctl_2_0_0[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "zz_ins_i_c[4]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.muxa_ctl_2_0_0_a3_1[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.muxb_ctl_2_0_0_a[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.muxb_ctl_2_0_0_a3_0_0_x[0]" in work.mips_sys(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.idecoder.muxb_ctl_2_0_0[1]
13) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxb_ctl_2_0_0[1], output net "mips_core.decoder_pipe.idecoder.muxb_ctl_2_0_0[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.BUS2094[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0_a2_2_x[3]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.fsm_dly_2_0_0_o2_x[2]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.muxb_ctl_2_0_0_a[1]" in work.mips_sys(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.idecoder.pc_gen_ctl_2_0_0[1]
14) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.pc_gen_ctl_2_0_0[1], output net "mips_core.decoder_pipe.idecoder.pc_gen_ctl_2_0_0[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0_a2_0[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.BUS2102[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.fsm_dly_2_0_0_o2_x[2]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.pc_gen_ctl_2_0_0_0[1]" in work.mips_sys(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.idecoder.rd_sel_2_0_0[0]
15) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.rd_sel_2_0_0[0], output net "mips_core.decoder_pipe.idecoder.rd_sel_2_0_0[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.BUS2110[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0_a2_3[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.rd_sel_2_0_0_a[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0_a3_1[1]" in work.mips_sys(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.idecoder.rd_sel_2_0_0[1]
16) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.rd_sel_2_0_0[1], output net "mips_core.decoder_pipe.idecoder.rd_sel_2_0_0[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.rd_sel_2_0_0_a[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.muxb_ctl_2_0_0_o3[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0_a2_0_x[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0_a2_x[4]" in work.mips_sys(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.idecoder.cmp_ctl_2_0_0[0]
17) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.cmp_ctl_2_0_0[0], output net "mips_core.decoder_pipe.idecoder.cmp_ctl_2_0_0[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0_a2_0[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.cmp_ctl_2_0_0_a2_1[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.BUS2056[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.cmp_ctl_2_0_0_1[0]" in work.mips_sys(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.idecoder.cmp_ctl_2_0_0[1]
18) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.cmp_ctl_2_0_0[1], output net "mips_core.decoder_pipe.idecoder.cmp_ctl_2_0_0[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.BUS2056[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.cmp_ctl_2_0_0_a2_0[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0_a2_0[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.cmp_ctl_2_0_0_a[1]" in work.mips_sys(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.idecoder.cmp_ctl_2_0_0[2]
19) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.cmp_ctl_2_0_0[2], output net "mips_core.decoder_pipe.idecoder.cmp_ctl_2_0_0[2]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0_a2_0[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.cmp_ctl_2_0_0_a2_x[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0_a2_0_x[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.cmp_ctl_2_0_0_a[2]" in work.mips_sys(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.idecoder.dmem_ctl_2_0_0[0]
20) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_2_0_0[0], output net "mips_core.decoder_pipe.idecoder.dmem_ctl_2_0_0[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.BUS2064[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0_a2_0[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.fsm_dly_2_0_0_o2_x[2]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0_a2_0_x[4]" in work.mips_sys(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.idecoder.dmem_ctl_2_0_0[1]
21) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_2_0_0[1], output net "mips_core.decoder_pipe.idecoder.dmem_ctl_2_0_0[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.BUS2064[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.wb_mux_1_0_0_a2_x[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.dmem_ctl_2_0_0_a3_1[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.dmem_ctl_2_0_0_a[1]" in work.mips_sys(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.idecoder.dmem_ctl_2_0_0[2]
22) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_2_0_0[2], output net "mips_core.decoder_pipe.idecoder.dmem_ctl_2_0_0[2]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.BUS2064[2]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.wb_mux_1_0_0_a2_x[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.dmem_ctl_2_0_0_a3_0[2]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.dmem_ctl_2_0_0_a[2]" in work.mips_sys(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.idecoder.dmem_ctl_2_0_0[3]
23) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_2_0_0[3], output net "mips_core.decoder_pipe.idecoder.dmem_ctl_2_0_0[3]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.BUS2064[3]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0_a2_0[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.fsm_dly_2_0_0_o2_x[2]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.dmem_ctl_2_0_0_a[3]" in work.mips_sys(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.idecoder.pc_gen_ctl_2_i_0[2]
24) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.pc_gen_ctl_2_i_0[2], output net "mips_core.decoder_pipe.idecoder.pc_gen_ctl_2_i_0[2]" in work.mips_sys(verilog)
    input nets to instance:
        net "zz_ins_i_c[2]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.pc_gen_ctl_2_i_0_a3_0_0[2]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.pc_gen_ctl_2_i_0_a[2]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.pc_gen_ctl_2_i_0_4[2]" in work.mips_sys(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.idecoder.alu_func_2_i_m3_0[2]
25) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_2_i_m3_0[2], output net "mips_core.decoder_pipe.idecoder.alu_func_2_i_m3_0[2]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0_a3_1[3]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.alu_func_2_i_m3_0_3[2]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.alu_func_2_i_m3_0_a3_5[2]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.alu_func_2_i_m3_0_a[2]" in work.mips_sys(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.idecoder.ext_ctl_2_i_m3_0[0]
26) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.ext_ctl_2_i_m3_0[0], output net "mips_core.decoder_pipe.idecoder.ext_ctl_2_i_m3_0[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "mips_core.decoder_pipe.idecoder.wb_mux_1_0_0_a3[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.fsm_dly_2_0_0_a3_0[2]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.ext_ctl_2_i_m3_0_a[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.ext_ctl_2_i_m3_0_2[0]" in work.mips_sys(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.idecoder.ext_ctl_2_i_m3_0[1]
27) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.ext_ctl_2_i_m3_0[1], output net "mips_core.decoder_pipe.idecoder.ext_ctl_2_i_m3_0[1]" in work.mips_sys(verilog)
    input nets to instance:
        net "zz_ins_i_c[29]" in work.mips_sys(verilog)
        net "zz_ins_i_c[28]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0_a2_0_x[0]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.ext_ctl_2_i_m3_0_a[1]" in work.mips_sys(verilog)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net mips_core.decoder_pipe.idecoder.pc_gen_ctl_2_i_m3_0[0]
28) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.pc_gen_ctl_2_i_m3_0[0], output net "mips_core.decoder_pipe.idecoder.pc_gen_ctl_2_i_m3_0[0]" in work.mips_sys(verilog)
    input nets to instance:
        net "zz_ins_i_c[4]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0_a2_x[4]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.muxa_ctl_2_0_0_o2_0[1]" in work.mips_sys(verilog)
        net "mips_core.decoder_pipe.idecoder.pc_gen_ctl_2_i_m3_0_5[0]" in work.mips_sys(verilog)
End of loops

Writing Analyst data base E:\mips789\mips789\synplify_prj\rev_1\fifo512_cyclone.srm
Warning: Found 28 combinational loops!
         Each loop is reported with an instance in the loop
         and nets connected to that instance.
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net wb_mux_1_0_0_0
1) instance work.decoder(netlist)-wb_mux_1_0_0[0], output net "wb_mux_1_0_0_0" in work.decoder(netlist)
    input nets to instance:
        net "alu_func_2_0_0_a2_0[1]" in work.decoder(netlist)
        net "BUS2118_0" in work.decoder(netlist)
        net "wb_mux_1_0_0_a3[0]" in work.decoder(netlist)
        net "fsm_dly_2_0_0_o2_x[2]" in work.decoder(netlist)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net wb_we_1_0_0_0
2) instance work.decoder(netlist)-wb_we_1_0_0[0], output net "wb_we_1_0_0_0" in work.decoder(netlist)
    input nets to instance:
        net "wb_we_1_0_0_a[0]" in work.decoder(netlist)
        net "wb_mux_1_0_0_a3[0]" in work.decoder(netlist)
        net "ext_ctl_2_i_m3_0_a2_x[1]" in work.decoder(netlist)
        net "fsm_dly350_1_0_a2_0_a3_0_o2_x" in work.decoder(netlist)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net rd_sel_2_0_0_1
3) instance work.decoder(netlist)-rd_sel_2_0_0[1], output net "rd_sel_2_0_0_1" in work.decoder(netlist)
    input nets to instance:
        net "rd_sel_2_0_0_a[1]" in work.decoder(netlist)
        net "muxb_ctl_2_0_0_o3[1]" in work.decoder(netlist)
        net "alu_func_2_0_0_a2_0_x[0]" in work.decoder(netlist)
        net "alu_func_2_0_0_a2_x[4]" in work.decoder(netlist)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net rd_sel_2_0_0_0
4) instance work.decoder(netlist)-rd_sel_2_0_0[0], output net "rd_sel_2_0_0_0" in work.decoder(netlist)
    input nets to instance:
        net "BUS2110_0" in work.decoder(netlist)
        net "alu_func_2_0_0_a2_3[1]" in work.decoder(netlist)
        net "rd_sel_2_0_0_a[0]" in work.decoder(netlist)
        net "alu_func_2_0_0_a3_1[1]" in work.decoder(netlist)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net pc_gen_ctl_2_0_0_0
5) instance work.decoder(netlist)-pc_gen_ctl_2_0_0[1], output net "pc_gen_ctl_2_0_0_0" in work.decoder(netlist)
    input nets to instance:
        net "alu_func_2_0_0_a2_0[1]" in work.decoder(netlist)
        net "BUS2102_1" in work.decoder(netlist)
        net "fsm_dly_2_0_0_o2_x[2]" in work.decoder(netlist)
        net "pc_gen_ctl_2_0_0_0[1]" in work.decoder(netlist)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net muxb_ctl_2_0_0_1
6) instance work.decoder(netlist)-muxb_ctl_2_0_0[1], output net "muxb_ctl_2_0_0_1" in work.decoder(netlist)
    input nets to instance:
        net "BUS2094_1" in work.decoder(netlist)
        net "alu_func_2_0_0_a2_2_x[3]" in work.decoder(netlist)
        net "fsm_dly_2_0_0_o2_x[2]" in work.decoder(netlist)
        net "muxb_ctl_2_0_0_a[1]" in work.decoder(netlist)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net muxb_ctl_2_0_0_0
7) instance work.decoder(netlist)-muxb_ctl_2_0_0[0], output net "muxb_ctl_2_0_0_0" in work.decoder(netlist)
    input nets to instance:
        net "zz_ins_i_c_4" in work.decoder(netlist)
        net "muxa_ctl_2_0_0_a3_1[0]" in work.decoder(netlist)
        net "muxb_ctl_2_0_0_a[0]" in work.decoder(netlist)
        net "muxb_ctl_2_0_0_a3_0_0_x[0]" in work.decoder(netlist)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net dmem_ctl_2_0_0_3
8) instance work.decoder(netlist)-dmem_ctl_2_0_0[3], output net "dmem_ctl_2_0_0_3" in work.decoder(netlist)
    input nets to instance:
        net "BUS2064_3" in work.decoder(netlist)
        net "alu_func_2_0_0_a2_0[1]" in work.decoder(netlist)
        net "fsm_dly_2_0_0_o2_x[2]" in work.decoder(netlist)
        net "dmem_ctl_2_0_0_a[3]" in work.decoder(netlist)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net dmem_ctl_2_0_0_2
9) instance work.decoder(netlist)-dmem_ctl_2_0_0[2], output net "dmem_ctl_2_0_0_2" in work.decoder(netlist)
    input nets to instance:
        net "BUS2064_2" in work.decoder(netlist)
        net "wb_mux_1_0_0_a2_x[0]" in work.decoder(netlist)
        net "dmem_ctl_2_0_0_a3_0[2]" in work.decoder(netlist)
        net "dmem_ctl_2_0_0_a[2]" in work.decoder(netlist)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net dmem_ctl_2_0_0_0
10) instance work.decoder(netlist)-dmem_ctl_2_0_0[0], output net "dmem_ctl_2_0_0_0" in work.decoder(netlist)
    input nets to instance:
        net "BUS2064_0" in work.decoder(netlist)
        net "alu_func_2_0_0_a2_0[1]" in work.decoder(netlist)
        net "fsm_dly_2_0_0_o2_x[2]" in work.decoder(netlist)
        net "alu_func_2_0_0_a2_0_x[4]" in work.decoder(netlist)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net dmem_ctl_2_0_0_1
11) instance work.decoder(netlist)-dmem_ctl_2_0_0[1], output net "dmem_ctl_2_0_0_1" in work.decoder(netlist)
    input nets to instance:
        net "BUS2064_1" in work.decoder(netlist)
        net "wb_mux_1_0_0_a2_x[0]" in work.decoder(netlist)
        net "dmem_ctl_2_0_0_a3_1[1]" in work.decoder(netlist)
        net "dmem_ctl_2_0_0_a[1]" in work.decoder(netlist)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net fsm_dly_2_0_0_0
12) instance work.decoder(netlist)-fsm_dly_2_0_0[0], output net "fsm_dly_2_0_0_0" in work.decoder(netlist)
    input nets to instance:
        net "BUS197_0" in work.decoder(netlist)
        net "ext_ctl_2_0_0_a3_1_0[2]" in work.decoder(netlist)
        net "ext_ctl_2_0_0_o3[2]" in work.decoder(netlist)
        net "fsm_dly_2_0_0_a[0]" in work.decoder(netlist)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net ext_ctl_2_0_0_0
13) instance work.decoder(netlist)-ext_ctl_2_0_0[2], output net "ext_ctl_2_0_0_0" in work.decoder(netlist)
    input nets to instance:
        net "BUS2072_2" in work.decoder(netlist)
        net "ext_ctl_2_0_0_a3_1_0[2]" in work.decoder(netlist)
        net "ext_ctl_2_0_0_o3[2]" in work.decoder(netlist)
        net "ext_ctl_2_0_0_a[2]" in work.decoder(netlist)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net alu_func_2_i_m3_0_0
14) instance work.decoder(netlist)-alu_func_2_i_m3_0[2], output net "alu_func_2_i_m3_0_0" in work.decoder(netlist)
    input nets to instance:
        net "alu_func_2_0_0_a3_1[3]" in work.decoder(netlist)
        net "alu_func_2_i_m3_0_3[2]" in work.decoder(netlist)
        net "alu_func_2_i_m3_0_a3_5[2]" in work.decoder(netlist)
        net "alu_func_2_i_m3_0_a[2]" in work.decoder(netlist)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net cmp_ctl_2_0_0_0
15) instance work.decoder(netlist)-cmp_ctl_2_0_0[0], output net "cmp_ctl_2_0_0_0" in work.decoder(netlist)
    input nets to instance:
        net "alu_func_2_0_0_a2_0[1]" in work.decoder(netlist)
        net "cmp_ctl_2_0_0_a2_1[0]" in work.decoder(netlist)
        net "BUS2056_0" in work.decoder(netlist)
        net "cmp_ctl_2_0_0_1[0]" in work.decoder(netlist)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net cmp_ctl_2_0_0_2
16) instance work.decoder(netlist)-cmp_ctl_2_0_0[2], output net "cmp_ctl_2_0_0_2" in work.decoder(netlist)
    input nets to instance:
        net "alu_func_2_0_0_a2_0[1]" in work.decoder(netlist)
        net "cmp_ctl_2_0_0_a2_x[0]" in work.decoder(netlist)
        net "alu_func_2_0_0_a2_0_x[0]" in work.decoder(netlist)
        net "cmp_ctl_2_0_0_a[2]" in work.decoder(netlist)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net cmp_ctl_2_0_0_1
17) instance work.decoder(netlist)-cmp_ctl_2_0_0[1], output net "cmp_ctl_2_0_0_1" in work.decoder(netlist)
    input nets to instance:
        net "BUS2056_1" in work.decoder(netlist)
        net "cmp_ctl_2_0_0_a2_0[0]" in work.decoder(netlist)
        net "alu_func_2_0_0_a2_0[1]" in work.decoder(netlist)
        net "cmp_ctl_2_0_0_a[1]" in work.decoder(netlist)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net muxa_ctl_2_0_0_0
18) instance work.decoder(netlist)-muxa_ctl_2_0_0[0], output net "muxa_ctl_2_0_0_0" in work.decoder(netlist)
    input nets to instance:
        net "alu_func_2_0_0_a2_0[1]" in work.decoder(netlist)
        net "alu_func_2_0_0_o2_x[3]" in work.decoder(netlist)
        net "ext_ctl_2_0_0_a2_2[2]" in work.decoder(netlist)
        net "muxa_ctl_2_0_0_a[0]" in work.decoder(netlist)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net muxa_ctl_2_0_0_1
19) instance work.decoder(netlist)-muxa_ctl_2_0_0[1], output net "muxa_ctl_2_0_0_1" in work.decoder(netlist)
    input nets to instance:
        net "zz_ins_i_c_29" in work.decoder(netlist)
        net "alu_func_2_0_0_o2_x[4]" in work.decoder(netlist)
        net "muxa_ctl_2_0_0_0[1]" in work.decoder(netlist)
        net "muxa_ctl_2_0_0_a[1]" in work.decoder(netlist)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net alu_we_1_0_0_0
20) instance work.decoder(netlist)-alu_we_1_0_0[0], output net "alu_we_1_0_0_0" in work.decoder(netlist)
    input nets to instance:
        net "zz_ins_i_c_29" in work.decoder(netlist)
        net "alu_we_1_0_0_0[0]" in work.decoder(netlist)
        net "alu_we_1_0_0_a3[0]" in work.decoder(netlist)
        net "alu_we_1_0_0_a[0]" in work.decoder(netlist)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net pc_gen_ctl_2_i_m3_0_0
21) instance work.decoder(netlist)-pc_gen_ctl_2_i_m3_0[0], output net "pc_gen_ctl_2_i_m3_0_0" in work.decoder(netlist)
    input nets to instance:
        net "zz_ins_i_c_4" in work.decoder(netlist)
        net "alu_func_2_0_0_a2_x[4]" in work.decoder(netlist)
        net "muxa_ctl_2_0_0_o2_0[1]" in work.decoder(netlist)
        net "pc_gen_ctl_2_i_m3_0_5[0]" in work.decoder(netlist)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net alu_func_2_0_0_4
22) instance work.decoder(netlist)-alu_func_2_0_0[4], output net "alu_func_2_0_0_4" in work.decoder(netlist)
    input nets to instance:
        net "BUS2040_4" in work.decoder(netlist)
        net "alu_func_2_0_0_a2_3[1]" in work.decoder(netlist)
        net "alu_func_2_0_0_2[4]" in work.decoder(netlist)
        net "alu_func_2_0_0_a[4]" in work.decoder(netlist)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net alu_func_2_0_0_1
23) instance work.decoder(netlist)-alu_func_2_0_0[1], output net "alu_func_2_0_0_1" in work.decoder(netlist)
    input nets to instance:
        net "alu_func_2_0_0_a2_x[0]" in work.decoder(netlist)
        net "alu_func_2_0_0_a3_1[1]" in work.decoder(netlist)
        net "alu_func_2_0_0_o2_x[0]" in work.decoder(netlist)
        net "alu_func_2_0_0_a[1]" in work.decoder(netlist)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net alu_func_2_0_0_0
24) instance work.decoder(netlist)-alu_func_2_0_0[0], output net "alu_func_2_0_0_0" in work.decoder(netlist)
    input nets to instance:
        net "zz_ins_i_c_0" in work.decoder(netlist)
        net "alu_func_2_0_0_a[0]" in work.decoder(netlist)
        net "alu_func_2_0_0_3[0]" in work.decoder(netlist)
        net "alu_func_2_0_0_o2_x[0]" in work.decoder(netlist)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net ext_ctl_2_i_m3_0_1
25) instance work.decoder(netlist)-ext_ctl_2_i_m3_0[1], output net "ext_ctl_2_i_m3_0_1" in work.decoder(netlist)
    input nets to instance:
        net "zz_ins_i_c_29" in work.decoder(netlist)
        net "zz_ins_i_c_28" in work.decoder(netlist)
        net "alu_func_2_0_0_a2_0_x[0]" in work.decoder(netlist)
        net "ext_ctl_2_i_m3_0_a[1]" in work.decoder(netlist)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net ext_ctl_2_i_m3_0_0
26) instance work.decoder(netlist)-ext_ctl_2_i_m3_0[0], output net "ext_ctl_2_i_m3_0_0" in work.decoder(netlist)
    input nets to instance:
        net "wb_mux_1_0_0_a3[0]" in work.decoder(netlist)
        net "fsm_dly_2_0_0_a3_0[2]" in work.decoder(netlist)
        net "ext_ctl_2_i_m3_0_a[0]" in work.decoder(netlist)
        net "ext_ctl_2_i_m3_0_2[0]" in work.decoder(netlist)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net pc_gen_ctl_2_i_0_0
27) instance work.decoder(netlist)-pc_gen_ctl_2_i_0[2], output net "pc_gen_ctl_2_i_0_0" in work.decoder(netlist)
    input nets to instance:
        net "zz_ins_i_c_2" in work.decoder(netlist)
        net "pc_gen_ctl_2_i_0_a3_0_0[2]" in work.decoder(netlist)
        net "pc_gen_ctl_2_i_0_a[2]" in work.decoder(netlist)
        net "pc_gen_ctl_2_i_0_4[2]" in work.decoder(netlist)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net alu_func_2_0_0_x_0
28) instance work.decoder(netlist)-alu_func_2_0_0_x[3], output net "alu_func_2_0_0_x_0" in work.decoder(netlist)
    input nets to instance:
        net "alu_func_2_0_0_a3_1[3]" in work.decoder(netlist)
        net "alu_func_2_0_0_1[3]" in work.decoder(netlist)
End of loops
Writing Verilog Netlist and constraint files
Warning: Found 28 combinational loops!
         Each loop is reported with an instance in the loop
         and nets connected to that instance.
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net wb_mux_1_0_0_0
1) instance work.decoder(netlist)-wb_mux_1_0_0[0], output net "wb_mux_1_0_0_0" in work.decoder(netlist)
    input nets to instance:
        net "alu_func_2_0_0_a2_0[1]" in work.decoder(netlist)
        net "BUS2118_0" in work.decoder(netlist)
        net "wb_mux_1_0_0_a3[0]" in work.decoder(netlist)
        net "fsm_dly_2_0_0_o2_x[2]" in work.decoder(netlist)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net wb_we_1_0_0_0
2) instance work.decoder(netlist)-wb_we_1_0_0[0], output net "wb_we_1_0_0_0" in work.decoder(netlist)
    input nets to instance:
        net "wb_we_1_0_0_a[0]" in work.decoder(netlist)
        net "wb_mux_1_0_0_a3[0]" in work.decoder(netlist)
        net "ext_ctl_2_i_m3_0_a2_x[1]" in work.decoder(netlist)
        net "fsm_dly350_1_0_a2_0_a3_0_o2_x" in work.decoder(netlist)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net rd_sel_2_0_0_1
3) instance work.decoder(netlist)-rd_sel_2_0_0[1], output net "rd_sel_2_0_0_1" in work.decoder(netlist)
    input nets to instance:
        net "rd_sel_2_0_0_a[1]" in work.decoder(netlist)
        net "muxb_ctl_2_0_0_o3[1]" in work.decoder(netlist)
        net "alu_func_2_0_0_a2_0_x[0]" in work.decoder(netlist)
        net "alu_func_2_0_0_a2_x[4]" in work.decoder(netlist)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net rd_sel_2_0_0_0
4) instance work.decoder(netlist)-rd_sel_2_0_0[0], output net "rd_sel_2_0_0_0" in work.decoder(netlist)
    input nets to instance:
        net "BUS2110_0" in work.decoder(netlist)
        net "alu_func_2_0_0_a2_3[1]" in work.decoder(netlist)
        net "rd_sel_2_0_0_a[0]" in work.decoder(netlist)
        net "alu_func_2_0_0_a3_1[1]" in work.decoder(netlist)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net pc_gen_ctl_2_0_0_0
5) instance work.decoder(netlist)-pc_gen_ctl_2_0_0[1], output net "pc_gen_ctl_2_0_0_0" in work.decoder(netlist)
    input nets to instance:
        net "alu_func_2_0_0_a2_0[1]" in work.decoder(netlist)
        net "BUS2102_1" in work.decoder(netlist)
        net "fsm_dly_2_0_0_o2_x[2]" in work.decoder(netlist)
        net "pc_gen_ctl_2_0_0_0[1]" in work.decoder(netlist)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net muxb_ctl_2_0_0_1
6) instance work.decoder(netlist)-muxb_ctl_2_0_0[1], output net "muxb_ctl_2_0_0_1" in work.decoder(netlist)
    input nets to instance:
        net "BUS2094_1" in work.decoder(netlist)
        net "alu_func_2_0_0_a2_2_x[3]" in work.decoder(netlist)
        net "fsm_dly_2_0_0_o2_x[2]" in work.decoder(netlist)
        net "muxb_ctl_2_0_0_a[1]" in work.decoder(netlist)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net muxb_ctl_2_0_0_0
7) instance work.decoder(netlist)-muxb_ctl_2_0_0[0], output net "muxb_ctl_2_0_0_0" in work.decoder(netlist)
    input nets to instance:
        net "zz_ins_i_c_4" in work.decoder(netlist)
        net "muxa_ctl_2_0_0_a3_1[0]" in work.decoder(netlist)
        net "muxb_ctl_2_0_0_a[0]" in work.decoder(netlist)
        net "muxb_ctl_2_0_0_a3_0_0_x[0]" in work.decoder(netlist)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net dmem_ctl_2_0_0_3
8) instance work.decoder(netlist)-dmem_ctl_2_0_0[3], output net "dmem_ctl_2_0_0_3" in work.decoder(netlist)
    input nets to instance:
        net "BUS2064_3" in work.decoder(netlist)
        net "alu_func_2_0_0_a2_0[1]" in work.decoder(netlist)
        net "fsm_dly_2_0_0_o2_x[2]" in work.decoder(netlist)
        net "dmem_ctl_2_0_0_a[3]" in work.decoder(netlist)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net dmem_ctl_2_0_0_2
9) instance work.decoder(netlist)-dmem_ctl_2_0_0[2], output net "dmem_ctl_2_0_0_2" in work.decoder(netlist)
    input nets to instance:
        net "BUS2064_2" in work.decoder(netlist)
        net "wb_mux_1_0_0_a2_x[0]" in work.decoder(netlist)
        net "dmem_ctl_2_0_0_a3_0[2]" in work.decoder(netlist)
        net "dmem_ctl_2_0_0_a[2]" in work.decoder(netlist)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net dmem_ctl_2_0_0_0
10) instance work.decoder(netlist)-dmem_ctl_2_0_0[0], output net "dmem_ctl_2_0_0_0" in work.decoder(netlist)
    input nets to instance:
        net "BUS2064_0" in work.decoder(netlist)
        net "alu_func_2_0_0_a2_0[1]" in work.decoder(netlist)
        net "fsm_dly_2_0_0_o2_x[2]" in work.decoder(netlist)
        net "alu_func_2_0_0_a2_0_x[4]" in work.decoder(netlist)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net dmem_ctl_2_0_0_1
11) instance work.decoder(netlist)-dmem_ctl_2_0_0[1], output net "dmem_ctl_2_0_0_1" in work.decoder(netlist)
    input nets to instance:
        net "BUS2064_1" in work.decoder(netlist)
        net "wb_mux_1_0_0_a2_x[0]" in work.decoder(netlist)
        net "dmem_ctl_2_0_0_a3_1[1]" in work.decoder(netlist)
        net "dmem_ctl_2_0_0_a[1]" in work.decoder(netlist)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net fsm_dly_2_0_0_0
12) instance work.decoder(netlist)-fsm_dly_2_0_0[0], output net "fsm_dly_2_0_0_0" in work.decoder(netlist)
    input nets to instance:
        net "BUS197_0" in work.decoder(netlist)
        net "ext_ctl_2_0_0_a3_1_0[2]" in work.decoder(netlist)
        net "ext_ctl_2_0_0_o3[2]" in work.decoder(netlist)
        net "fsm_dly_2_0_0_a[0]" in work.decoder(netlist)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net ext_ctl_2_0_0_0
13) instance work.decoder(netlist)-ext_ctl_2_0_0[2], output net "ext_ctl_2_0_0_0" in work.decoder(netlist)
    input nets to instance:
        net "BUS2072_2" in work.decoder(netlist)
        net "ext_ctl_2_0_0_a3_1_0[2]" in work.decoder(netlist)
        net "ext_ctl_2_0_0_o3[2]" in work.decoder(netlist)
        net "ext_ctl_2_0_0_a[2]" in work.decoder(netlist)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net alu_func_2_i_m3_0_0
14) instance work.decoder(netlist)-alu_func_2_i_m3_0[2], output net "alu_func_2_i_m3_0_0" in work.decoder(netlist)
    input nets to instance:
        net "alu_func_2_0_0_a3_1[3]" in work.decoder(netlist)
        net "alu_func_2_i_m3_0_3[2]" in work.decoder(netlist)
        net "alu_func_2_i_m3_0_a3_5[2]" in work.decoder(netlist)
        net "alu_func_2_i_m3_0_a[2]" in work.decoder(netlist)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net cmp_ctl_2_0_0_0
15) instance work.decoder(netlist)-cmp_ctl_2_0_0[0], output net "cmp_ctl_2_0_0_0" in work.decoder(netlist)
    input nets to instance:
        net "alu_func_2_0_0_a2_0[1]" in work.decoder(netlist)
        net "cmp_ctl_2_0_0_a2_1[0]" in work.decoder(netlist)
        net "BUS2056_0" in work.decoder(netlist)
        net "cmp_ctl_2_0_0_1[0]" in work.decoder(netlist)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net cmp_ctl_2_0_0_2
16) instance work.decoder(netlist)-cmp_ctl_2_0_0[2], output net "cmp_ctl_2_0_0_2" in work.decoder(netlist)
    input nets to instance:
        net "alu_func_2_0_0_a2_0[1]" in work.decoder(netlist)
        net "cmp_ctl_2_0_0_a2_x[0]" in work.decoder(netlist)
        net "alu_func_2_0_0_a2_0_x[0]" in work.decoder(netlist)
        net "cmp_ctl_2_0_0_a[2]" in work.decoder(netlist)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net cmp_ctl_2_0_0_1
17) instance work.decoder(netlist)-cmp_ctl_2_0_0[1], output net "cmp_ctl_2_0_0_1" in work.decoder(netlist)
    input nets to instance:
        net "BUS2056_1" in work.decoder(netlist)
        net "cmp_ctl_2_0_0_a2_0[0]" in work.decoder(netlist)
        net "alu_func_2_0_0_a2_0[1]" in work.decoder(netlist)
        net "cmp_ctl_2_0_0_a[1]" in work.decoder(netlist)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net muxa_ctl_2_0_0_0
18) instance work.decoder(netlist)-muxa_ctl_2_0_0[0], output net "muxa_ctl_2_0_0_0" in work.decoder(netlist)
    input nets to instance:
        net "alu_func_2_0_0_a2_0[1]" in work.decoder(netlist)
        net "alu_func_2_0_0_o2_x[3]" in work.decoder(netlist)
        net "ext_ctl_2_0_0_a2_2[2]" in work.decoder(netlist)
        net "muxa_ctl_2_0_0_a[0]" in work.decoder(netlist)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net muxa_ctl_2_0_0_1
19) instance work.decoder(netlist)-muxa_ctl_2_0_0[1], output net "muxa_ctl_2_0_0_1" in work.decoder(netlist)
    input nets to instance:
        net "zz_ins_i_c_29" in work.decoder(netlist)
        net "alu_func_2_0_0_o2_x[4]" in work.decoder(netlist)
        net "muxa_ctl_2_0_0_0[1]" in work.decoder(netlist)
        net "muxa_ctl_2_0_0_a[1]" in work.decoder(netlist)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net alu_we_1_0_0_0
20) instance work.decoder(netlist)-alu_we_1_0_0[0], output net "alu_we_1_0_0_0" in work.decoder(netlist)
    input nets to instance:
        net "zz_ins_i_c_29" in work.decoder(netlist)
        net "alu_we_1_0_0_0[0]" in work.decoder(netlist)
        net "alu_we_1_0_0_a3[0]" in work.decoder(netlist)
        net "alu_we_1_0_0_a[0]" in work.decoder(netlist)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net pc_gen_ctl_2_i_m3_0_0
21) instance work.decoder(netlist)-pc_gen_ctl_2_i_m3_0[0], output net "pc_gen_ctl_2_i_m3_0_0" in work.decoder(netlist)
    input nets to instance:
        net "zz_ins_i_c_4" in work.decoder(netlist)
        net "alu_func_2_0_0_a2_x[4]" in work.decoder(netlist)
        net "muxa_ctl_2_0_0_o2_0[1]" in work.decoder(netlist)
        net "pc_gen_ctl_2_i_m3_0_5[0]" in work.decoder(netlist)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net alu_func_2_0_0_4
22) instance work.decoder(netlist)-alu_func_2_0_0[4], output net "alu_func_2_0_0_4" in work.decoder(netlist)
    input nets to instance:
        net "BUS2040_4" in work.decoder(netlist)
        net "alu_func_2_0_0_a2_3[1]" in work.decoder(netlist)
        net "alu_func_2_0_0_2[4]" in work.decoder(netlist)
        net "alu_func_2_0_0_a[4]" in work.decoder(netlist)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net alu_func_2_0_0_1
23) instance work.decoder(netlist)-alu_func_2_0_0[1], output net "alu_func_2_0_0_1" in work.decoder(netlist)
    input nets to instance:
        net "alu_func_2_0_0_a2_x[0]" in work.decoder(netlist)
        net "alu_func_2_0_0_a3_1[1]" in work.decoder(netlist)
        net "alu_func_2_0_0_o2_x[0]" in work.decoder(netlist)
        net "alu_func_2_0_0_a[1]" in work.decoder(netlist)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net alu_func_2_0_0_0
24) instance work.decoder(netlist)-alu_func_2_0_0[0], output net "alu_func_2_0_0_0" in work.decoder(netlist)
    input nets to instance:
        net "zz_ins_i_c_0" in work.decoder(netlist)
        net "alu_func_2_0_0_a[0]" in work.decoder(netlist)
        net "alu_func_2_0_0_3[0]" in work.decoder(netlist)
        net "alu_func_2_0_0_o2_x[0]" in work.decoder(netlist)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net ext_ctl_2_i_m3_0_1
25) instance work.decoder(netlist)-ext_ctl_2_i_m3_0[1], output net "ext_ctl_2_i_m3_0_1" in work.decoder(netlist)
    input nets to instance:
        net "zz_ins_i_c_29" in work.decoder(netlist)
        net "zz_ins_i_c_28" in work.decoder(netlist)
        net "alu_func_2_0_0_a2_0_x[0]" in work.decoder(netlist)
        net "ext_ctl_2_i_m3_0_a[1]" in work.decoder(netlist)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net ext_ctl_2_i_m3_0_0
26) instance work.decoder(netlist)-ext_ctl_2_i_m3_0[0], output net "ext_ctl_2_i_m3_0_0" in work.decoder(netlist)
    input nets to instance:
        net "wb_mux_1_0_0_a3[0]" in work.decoder(netlist)
        net "fsm_dly_2_0_0_a3_0[2]" in work.decoder(netlist)
        net "ext_ctl_2_i_m3_0_a[0]" in work.decoder(netlist)
        net "ext_ctl_2_i_m3_0_2[0]" in work.decoder(netlist)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net pc_gen_ctl_2_i_0_0
27) instance work.decoder(netlist)-pc_gen_ctl_2_i_0[2], output net "pc_gen_ctl_2_i_0_0" in work.decoder(netlist)
    input nets to instance:
        net "zz_ins_i_c_2" in work.decoder(netlist)
        net "pc_gen_ctl_2_i_0_a3_0_0[2]" in work.decoder(netlist)
        net "pc_gen_ctl_2_i_0_a[2]" in work.decoder(netlist)
        net "pc_gen_ctl_2_i_0_4[2]" in work.decoder(netlist)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net alu_func_2_0_0_x_0
28) instance work.decoder(netlist)-alu_func_2_0_0_x[3], output net "alu_func_2_0_0_x_0" in work.decoder(netlist)
    input nets to instance:
        net "alu_func_2_0_0_a3_1[3]" in work.decoder(netlist)
        net "alu_func_2_0_0_1[3]" in work.decoder(netlist)
End of loops
Writing .vqm output for Quartus
Writing Cross reference file for Quartus to E:\mips789\mips789\synplify_prj\rev_1\mips_sys.xrf
Warning: Found 28 combinational loops!
         Each loop is reported with an instance in the loop
         and nets connected to that instance.
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net wb_mux_1_0_0_0
1) instance work.decoder(netlist)-wb_mux_1_0_0[0], output net "wb_mux_1_0_0_0" in work.decoder(netlist)
    input nets to instance:
        net "alu_func_2_0_0_a2_0[1]" in work.decoder(netlist)
        net "BUS2118_0" in work.decoder(netlist)
        net "wb_mux_1_0_0_a3[0]" in work.decoder(netlist)
        net "fsm_dly_2_0_0_o2_x[2]" in work.decoder(netlist)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net wb_we_1_0_0_0
2) instance work.decoder(netlist)-wb_we_1_0_0[0], output net "wb_we_1_0_0_0" in work.decoder(netlist)
    input nets to instance:
        net "wb_we_1_0_0_a[0]" in work.decoder(netlist)
        net "wb_mux_1_0_0_a3[0]" in work.decoder(netlist)
        net "ext_ctl_2_i_m3_0_a2_x[1]" in work.decoder(netlist)
        net "fsm_dly350_1_0_a2_0_a3_0_o2_x" in work.decoder(netlist)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net rd_sel_2_0_0_1
3) instance work.decoder(netlist)-rd_sel_2_0_0[1], output net "rd_sel_2_0_0_1" in work.decoder(netlist)
    input nets to instance:
        net "rd_sel_2_0_0_a[1]" in work.decoder(netlist)
        net "muxb_ctl_2_0_0_o3[1]" in work.decoder(netlist)
        net "alu_func_2_0_0_a2_0_x[0]" in work.decoder(netlist)
        net "alu_func_2_0_0_a2_x[4]" in work.decoder(netlist)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net rd_sel_2_0_0_0
4) instance work.decoder(netlist)-rd_sel_2_0_0[0], output net "rd_sel_2_0_0_0" in work.decoder(netlist)
    input nets to instance:
        net "BUS2110_0" in work.decoder(netlist)
        net "alu_func_2_0_0_a2_3[1]" in work.decoder(netlist)
        net "rd_sel_2_0_0_a[0]" in work.decoder(netlist)
        net "alu_func_2_0_0_a3_1[1]" in work.decoder(netlist)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net pc_gen_ctl_2_0_0_0
5) instance work.decoder(netlist)-pc_gen_ctl_2_0_0[1], output net "pc_gen_ctl_2_0_0_0" in work.decoder(netlist)
    input nets to instance:
        net "alu_func_2_0_0_a2_0[1]" in work.decoder(netlist)
        net "BUS2102_1" in work.decoder(netlist)
        net "fsm_dly_2_0_0_o2_x[2]" in work.decoder(netlist)
        net "pc_gen_ctl_2_0_0_0[1]" in work.decoder(netlist)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net muxb_ctl_2_0_0_1
6) instance work.decoder(netlist)-muxb_ctl_2_0_0[1], output net "muxb_ctl_2_0_0_1" in work.decoder(netlist)
    input nets to instance:
        net "BUS2094_1" in work.decoder(netlist)
        net "alu_func_2_0_0_a2_2_x[3]" in work.decoder(netlist)
        net "fsm_dly_2_0_0_o2_x[2]" in work.decoder(netlist)
        net "muxb_ctl_2_0_0_a[1]" in work.decoder(netlist)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net muxb_ctl_2_0_0_0
7) instance work.decoder(netlist)-muxb_ctl_2_0_0[0], output net "muxb_ctl_2_0_0_0" in work.decoder(netlist)
    input nets to instance:
        net "zz_ins_i_c_4" in work.decoder(netlist)
        net "muxa_ctl_2_0_0_a3_1[0]" in work.decoder(netlist)
        net "muxb_ctl_2_0_0_a[0]" in work.decoder(netlist)
        net "muxb_ctl_2_0_0_a3_0_0_x[0]" in work.decoder(netlist)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net dmem_ctl_2_0_0_3
8) instance work.decoder(netlist)-dmem_ctl_2_0_0[3], output net "dmem_ctl_2_0_0_3" in work.decoder(netlist)
    input nets to instance:
        net "BUS2064_3" in work.decoder(netlist)
        net "alu_func_2_0_0_a2_0[1]" in work.decoder(netlist)
        net "fsm_dly_2_0_0_o2_x[2]" in work.decoder(netlist)
        net "dmem_ctl_2_0_0_a[3]" in work.decoder(netlist)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net dmem_ctl_2_0_0_2
9) instance work.decoder(netlist)-dmem_ctl_2_0_0[2], output net "dmem_ctl_2_0_0_2" in work.decoder(netlist)
    input nets to instance:
        net "BUS2064_2" in work.decoder(netlist)
        net "wb_mux_1_0_0_a2_x[0]" in work.decoder(netlist)
        net "dmem_ctl_2_0_0_a3_0[2]" in work.decoder(netlist)
        net "dmem_ctl_2_0_0_a[2]" in work.decoder(netlist)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net dmem_ctl_2_0_0_0
10) instance work.decoder(netlist)-dmem_ctl_2_0_0[0], output net "dmem_ctl_2_0_0_0" in work.decoder(netlist)
    input nets to instance:
        net "BUS2064_0" in work.decoder(netlist)
        net "alu_func_2_0_0_a2_0[1]" in work.decoder(netlist)
        net "fsm_dly_2_0_0_o2_x[2]" in work.decoder(netlist)
        net "alu_func_2_0_0_a2_0_x[4]" in work.decoder(netlist)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net dmem_ctl_2_0_0_1
11) instance work.decoder(netlist)-dmem_ctl_2_0_0[1], output net "dmem_ctl_2_0_0_1" in work.decoder(netlist)
    input nets to instance:
        net "BUS2064_1" in work.decoder(netlist)
        net "wb_mux_1_0_0_a2_x[0]" in work.decoder(netlist)
        net "dmem_ctl_2_0_0_a3_1[1]" in work.decoder(netlist)
        net "dmem_ctl_2_0_0_a[1]" in work.decoder(netlist)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net fsm_dly_2_0_0_0
12) instance work.decoder(netlist)-fsm_dly_2_0_0[0], output net "fsm_dly_2_0_0_0" in work.decoder(netlist)
    input nets to instance:
        net "BUS197_0" in work.decoder(netlist)
        net "ext_ctl_2_0_0_a3_1_0[2]" in work.decoder(netlist)
        net "ext_ctl_2_0_0_o3[2]" in work.decoder(netlist)
        net "fsm_dly_2_0_0_a[0]" in work.decoder(netlist)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net ext_ctl_2_0_0_0
13) instance work.decoder(netlist)-ext_ctl_2_0_0[2], output net "ext_ctl_2_0_0_0" in work.decoder(netlist)
    input nets to instance:
        net "BUS2072_2" in work.decoder(netlist)
        net "ext_ctl_2_0_0_a3_1_0[2]" in work.decoder(netlist)
        net "ext_ctl_2_0_0_o3[2]" in work.decoder(netlist)
        net "ext_ctl_2_0_0_a[2]" in work.decoder(netlist)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net alu_func_2_i_m3_0_0
14) instance work.decoder(netlist)-alu_func_2_i_m3_0[2], output net "alu_func_2_i_m3_0_0" in work.decoder(netlist)
    input nets to instance:
        net "alu_func_2_0_0_a3_1[3]" in work.decoder(netlist)
        net "alu_func_2_i_m3_0_3[2]" in work.decoder(netlist)
        net "alu_func_2_i_m3_0_a3_5[2]" in work.decoder(netlist)
        net "alu_func_2_i_m3_0_a[2]" in work.decoder(netlist)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net cmp_ctl_2_0_0_0
15) instance work.decoder(netlist)-cmp_ctl_2_0_0[0], output net "cmp_ctl_2_0_0_0" in work.decoder(netlist)
    input nets to instance:
        net "alu_func_2_0_0_a2_0[1]" in work.decoder(netlist)
        net "cmp_ctl_2_0_0_a2_1[0]" in work.decoder(netlist)
        net "BUS2056_0" in work.decoder(netlist)
        net "cmp_ctl_2_0_0_1[0]" in work.decoder(netlist)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net cmp_ctl_2_0_0_2
16) instance work.decoder(netlist)-cmp_ctl_2_0_0[2], output net "cmp_ctl_2_0_0_2" in work.decoder(netlist)
    input nets to instance:
        net "alu_func_2_0_0_a2_0[1]" in work.decoder(netlist)
        net "cmp_ctl_2_0_0_a2_x[0]" in work.decoder(netlist)
        net "alu_func_2_0_0_a2_0_x[0]" in work.decoder(netlist)
        net "cmp_ctl_2_0_0_a[2]" in work.decoder(netlist)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net cmp_ctl_2_0_0_1
17) instance work.decoder(netlist)-cmp_ctl_2_0_0[1], output net "cmp_ctl_2_0_0_1" in work.decoder(netlist)
    input nets to instance:
        net "BUS2056_1" in work.decoder(netlist)
        net "cmp_ctl_2_0_0_a2_0[0]" in work.decoder(netlist)
        net "alu_func_2_0_0_a2_0[1]" in work.decoder(netlist)
        net "cmp_ctl_2_0_0_a[1]" in work.decoder(netlist)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net muxa_ctl_2_0_0_0
18) instance work.decoder(netlist)-muxa_ctl_2_0_0[0], output net "muxa_ctl_2_0_0_0" in work.decoder(netlist)
    input nets to instance:
        net "alu_func_2_0_0_a2_0[1]" in work.decoder(netlist)
        net "alu_func_2_0_0_o2_x[3]" in work.decoder(netlist)
        net "ext_ctl_2_0_0_a2_2[2]" in work.decoder(netlist)
        net "muxa_ctl_2_0_0_a[0]" in work.decoder(netlist)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net muxa_ctl_2_0_0_1
19) instance work.decoder(netlist)-muxa_ctl_2_0_0[1], output net "muxa_ctl_2_0_0_1" in work.decoder(netlist)
    input nets to instance:
        net "zz_ins_i_c_29" in work.decoder(netlist)
        net "alu_func_2_0_0_o2_x[4]" in work.decoder(netlist)
        net "muxa_ctl_2_0_0_0[1]" in work.decoder(netlist)
        net "muxa_ctl_2_0_0_a[1]" in work.decoder(netlist)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net alu_we_1_0_0_0
20) instance work.decoder(netlist)-alu_we_1_0_0[0], output net "alu_we_1_0_0_0" in work.decoder(netlist)
    input nets to instance:
        net "zz_ins_i_c_29" in work.decoder(netlist)
        net "alu_we_1_0_0_0[0]" in work.decoder(netlist)
        net "alu_we_1_0_0_a3[0]" in work.decoder(netlist)
        net "alu_we_1_0_0_a[0]" in work.decoder(netlist)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net pc_gen_ctl_2_i_m3_0_0
21) instance work.decoder(netlist)-pc_gen_ctl_2_i_m3_0[0], output net "pc_gen_ctl_2_i_m3_0_0" in work.decoder(netlist)
    input nets to instance:
        net "zz_ins_i_c_4" in work.decoder(netlist)
        net "alu_func_2_0_0_a2_x[4]" in work.decoder(netlist)
        net "muxa_ctl_2_0_0_o2_0[1]" in work.decoder(netlist)
        net "pc_gen_ctl_2_i_m3_0_5[0]" in work.decoder(netlist)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net alu_func_2_0_0_4
22) instance work.decoder(netlist)-alu_func_2_0_0[4], output net "alu_func_2_0_0_4" in work.decoder(netlist)
    input nets to instance:
        net "BUS2040_4" in work.decoder(netlist)
        net "alu_func_2_0_0_a2_3[1]" in work.decoder(netlist)
        net "alu_func_2_0_0_2[4]" in work.decoder(netlist)
        net "alu_func_2_0_0_a[4]" in work.decoder(netlist)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net alu_func_2_0_0_1
23) instance work.decoder(netlist)-alu_func_2_0_0[1], output net "alu_func_2_0_0_1" in work.decoder(netlist)
    input nets to instance:
        net "alu_func_2_0_0_a2_x[0]" in work.decoder(netlist)
        net "alu_func_2_0_0_a3_1[1]" in work.decoder(netlist)
        net "alu_func_2_0_0_o2_x[0]" in work.decoder(netlist)
        net "alu_func_2_0_0_a[1]" in work.decoder(netlist)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net alu_func_2_0_0_0
24) instance work.decoder(netlist)-alu_func_2_0_0[0], output net "alu_func_2_0_0_0" in work.decoder(netlist)
    input nets to instance:
        net "zz_ins_i_c_0" in work.decoder(netlist)
        net "alu_func_2_0_0_a[0]" in work.decoder(netlist)
        net "alu_func_2_0_0_3[0]" in work.decoder(netlist)
        net "alu_func_2_0_0_o2_x[0]" in work.decoder(netlist)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net ext_ctl_2_i_m3_0_1
25) instance work.decoder(netlist)-ext_ctl_2_i_m3_0[1], output net "ext_ctl_2_i_m3_0_1" in work.decoder(netlist)
    input nets to instance:
        net "zz_ins_i_c_29" in work.decoder(netlist)
        net "zz_ins_i_c_28" in work.decoder(netlist)
        net "alu_func_2_0_0_a2_0_x[0]" in work.decoder(netlist)
        net "ext_ctl_2_i_m3_0_a[1]" in work.decoder(netlist)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net ext_ctl_2_i_m3_0_0
26) instance work.decoder(netlist)-ext_ctl_2_i_m3_0[0], output net "ext_ctl_2_i_m3_0_0" in work.decoder(netlist)
    input nets to instance:
        net "wb_mux_1_0_0_a3[0]" in work.decoder(netlist)
        net "fsm_dly_2_0_0_a3_0[2]" in work.decoder(netlist)
        net "ext_ctl_2_i_m3_0_a[0]" in work.decoder(netlist)
        net "ext_ctl_2_i_m3_0_2[0]" in work.decoder(netlist)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net pc_gen_ctl_2_i_0_0
27) instance work.decoder(netlist)-pc_gen_ctl_2_i_0[2], output net "pc_gen_ctl_2_i_0_0" in work.decoder(netlist)
    input nets to instance:
        net "zz_ins_i_c_2" in work.decoder(netlist)
        net "pc_gen_ctl_2_i_0_a3_0_0[2]" in work.decoder(netlist)
        net "pc_gen_ctl_2_i_0_a[2]" in work.decoder(netlist)
        net "pc_gen_ctl_2_i_0_4[2]" in work.decoder(netlist)
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net alu_func_2_0_0_x_0
28) instance work.decoder(netlist)-alu_func_2_0_0_x[3], output net "alu_func_2_0_0_x_0" in work.decoder(netlist)
    input nets to instance:
        net "alu_func_2_0_0_a3_1[3]" in work.decoder(netlist)
        net "alu_func_2_0_0_1[3]" in work.decoder(netlist)
End of loops
Found clock mips_sys|clk with period 20.00ns 
@W: MT253 :"e:\mips789\mips789\rtl\verilog\altera\fifo512_cyclone.v":66:8:66:23|Blackbox scfifo_Z1 is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W:"e:\mips789\mips789\rtl\verilog\mem_module.v":161:4:161:7|Net un1_byte_addr_2 appears to be a clock source which was not identified. Assuming default frequency. 
@W:"e:\mips789\mips789\rtl\verilog\ctl_fsm.v":58:8:58:11|Net un1_NextState_Sreg0_6 appears to be a clock source which was not identified. Assuming default frequency. 
@W:"e:\mips789\mips789\rtl\verilog\decode_pipe.v":1:1:961:15|Net un1_fsm_dly370 appears to be a clock source which was not identified. Assuming default frequency. 


##### START OF TIMING REPORT #####[
# Timing Report written on Fri Oct 10 10:30:00 2008
#


Top view:               mips_sys
Requested Frequency:    50.0 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    
@N: MT195 |This timing report estimates place and route data. Please look at the place and route timing report for final timing..

@N: MT197 |Clock constraints cover only FF-to-FF paths associated with the clock..



Performance Summary 
*******************


Worst slack in design: 1.601

                   Requested     Estimated     Requested     Estimated                Clock        Clock              
Starting Clock     Frequency     Frequency     Period        Period        Slack      Type         Group              
----------------------------------------------------------------------------------------------------------------------
mips_sys|clk       50.0 MHz      54.4 MHz      20.000        18.399        1.601      inferred     Inferred_clkgroup_0
System             50.0 MHz      370.5 MHz     20.000        2.699         17.301     system       default_clkgroup   
======================================================================================================================





Clock Relationships
*******************

Clocks                      |    rise  to  rise   |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
------------------------------------------------------------------------------------------------------------------
Starting      Ending        |  constraint  slack  |  constraint  slack  |  constraint  slack  |  constraint  slack
------------------------------------------------------------------------------------------------------------------
mips_sys|clk  mips_sys|clk  |  20.000      1.601  |  No paths    -      |  No paths    -      |  No paths    -    
==================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

                No IO constraint found 



====================================
Detailed Report for Clock: mips_sys|clk
====================================



Starting Points with Worst Slack
********************************

                                          Starting                                                      Arrival          
Instance                                  Reference        Type                 Pin        Net          Time        Slack
                                          Clock                                                                          
-------------------------------------------------------------------------------------------------------------------------
mips_core.rnd_pass1.r5_o[2]               mips_sys|clk     cyclone_lcell_ff     regout     r5_o_2       0.224       1.601
mips_core.rnd_pass1.r5_o[4]               mips_sys|clk     cyclone_lcell_ff     regout     r5_o_4       0.224       1.749
mips_core.iRF_stage.ins_reg.r32_o[22]     mips_sys|clk     cyclone_lcell_ff     regout     r32_o_22     0.224       1.965
mips_core.rnd_pass1.r5_o[3]               mips_sys|clk     cyclone_lcell_ff     regout     r5_o_3       0.224       2.034
mips_core.rnd_pass1.r5_o[1]               mips_sys|clk     cyclone_lcell_ff     regout     r5_o_1       0.224       2.113
mips_core.iRF_stage.ins_reg.r32_o[23]     mips_sys|clk     cyclone_lcell_ff     regout     r32_o_23     0.224       2.143
mips_core.rnd_pass1.r5_o[0]               mips_sys|clk     cyclone_lcell_ff     regout     r5_o_0       0.224       2.182
mips_core.iRF_stage.ins_reg.r32_o[21]     mips_sys|clk     cyclone_lcell_ff     regout     r32_o_21     0.224       2.263
mips_core.iRF_stage.ins_reg.r32_o[20]     mips_sys|clk     cyclone_lcell_ff     regout     r32_o_20     0.224       2.276
mips_core.iRF_stage.ins_reg.r32_o[19]     mips_sys|clk     cyclone_lcell_ff     regout     r32_o_19     0.224       2.424
=========================================================================================================================


Ending Points with Worst Slack
******************************

                               Starting                                                         Required          
Instance                       Reference        Type                 Pin       Net              Time         Slack
                               Clock                                                                              
------------------------------------------------------------------------------------------------------------------
mips_core.rs_reg.r32_o[14]     mips_sys|clk     cyclone_lcell_ff     datab     dout_iv_1_14     9.834        1.601
mips_core.pc.r32_o[31]         mips_sys|clk     cyclone_lcell_ff     datad     un1_pc_add31     19.963       1.601
mips_core.pc.r32_o[30]         mips_sys|clk     cyclone_lcell_ff     datac     un1_pc_add30     19.963       1.635
mips_core.pc.r32_o[29]         mips_sys|clk     cyclone_lcell_ff     datac     un1_pc_add29     19.963       1.669
mips_core.pc.r32_o[28]         mips_sys|clk     cyclone_lcell_ff     datac     un1_pc_add28     19.963       1.703
mips_core.pc.r32_o[27]         mips_sys|clk     cyclone_lcell_ff     datac     un1_pc_add27     19.963       1.737
mips_core.rs_reg.r32_o[9]      mips_sys|clk     cyclone_lcell_ff     datab     dout_iv_1_9      9.973        1.741
mips_core.rs_reg.r32_o[19]     mips_sys|clk     cyclone_lcell_ff     datab     dout_iv_1_19     9.982        1.749
mips_core.pc.r32_o[26]         mips_sys|clk     cyclone_lcell_ff     datac     un1_pc_add26     19.963       1.771
mips_core.pc.r32_o[25]         mips_sys|clk     cyclone_lcell_ff     datac     un1_pc_add25     19.963       1.805
==================================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
    Requested Period:                        20.000
    - Setup time:                            0.037
    = Required time:                         19.963

    - Propagation time:                      18.362
    = Slack (critical) :                     1.601

    Number of logic level(s):                48
    Starting point:                          mips_core.rnd_pass1.r5_o[2] / regout
    Ending point:                            mips_core.pc.r32_o[31] / datad
    The start point is clocked by            mips_sys|clk [rising] on pin clk
    The end   point is clocked by            mips_sys|clk [rising] on pin clk

Instance / Net                                                                Pin         Pin               Arrival     No. of    
Name                                                     Type                 Name        Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------------------------------------------
mips_core.rnd_pass1.r5_o[2]                              cyclone_lcell_ff     regout      Out     0.224     0.224       -         
r5_o_2                                                   Net                  -           -       0.829     -           6         
mips_core.iforward.fw_alu_rs.un14_mux_fw_a               cyclone_lcell        dataa       In      -         1.053       -         
mips_core.iforward.fw_alu_rs.un14_mux_fw_a               cyclone_lcell        combout     Out     0.590     1.643       -         
un14_mux_fw_a                                            Net                  -           -       0.319     -           1         
mips_core.iforward.fw_alu_rs.un14_mux_fw                 cyclone_lcell        datad       In      -         1.962       -         
mips_core.iforward.fw_alu_rs.un14_mux_fw                 cyclone_lcell        combout     Out     0.114     2.076       -         
un14_mux_fw                                              Net                  -           -       0.711     -           5         
mips_core.iforward.fw_cmp_rs.mux_fw_1                    cyclone_lcell        datab       In      -         2.786       -         
mips_core.iforward.fw_cmp_rs.mux_fw_1                    cyclone_lcell        combout     Out     0.442     3.228       -         
mux_fw_1                                                 Net                  -           -       1.636     -           34        
mips_core.iforward.fw_cmp_rs.un32_mux_fw                 cyclone_lcell        datad       In      -         4.864       -         
mips_core.iforward.fw_cmp_rs.un32_mux_fw                 cyclone_lcell        combout     Out     0.114     4.978       -         
un32_mux_fw                                              Net                  -           -       0.357     -           2         
mips_core.iRF_stage.reg_bank.N_14_i_0_s2                 cyclone_lcell        datad       In      -         5.335       -         
mips_core.iRF_stage.reg_bank.N_14_i_0_s2                 cyclone_lcell        combout     Out     0.114     5.449       -         
N_14_i_0_s2                                              Net                  -           -       1.590     -           32        
mips_core.iRF_stage.rs_fwd_rs.dout_iv_1_a[14]            cyclone_lcell        datad       In      -         7.039       -         
mips_core.iRF_stage.rs_fwd_rs.dout_iv_1_a[14]            cyclone_lcell        combout     Out     0.114     7.153       -         
dout_iv_1_a[14]                                          Net                  -           -       0.319     -           1         
mips_core.iRF_stage.rs_fwd_rs.dout_iv_1[14]              cyclone_lcell        datab       In      -         7.472       -         
mips_core.iRF_stage.rs_fwd_rs.dout_iv_1[14]              cyclone_lcell        combout     Out     0.442     7.914       -         
dout_iv_1_14                                             Net                  -           -       0.319     -           1         
mips_core.rs_reg.r32_o[14]                               cyclone_lcell_ff     datab       In      -         8.233       -         
mips_core.rs_reg.r32_o[14]                               cyclone_lcell_ff     combout     Out     0.442     8.675       -         
dout_iv_14                                               Net                  -           -       0.475     -           3         
mips_core.iRF_stage.i_cmp.un10_res_23_a                  cyclone_lcell        dataa       In      -         9.150       -         
mips_core.iRF_stage.i_cmp.un10_res_23_a                  cyclone_lcell        combout     Out     0.590     9.740       -         
un10_res_23_a                                            Net                  -           -       0.319     -           1         
mips_core.iRF_stage.i_cmp.un10_res_23                    cyclone_lcell        datad       In      -         10.059      -         
mips_core.iRF_stage.i_cmp.un10_res_23                    cyclone_lcell        combout     Out     0.114     10.172      -         
un10_res_23                                              Net                  -           -       0.319     -           1         
mips_core.iRF_stage.i_cmp.un10_res_27                    cyclone_lcell        datac       In      -         10.491      -         
mips_core.iRF_stage.i_cmp.un10_res_27                    cyclone_lcell        combout     Out     0.292     10.783      -         
un10_res_27                                              Net                  -           -       0.319     -           1         
mips_core.iRF_stage.i_cmp.res_5                          cyclone_lcell        datab       In      -         11.102      -         
mips_core.iRF_stage.i_cmp.res_5                          cyclone_lcell        combout     Out     0.442     11.544      -         
res_5                                                    Net                  -           -       0.319     -           1         
mips_core.iRF_stage.i_cmp.res_7_0_a                      cyclone_lcell        datac       In      -         11.863      -         
mips_core.iRF_stage.i_cmp.res_7_0_a                      cyclone_lcell        combout     Out     0.292     12.155      -         
res_7_0_a                                                Net                  -           -       0.319     -           1         
mips_core.iRF_stage.i_cmp.res_7_0                        cyclone_lcell        datac       In      -         12.474      -         
mips_core.iRF_stage.i_cmp.res_7_0                        cyclone_lcell        combout     Out     0.292     12.766      -         
res_7_0                                                  Net                  -           -       0.357     -           2         
mips_core.iRF_stage.i_pc_gen.un1_pc_prectl_1_0_a3[0]     cyclone_lcell        datad       In      -         13.123      -         
mips_core.iRF_stage.i_pc_gen.un1_pc_prectl_1_0_a3[0]     cyclone_lcell        combout     Out     0.114     13.237      -         
un1_pc_prectl_1_0_a3[0]                                  Net                  -           -       1.567     -           31        
mips_core.iRF_stage.i_pc_gen.un1_pc_prectl_1_0_a4[0]     cyclone_lcell        datab       In      -         14.804      -         
mips_core.iRF_stage.i_pc_gen.un1_pc_prectl_1_0_a4[0]     cyclone_lcell        combout     Out     0.442     15.246      -         
un1_pc_prectl_1_0_a4[0]                                  Net                  -           -       0.319     -           1         
mips_core.iRF_stage.i_pc_gen.un1_pc_add0                 cyclone_lcell        datab       In      -         15.564      -         
mips_core.iRF_stage.i_pc_gen.un1_pc_add0                 cyclone_lcell        cout        Out     0.838     16.402      -         
un1_pc_carry_0                                           Net                  -           -       0.000     -           1         
mips_core.iRF_stage.i_pc_gen.un1_pc_add1                 cyclone_lcell        cin         In      -         16.402      -         
mips_core.iRF_stage.i_pc_gen.un1_pc_add1                 cyclone_lcell        cout        Out     0.034     16.436      -         
un1_pc_carry_1                                           Net                  -           -       0.000     -           1         
mips_core.iRF_stage.i_pc_gen.un1_pc_add2                 cyclone_lcell        cin         In      -         16.436      -         
mips_core.iRF_stage.i_pc_gen.un1_pc_add2                 cyclone_lcell        cout        Out     0.034     16.470      -         
un1_pc_carry_2                                           Net                  -           -       0.000     -           1         
mips_core.iRF_stage.i_pc_gen.un1_pc_add3                 cyclone_lcell        cin         In      -         16.470      -         
mips_core.iRF_stage.i_pc_gen.un1_pc_add3                 cyclone_lcell        cout        Out     0.034     16.504      -         
un1_pc_carry_3                                           Net                  -           -       0.000     -           1         
mips_core.iRF_stage.i_pc_gen.un1_pc_add4                 cyclone_lcell        cin         In      -         16.504      -         
mips_core.iRF_stage.i_pc_gen.un1_pc_add4                 cyclone_lcell        cout        Out     0.034     16.538      -         
un1_pc_carry_4                                           Net                  -           -       0.000     -           1         
mips_core.iRF_stage.i_pc_gen.un1_pc_add5                 cyclone_lcell        cin         In      -         16.538      -         
mips_core.iRF_stage.i_pc_gen.un1_pc_add5                 cyclone_lcell        cout        Out     0.034     16.572      -         
un1_pc_carry_5                                           Net                  -           -       0.000     -           1         
mips_core.iRF_stage.i_pc_gen.un1_pc_add6                 cyclone_lcell        cin         In      -         16.572      -         
mips_core.iRF_stage.i_pc_gen.un1_pc_add6                 cyclone_lcell        cout        Out     0.034     16.606      -         
un1_pc_carry_6                                           Net                  -           -       0.000     -           1         
mips_core.iRF_stage.i_pc_gen.un1_pc_add7                 cyclone_lcell        cin         In      -         16.606      -         
mips_core.iRF_stage.i_pc_gen.un1_pc_add7                 cyclone_lcell        cout        Out     0.034     16.640      -         
un1_pc_carry_7                                           Net                  -           -       0.000     -           1         
mips_core.iRF_stage.i_pc_gen.un1_pc_add8                 cyclone_lcell        cin         In      -         16.640      -         
mips_core.iRF_stage.i_pc_gen.un1_pc_add8                 cyclone_lcell        cout        Out     0.034     16.674      -         
un1_pc_carry_8                                           Net                  -           -       0.000     -           1         
mips_core.iRF_stage.i_pc_gen.un1_pc_add9                 cyclone_lcell        cin         In      -         16.674      -         
mips_core.iRF_stage.i_pc_gen.un1_pc_add9                 cyclone_lcell        cout        Out     0.034     16.708      -         
un1_pc_carry_9                                           Net                  -           -       0.000     -           1         
mips_core.iRF_stage.i_pc_gen.un1_pc_add10                cyclone_lcell        cin         In      -         16.708      -         
mips_core.iRF_stage.i_pc_gen.un1_pc_add10                cyclone_lcell        cout        Out     0.034     16.742      -         
un1_pc_carry_10                                          Net                  -           -       0.000     -           1         
mips_core.iRF_stage.i_pc_gen.un1_pc_add11                cyclone_lcell        cin         In      -         16.742      -         
mips_core.iRF_stage.i_pc_gen.un1_pc_add11                cyclone_lcell        cout        Out     0.034     16.776      -         
un1_pc_carry_11                                          Net                  -           -       0.000     -           1         
mips_core.iRF_stage.i_pc_gen.un1_pc_add12                cyclone_lcell        cin         In      -         16.776      -         
mips_core.iRF_stage.i_pc_gen.un1_pc_add12                cyclone_lcell        cout        Out     0.034     16.810      -         
un1_pc_carry_12                                          Net                  -           -       0.000     -           1         
mips_core.iRF_stage.i_pc_gen.un1_pc_add13                cyclone_lcell        cin         In      -         16.810      -         
mips_core.iRF_stage.i_pc_gen.un1_pc_add13                cyclone_lcell        cout        Out     0.034     16.844      -         
un1_pc_carry_13                                          Net                  -           -       0.000     -           1         
mips_core.iRF_stage.i_pc_gen.un1_pc_add14                cyclone_lcell        cin         In      -         16.844      -         
mips_core.iRF_stage.i_pc_gen.un1_pc_add14                cyclone_lcell        cout        Out     0.034     16.878      -         
un1_pc_carry_14                                          Net                  -           -       0.000     -           1         
mips_core.iRF_stage.i_pc_gen.un1_pc_add15                cyclone_lcell        cin         In      -         16.878      -         
mips_core.iRF_stage.i_pc_gen.un1_pc_add15                cyclone_lcell        cout        Out     0.034     16.912      -         
un1_pc_carry_15                                          Net                  -           -       0.000     -           1         
mips_core.iRF_stage.i_pc_gen.un1_pc_add16                cyclone_lcell        cin         In      -         16.912      -         
mips_core.iRF_stage.i_pc_gen.un1_pc_add16                cyclone_lcell        cout        Out     0.034     16.946      -         
un1_pc_carry_16                                          Net                  -           -       0.000     -           1         
mips_core.iRF_stage.i_pc_gen.un1_pc_add17                cyclone_lcell        cin         In      -         16.946      -         
mips_core.iRF_stage.i_pc_gen.un1_pc_add17                cyclone_lcell        cout        Out     0.034     16.980      -         
un1_pc_carry_17                                          Net                  -           -       0.000     -           1         
mips_core.iRF_stage.i_pc_gen.un1_pc_add18                cyclone_lcell        cin         In      -         16.980      -         
mips_core.iRF_stage.i_pc_gen.un1_pc_add18                cyclone_lcell        cout        Out     0.034     17.014      -         
un1_pc_carry_18                                          Net                  -           -       0.000     -           1         
mips_core.iRF_stage.i_pc_gen.un1_pc_add19                cyclone_lcell        cin         In      -         17.014      -         
mips_core.iRF_stage.i_pc_gen.un1_pc_add19                cyclone_lcell        cout        Out     0.034     17.048      -         
un1_pc_carry_19                                          Net                  -           -       0.000     -           1         
mips_core.iRF_stage.i_pc_gen.un1_pc_add20                cyclone_lcell        cin         In      -         17.048      -         
mips_core.iRF_stage.i_pc_gen.un1_pc_add20                cyclone_lcell        cout        Out     0.034     17.082      -         
un1_pc_carry_20                                          Net                  -           -       0.000     -           1         
mips_core.iRF_stage.i_pc_gen.un1_pc_add21                cyclone_lcell        cin         In      -         17.082      -         
mips_core.iRF_stage.i_pc_gen.un1_pc_add21                cyclone_lcell        cout        Out     0.034     17.116      -         
un1_pc_carry_21                                          Net                  -           -       0.000     -           1         
mips_core.iRF_stage.i_pc_gen.un1_pc_add22                cyclone_lcell        cin         In      -         17.116      -         
mips_core.iRF_stage.i_pc_gen.un1_pc_add22                cyclone_lcell        cout        Out     0.034     17.150      -         
un1_pc_carry_22                                          Net                  -           -       0.000     -           1         
mips_core.iRF_stage.i_pc_gen.un1_pc_add23                cyclone_lcell        cin         In      -         17.150      -         
mips_core.iRF_stage.i_pc_gen.un1_pc_add23                cyclone_lcell        cout        Out     0.034     17.184      -         
un1_pc_carry_23                                          Net                  -           -       0.000     -           1         
mips_core.iRF_stage.i_pc_gen.un1_pc_add24                cyclone_lcell        cin         In      -         17.184      -         
mips_core.iRF_stage.i_pc_gen.un1_pc_add24                cyclone_lcell        cout        Out     0.034     17.218      -         
un1_pc_carry_24                                          Net                  -           -       0.000     -           1         
mips_core.iRF_stage.i_pc_gen.un1_pc_add25                cyclone_lcell        cin         In      -         17.218      -         
mips_core.iRF_stage.i_pc_gen.un1_pc_add25                cyclone_lcell        cout        Out     0.034     17.252      -         
un1_pc_carry_25                                          Net                  -           -       0.000     -           1         
mips_core.iRF_stage.i_pc_gen.un1_pc_add26                cyclone_lcell        cin         In      -         17.252      -         
mips_core.iRF_stage.i_pc_gen.un1_pc_add26                cyclone_lcell        cout        Out     0.034     17.286      -         
un1_pc_carry_26                                          Net                  -           -       0.000     -           1         
mips_core.iRF_stage.i_pc_gen.un1_pc_add27                cyclone_lcell        cin         In      -         17.286      -         
mips_core.iRF_stage.i_pc_gen.un1_pc_add27                cyclone_lcell        cout        Out     0.034     17.320      -         
un1_pc_carry_27                                          Net                  -           -       0.000     -           1         
mips_core.iRF_stage.i_pc_gen.un1_pc_add28                cyclone_lcell        cin         In      -         17.320      -         
mips_core.iRF_stage.i_pc_gen.un1_pc_add28                cyclone_lcell        cout        Out     0.034     17.354      -         
un1_pc_carry_28                                          Net                  -           -       0.000     -           1         
mips_core.iRF_stage.i_pc_gen.un1_pc_add29                cyclone_lcell        cin         In      -         17.354      -         
mips_core.iRF_stage.i_pc_gen.un1_pc_add29                cyclone_lcell        cout        Out     0.034     17.388      -         
un1_pc_carry_29                                          Net                  -           -       0.000     -           1         
mips_core.iRF_stage.i_pc_gen.un1_pc_add30                cyclone_lcell        cin         In      -         17.388      -         
mips_core.iRF_stage.i_pc_gen.un1_pc_add30                cyclone_lcell        cout        Out     0.034     17.422      -         
un1_pc_carry_30                                          Net                  -           -       0.000     -           1         
mips_core.iRF_stage.i_pc_gen.un1_pc_add31                cyclone_lcell        cin         In      -         17.422      -         
mips_core.iRF_stage.i_pc_gen.un1_pc_add31                cyclone_lcell        combout     Out     0.621     18.043      -         
un1_pc_add31                                             Net                  -           -       0.319     -           1         
mips_core.pc.r32_o[31]                                   cyclone_lcell_ff     datad       In      -         18.362      -         
==================================================================================================================================
Total path delay (propagation time + setup) of 18.399 is 7.690(41.8%) logic and 10.709(58.2%) route.




====================================
Detailed Report for Clock: System
====================================



Starting Points with Worst Slack
********************************

                                                    Starting                                                Arrival           
Instance                                            Reference     Type             Pin       Net            Time        Slack 
                                                    Clock                                                                     
------------------------------------------------------------------------------------------------------------------------------
imips_dvc.iuart0.uart_txd.fifo.scfifo_component     System        scfifo_Z1        empty     empty          0.599       17.301
mips_core.decoder_pipe.idecoder.fsm_dly_1[1]        System        SYNLPM_LATR1     Q[0]      BUS197_1       0.224       18.119
mips_core.decoder_pipe.idecoder.fsm_dly_1[2]        System        SYNLPM_LATR1     Q[0]      BUS197_2       0.224       18.447
mips_core.MEM_CTL.i_mem_dout_ctl.dout_1[0]          System        SYNLPM_LATR1     Q[0]      BUS22401_0     0.224       19.420
mips_core.MEM_CTL.i_mem_dout_ctl.dout_1[1]          System        SYNLPM_LATR1     Q[0]      BUS22401_1     0.224       19.420
mips_core.MEM_CTL.i_mem_dout_ctl.dout_1[2]          System        SYNLPM_LATR1     Q[0]      BUS22401_2     0.224       19.420
mips_core.MEM_CTL.i_mem_dout_ctl.dout_1[3]          System        SYNLPM_LATR1     Q[0]      BUS22401_3     0.224       19.420
mips_core.MEM_CTL.i_mem_dout_ctl.dout_1[4]          System        SYNLPM_LATR1     Q[0]      BUS22401_4     0.224       19.420
mips_core.MEM_CTL.i_mem_dout_ctl.dout_1[5]          System        SYNLPM_LATR1     Q[0]      BUS22401_5     0.224       19.420
mips_core.MEM_CTL.i_mem_dout_ctl.dout_1[6]          System        SYNLPM_LATR1     Q[0]      BUS22401_6     0.224       19.420
==============================================================================================================================


Ending Points with Worst Slack
******************************

                                                    Starting                                                                       Required           
Instance                                            Reference     Type                 Pin         Net                             Time         Slack 
                                                    Clock                                                                                             
------------------------------------------------------------------------------------------------------------------------------------------------------
imips_dvc.iuart0.uart_txd.fifo.scfifo_component     System        scfifo_Z1            rdreq       ua_state_ns_0_a2_0_0            19.401       17.301
mips_core.iRF_stage.MIAN_FSM.CurrState_Sreg0[1]     System        cyclone_lcell_ff     datab       CurrState_Sreg0_ns_0_0_a[1]     19.963       18.119
mips_core.decoder_pipe.idecoder.fsm_dly_1[1]        System        SYNLPM_LATR1         DATA[0]     fsm_dly_2_i_m3_0[1]             19.963       18.447
mips_core.decoder_pipe.idecoder.fsm_dly_1[2]        System        SYNLPM_LATR1         DATA[0]     fsm_dly_2_0_0[2]                19.963       18.447
imips_dvc.iuart0.uart_txd.read_request_ff           System        cyclone_lcell_ff     dataa       empty                           19.963       18.772
imips_dvc.iuart0.uart_txd.ua_state[1]               System        cyclone_lcell_ff     dataa       empty                           19.963       18.772
imips_dvc.iuart0.uart_txd.ua_state_i[0]             System        cyclone_lcell_ff     dataa       empty                           19.963       18.772
mips_core.iRF_stage.MIAN_FSM.CurrState_Sreg0[2]     System        cyclone_lcell_ff     datab       BUS197_1                        19.963       18.880
mips_core.iRF_stage.MIAN_FSM.CurrState_Sreg0[2]     System        cyclone_lcell_ff     datac       BUS197_2                        19.963       18.880
mips_core.iRF_stage.MIAN_FSM.CurrState_Sreg0[3]     System        cyclone_lcell_ff     datab       BUS197_1                        19.963       18.880
======================================================================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
    Requested Period:                        20.000
    - Setup time:                            0.599
    = Required time:                         19.401

    - Propagation time:                      2.100
    = Slack (non-critical) :                 17.301

    Number of logic level(s):                1
    Starting point:                          imips_dvc.iuart0.uart_txd.fifo.scfifo_component / empty
    Ending point:                            imips_dvc.iuart0.uart_txd.fifo.scfifo_component / rdreq
    The start point is clocked by            System [rising]
    The end   point is clocked by            System [rising]

Instance / Net                                                        Pin         Pin               Arrival     No. of    
Name                                                Type              Name        Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------------------------------
imips_dvc.iuart0.uart_txd.fifo.scfifo_component     scfifo_Z1         empty       Out     0.000     0.599       -         
empty                                               Net               -           -       0.593     -           4         
imips_dvc.iuart0.uart_txd.ua_state_ns_0_a2_0[1]     cyclone_lcell     dataa       In      -         1.192       -         
imips_dvc.iuart0.uart_txd.ua_state_ns_0_a2_0[1]     cyclone_lcell     combout     Out     0.590     1.782       -         
ua_state_ns_0_a2_0[1]                               Net               -           -       0.319     -           1         
imips_dvc.iuart0.uart_txd.fifo.scfifo_component     scfifo_Z1         rdreq       In      -         2.100       -         
==========================================================================================================================
Total path delay (propagation time + setup) of 2.699 is 1.189(44.0%) logic and 0.912(33.8%) route.



##### END OF TIMING REPORT #####]

##### START OF AREA REPORT #####[
Design view:work.mips_sys(verilog)
Selecting part EP1C6Q240C8
@N: FA174 |The following device usage report estimates place and route data. Please look at the place and route report for final resource usage..

I/O ATOMs:       197

Total LUTs:  3334 of 5980 (55%)
Logic resources:  3467 ATOMs of 5980 (57%)
ATOM count by mode:
  normal:       3054
  arithmetic:   413

ShiftTap:       0  (0 registers)
Total ESB:      2048 bits   (2% of 81920)

LPM latches:    72

ATOMs using regout pin: 794
  also using enable pin: 310
  also using combout pin: 255
ATOMs using combout pin: 2829
Number of Inputs on ATOMs: 12612
Number of Nets:   10676

##### END OF AREA REPORT #####]

Mapper successful!
Process took 0h:1m:32s realtime, 0h:1m:32s cputime
###########################################################]

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