Subversion Repositories mips789

vendor_name = Synplicity
source_file = 0, noname, synplify
source_file = 1, c:\program files\synplicity\fpga_81\lib\altera\altera.v, synplify
source_file = 2, c:\program files\synplicity\fpga_81\lib\altera\cyclone.v, synplify
source_file = 3, c:\program files\synplicity\fpga_81\lib\altera\altera_mf.v, synplify
source_file = 4, c:\program files\synplicity\fpga_81\lib\altera\altera_lpm.v, synplify
source_file = 5, e:\mips789\mips789\rtl\verilog\exec_stage.v, synplify
source_file = 6, e:\mips789\mips789\rtl\verilog\include.h, synplify
source_file = 7, e:\mips789\mips789\rtl\verilog\rf_components.v, synplify
source_file = 8, e:\mips789\mips789\rtl\verilog\rf_stage.v, synplify
source_file = 9, e:\mips789\mips789\rtl\verilog\ctl_fsm.v, synplify
source_file = 10, e:\mips789\mips789\rtl\verilog\decode_pipe.v, synplify
source_file = 11, e:\mips789\mips789\rtl\verilog\dvc.v, synplify
source_file = 12, e:\mips789\mips789\rtl\verilog\fifo.v, synplify
source_file = 13, e:\mips789\mips789\rtl\verilog\forward.v, synplify
source_file = 14, e:\mips789\mips789\rtl\verilog\mem_module.v, synplify
source_file = 15, e:\mips789\mips789\rtl\verilog\mips_core.v, synplify
source_file = 16, e:\mips789\mips789\rtl\verilog\mips_dvc.v, synplify
source_file = 17, e:\mips789\mips789\rtl\verilog\mips_sys.v, synplify
source_file = 18, e:\mips789\mips789\rtl\verilog\mips_uart.v, synplify
source_file = 19, e:\mips789\mips789\rtl\verilog\ram_module.v, synplify
source_file = 20, e:\mips789\mips789\rtl\verilog\sim_ram.v, synplify
source_file = 21, e:\mips789\mips789\rtl\verilog\ulit.v, synplify
source_file = 22, e:\mips789\mips789\rtl\verilog\altera\fifo512_cyclone.v, synplify
design_name=r5_reg_cls
instance = port, r5_i[4:0], , r5_reg_cls, 21, 172:37:172:40
instance = port, r5_o[4:0], , r5_reg_cls, 21, 172:66:172:69
instance = port, clk, , r5_reg_cls, 21, 172:77:172:79
instance = port, cls, , r5_reg_cls, 21, 172:87:172:89
instance = comp, r5_o_4__Z, , r5_reg_cls, 21, 172:92:172:97
instance = comp, r5_o_3__Z, , r5_reg_cls, 21, 172:92:172:97
instance = comp, r5_o_2__Z, , r5_reg_cls, 21, 172:92:172:97
instance = comp, r5_o_1__Z, , r5_reg_cls, 21, 172:92:172:97
instance = comp, r5_o_0__Z, , r5_reg_cls, 21, 172:92:172:97
instance = comp, cls_in, , r5_reg_cls, 21, 172:87:172:89
instance = comp, clk_in, , r5_reg_cls, 21, 172:77:172:79
instance = comp, r5_i_in_4_, , r5_reg_cls, 21, 172:37:172:40
instance = comp, r5_i_in_3_, , r5_reg_cls, 21, 172:37:172:40
instance = comp, r5_i_in_2_, , r5_reg_cls, 21, 172:37:172:40
instance = comp, r5_i_in_1_, , r5_reg_cls, 21, 172:37:172:40
instance = comp, r5_i_in_0_, , r5_reg_cls, 21, 172:37:172:40
instance = comp, r5_o_out_4_, , r5_reg_cls, 21, 172:66:172:69
instance = comp, r5_o_out_3_, , r5_reg_cls, 21, 172:66:172:69
instance = comp, r5_o_out_2_, , r5_reg_cls, 21, 172:66:172:69
instance = comp, r5_o_out_1_, , r5_reg_cls, 21, 172:66:172:69
instance = comp, r5_o_out_0_, , r5_reg_cls, 21, 172:66:172:69