URL https://opencores.org/ocsvn/mips789/mips789/trunk
Subversion Repositories mips789

[/] [mips789/] [branches/] [avendor/] [synplify_prj/] [rev_1/] [mips_sys.tlg] - Rev 15

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Selecting top level module mips_sys
@N:"E:\mips789\mips789\rtl\verilog\mem_module.v":78:7:78:25|Synthesizing module infile_dmem_ctl_reg

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <30> of dmem_addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <29> of dmem_addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <28> of dmem_addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <27> of dmem_addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <26> of dmem_addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <25> of dmem_addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <24> of dmem_addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <23> of dmem_addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <22> of dmem_addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <21> of dmem_addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <20> of dmem_addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <19> of dmem_addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <18> of dmem_addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <17> of dmem_addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <16> of dmem_addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <15> of dmem_addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <14> of dmem_addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <13> of dmem_addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <12> of dmem_addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <11> of dmem_addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <10> of dmem_addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <9> of dmem_addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <8> of dmem_addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <7> of dmem_addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <6> of dmem_addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <5> of dmem_addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <4> of dmem_addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <3> of dmem_addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <2> of dmem_addr_i[31:0] is unused

@N:"E:\mips789\mips789\rtl\verilog\mem_module.v":96:7:96:18|Synthesizing module mem_addr_ctl

@W: CL118 :"E:\mips789\mips789\rtl\verilog\mem_module.v":102:4:102:7|Latch generated from always block for signal wr_en[3:0], probably caused by a missing assignment in an if or case stmt
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <31> of addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <30> of addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <29> of addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <28> of addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <27> of addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <26> of addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <25> of addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <24> of addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <23> of addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <22> of addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <21> of addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <20> of addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <19> of addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <18> of addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <17> of addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <16> of addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <15> of addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <14> of addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <13> of addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <12> of addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <11> of addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <10> of addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <9> of addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <8> of addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <7> of addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <6> of addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <5> of addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <4> of addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <3> of addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <2> of addr_i[31:0] is unused

@N:"E:\mips789\mips789\rtl\verilog\mem_module.v":199:7:199:17|Synthesizing module mem_din_ctl

@N:"E:\mips789\mips789\rtl\verilog\mem_module.v":130:7:130:18|Synthesizing module mem_dout_ctl

@W: CL118 :"E:\mips789\mips789\rtl\verilog\mem_module.v":161:4:161:7|Latch generated from always block for signal dout[31:0], probably caused by a missing assignment in an if or case stmt
@N:"E:\mips789\mips789\rtl\verilog\mem_module.v":4:7:4:16|Synthesizing module mem_module

@N:"E:\mips789\mips789\rtl\verilog\ulit.v":3:7:3:13|Synthesizing module cal_cpi

@N:"E:\mips789\mips789\rtl\verilog\ctl_fsm.v":2:7:2:13|Synthesizing module ctl_FSM

@W: CL118 :"E:\mips789\mips789\rtl\verilog\ctl_fsm.v":58:8:58:11|Latch generated from always block for signal zz_is_nop, probably caused by a missing assignment in an if or case stmt
@W: CL113 :"E:\mips789\mips789\rtl\verilog\ctl_fsm.v":58:8:58:11|Feedback mux created for signal iack.
@W: CL118 :"E:\mips789\mips789\rtl\verilog\ctl_fsm.v":58:8:58:11|Latch generated from always block for signal iack, probably caused by a missing assignment in an if or case stmt
@W: CL118 :"E:\mips789\mips789\rtl\verilog\ctl_fsm.v":58:8:58:11|Latch generated from always block for signal next_delay_counter_Sreg0[5:0], probably caused by a missing assignment in an if or case stmt
@N: CL201 :"E:\mips789\mips789\rtl\verilog\ctl_fsm.v":255:4:255:9|Trying to extract state machine for register CurrState_Sreg0
Extracted state machine for register CurrState_Sreg0
State machine has 9 reachable states with original encodings of:
   0000
   0001
   0010
   0011
   0100
   0101
   0110
   0111
   1000
@N:"E:\mips789\mips789\rtl\verilog\RF_components.v":49:7:49:12|Synthesizing module pc_gen

@N:"E:\mips789\mips789\rtl\verilog\RF_components.v":30:7:30:13|Synthesizing module compare

@N:"E:\mips789\mips789\rtl\verilog\RF_components.v":2:7:2:9|Synthesizing module ext

@W:"E:\mips789\mips789\rtl\verilog\RF_components.v":3:21:3:25|Input port bit <31> of ins_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\RF_components.v":3:21:3:25|Input port bit <30> of ins_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\RF_components.v":3:21:3:25|Input port bit <29> of ins_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\RF_components.v":3:21:3:25|Input port bit <28> of ins_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\RF_components.v":3:21:3:25|Input port bit <27> of ins_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\RF_components.v":3:21:3:25|Input port bit <26> of ins_i[31:0] is unused

@N:"E:\mips789\mips789\rtl\verilog\ulit.v":103:7:103:21|Synthesizing module r32_reg_clr_cls

@N: CG179 :"E:\mips789\mips789\rtl\verilog\ulit.v":103:167:103:171|Removing redundant assignment
@N:"E:\mips789\mips789\rtl\verilog\ulit.v":30:7:30:10|Synthesizing module jack

@W:"E:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|Input port bit <31> of ins_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|Input port bit <30> of ins_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|Input port bit <29> of ins_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|Input port bit <28> of ins_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|Input port bit <27> of ins_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|Input port bit <26> of ins_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|Input port bit <10> of ins_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|Input port bit <9> of ins_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|Input port bit <8> of ins_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|Input port bit <7> of ins_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|Input port bit <6> of ins_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|Input port bit <5> of ins_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|Input port bit <4> of ins_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|Input port bit <3> of ins_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|Input port bit <2> of ins_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|Input port bit <1> of ins_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|Input port bit <0> of ins_i[31:0] is unused

@N:"E:\mips789\mips789\rtl\verilog\ulit.v":64:7:64:12|Synthesizing module rd_sel

@N:"E:\mips789\mips789\rtl\verilog\RF_components.v":89:7:89:15|Synthesizing module reg_array

@N: CL134 :"E:\mips789\mips789\rtl\verilog\RF_components.v":139:4:139:9|Found RAM reg_bank, depth=32, width=32
@N: CL134 :"E:\mips789\mips789\rtl\verilog\RF_components.v":139:4:139:9|Found RAM reg_bank, depth=32, width=32
@N:"E:\mips789\mips789\rtl\verilog\forward.v":25:7:25:13|Synthesizing module fwd_mux

@N:"E:\mips789\mips789\rtl\verilog\RF_stage.v":3:7:3:14|Synthesizing module rf_stage

@W: CS149 :"E:\mips789\mips789\rtl\verilog\RF_stage.v":91:24:91:29|Port width mismatch for port ins_no.  Formal has width 101, Actual 1
@W: CS149 :"E:\mips789\mips789\rtl\verilog\RF_stage.v":90:24:90:29|Port width mismatch for port clk_no.  Formal has width 101, Actual 1
@W: CL168 :"E:\mips789\mips789\rtl\verilog\RF_stage.v":87:12:87:18|Pruning instance CAL_CPI - not in use ...

@N:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":512:7:512:15|Synthesizing module muldiv_ff

@W: CL169 :"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":563:4:563:9|Pruning Register LAST_CYCLE_DEAL_SECTION.eqop2 

@W: CL169 :"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":563:4:563:9|Pruning Register LAST_CYCLE_DEAL_SECTION.eqnop2 

@W: CL169 :"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":563:4:563:9|Pruning Register LAST_CYCLE_DEAL_SECTION.LAST_CYCLE_DEAL_SECTION_DEFAULT.op1s_eq_op2s 

@W: CL169 :"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":563:4:563:9|Pruning Register START_SECTION.over[32:0] 

@W: CL169 :"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":563:4:563:9|Pruning Register LAST_CYCLE_DEAL_SECTION.LAST_CYCLE_DEAL_SECTION_DEFAULT.op1s_eq_h64 

@W: CL169 :"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":563:4:563:9|Pruning Register LAST_CYCLE_DEAL_SECTION.eqz 

@N:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":227:7:227:9|Synthesizing module alu

@N:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":259:4:259:14|Synthesizing module shifter_tak

@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":263:25:263:50|Input port bit <31> of shift_amount[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":263:25:263:50|Input port bit <30> of shift_amount[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":263:25:263:50|Input port bit <29> of shift_amount[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":263:25:263:50|Input port bit <28> of shift_amount[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":263:25:263:50|Input port bit <27> of shift_amount[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":263:25:263:50|Input port bit <26> of shift_amount[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":263:25:263:50|Input port bit <25> of shift_amount[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":263:25:263:50|Input port bit <24> of shift_amount[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":263:25:263:50|Input port bit <23> of shift_amount[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":263:25:263:50|Input port bit <22> of shift_amount[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":263:25:263:50|Input port bit <21> of shift_amount[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":263:25:263:50|Input port bit <20> of shift_amount[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":263:25:263:50|Input port bit <19> of shift_amount[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":263:25:263:50|Input port bit <18> of shift_amount[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":263:25:263:50|Input port bit <17> of shift_amount[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":263:25:263:50|Input port bit <16> of shift_amount[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":263:25:263:50|Input port bit <15> of shift_amount[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":263:25:263:50|Input port bit <14> of shift_amount[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":263:25:263:50|Input port bit <13> of shift_amount[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":263:25:263:50|Input port bit <12> of shift_amount[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":263:25:263:50|Input port bit <11> of shift_amount[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":263:25:263:50|Input port bit <10> of shift_amount[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":263:25:263:50|Input port bit <9> of shift_amount[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":263:25:263:50|Input port bit <8> of shift_amount[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":263:25:263:50|Input port bit <7> of shift_amount[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":263:25:263:50|Input port bit <6> of shift_amount[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":263:25:263:50|Input port bit <5> of shift_amount[31:0] is unused

@N:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":132:7:132:13|Synthesizing module big_alu

@N:"E:\mips789\mips789\rtl\verilog\ulit.v":22:7:22:11|Synthesizing module add32

@N:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":182:7:182:14|Synthesizing module alu_muxa

@N:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":206:7:206:14|Synthesizing module alu_muxb

@N:"E:\mips789\mips789\rtl\verilog\ulit.v":149:7:149:13|Synthesizing module r32_reg

@N:"E:\mips789\mips789\rtl\verilog\ulit.v":172:7:172:17|Synthesizing module r32_reg_cls

@N: CG179 :"E:\mips789\mips789\rtl\verilog\ulit.v":172:132:172:136|Removing redundant assignment
@N:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":3:7:3:16|Synthesizing module exec_stage

@N:"E:\mips789\mips789\rtl\verilog\ulit.v":54:7:54:10|Synthesizing module or32

@N:"E:\mips789\mips789\rtl\verilog\decode_pipe.v":2:7:2:13|Synthesizing module decoder

@W: CL118 :"E:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Latch generated from always block for signal alu_func[4:0], probably caused by a missing assignment in an if or case stmt
@W: CL118 :"E:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Latch generated from always block for signal pc_gen_ctl[2:0], probably caused by a missing assignment in an if or case stmt
@W: CL118 :"E:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Latch generated from always block for signal fsm_dly[2:0], probably caused by a missing assignment in an if or case stmt
@W: CL118 :"E:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Latch generated from always block for signal ext_ctl[2:0], probably caused by a missing assignment in an if or case stmt
@W: CL118 :"E:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Latch generated from always block for signal rd_sel[1:0], probably caused by a missing assignment in an if or case stmt
@W: CL118 :"E:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Latch generated from always block for signal muxb_ctl[1:0], probably caused by a missing assignment in an if or case stmt
@W: CL118 :"E:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Latch generated from always block for signal muxa_ctl[1:0], probably caused by a missing assignment in an if or case stmt
@W: CL118 :"E:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Latch generated from always block for signal alu_we[0], probably caused by a missing assignment in an if or case stmt
@W: CL118 :"E:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Latch generated from always block for signal dmem_ctl[3:0], probably caused by a missing assignment in an if or case stmt
@W: CL118 :"E:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Latch generated from always block for signal cmp_ctl[2:0], probably caused by a missing assignment in an if or case stmt
@W: CL118 :"E:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Latch generated from always block for signal wb_we[0], probably caused by a missing assignment in an if or case stmt
@W: CL118 :"E:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Latch generated from always block for signal wb_mux[0], probably caused by a missing assignment in an if or case stmt
@W:"E:\mips789\mips789\rtl\verilog\decode_pipe.v":3:20:3:24|Input port bit <15> of ins_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\decode_pipe.v":3:20:3:24|Input port bit <14> of ins_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\decode_pipe.v":3:20:3:24|Input port bit <13> of ins_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\decode_pipe.v":3:20:3:24|Input port bit <12> of ins_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\decode_pipe.v":3:20:3:24|Input port bit <11> of ins_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\decode_pipe.v":3:20:3:24|Input port bit <10> of ins_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\decode_pipe.v":3:20:3:24|Input port bit <9> of ins_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\decode_pipe.v":3:20:3:24|Input port bit <8> of ins_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\decode_pipe.v":3:20:3:24|Input port bit <7> of ins_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\decode_pipe.v":3:20:3:24|Input port bit <6> of ins_i[31:0] is unused

@N:"E:\mips789\mips789\rtl\verilog\ulit.v":89:7:89:26|Synthesizing module muxb_ctl_reg_clr_cls

@N: CG179 :"E:\mips789\mips789\rtl\verilog\ulit.v":89:202:89:211|Removing redundant assignment
@N:"E:\mips789\mips789\rtl\verilog\ulit.v":93:7:93:28|Synthesizing module wb_mux_ctl_reg_clr_cls

@N: CG179 :"E:\mips789\mips789\rtl\verilog\ulit.v":93:216:93:227|Removing redundant assignment
@N:"E:\mips789\mips789\rtl\verilog\ulit.v":94:7:94:23|Synthesizing module wb_we_reg_clr_cls

@N: CG179 :"E:\mips789\mips789\rtl\verilog\ulit.v":94:181:94:187|Removing redundant assignment
@N:"E:\mips789\mips789\rtl\verilog\ulit.v":140:7:140:15|Synthesizing module wb_we_reg

@N:"E:\mips789\mips789\rtl\verilog\ulit.v":116:7:116:24|Synthesizing module wb_mux_ctl_reg_clr

@N:"E:\mips789\mips789\rtl\verilog\ulit.v":112:7:112:22|Synthesizing module muxb_ctl_reg_clr

@N:"E:\mips789\mips789\rtl\verilog\ulit.v":115:7:115:22|Synthesizing module dmem_ctl_reg_clr

@N:"E:\mips789\mips789\rtl\verilog\ulit.v":113:7:113:22|Synthesizing module alu_func_reg_clr

@N:"E:\mips789\mips789\rtl\verilog\ulit.v":111:7:111:22|Synthesizing module muxa_ctl_reg_clr

@N:"E:\mips789\mips789\rtl\verilog\ulit.v":139:7:139:20|Synthesizing module wb_mux_ctl_reg

@N:"E:\mips789\mips789\rtl\verilog\ulit.v":117:7:117:19|Synthesizing module wb_we_reg_clr

@N:"E:\mips789\mips789\rtl\verilog\ulit.v":85:7:85:25|Synthesizing module cmp_ctl_reg_clr_cls

@N: CG179 :"E:\mips789\mips789\rtl\verilog\ulit.v":85:195:85:203|Removing redundant assignment
@N:"E:\mips789\mips789\rtl\verilog\ulit.v":114:7:114:20|Synthesizing module alu_we_reg_clr

@N:"E:\mips789\mips789\rtl\verilog\ulit.v":90:7:90:26|Synthesizing module alu_func_reg_clr_cls

@N: CG179 :"E:\mips789\mips789\rtl\verilog\ulit.v":90:202:90:211|Removing redundant assignment
@N:"E:\mips789\mips789\rtl\verilog\ulit.v":92:7:92:26|Synthesizing module dmem_ctl_reg_clr_cls

@N: CG179 :"E:\mips789\mips789\rtl\verilog\ulit.v":92:202:92:211|Removing redundant assignment
@N:"E:\mips789\mips789\rtl\verilog\ulit.v":83:7:83:25|Synthesizing module ext_ctl_reg_clr_cls

@N: CG179 :"E:\mips789\mips789\rtl\verilog\ulit.v":83:195:83:203|Removing redundant assignment
@N:"E:\mips789\mips789\rtl\verilog\ulit.v":84:7:84:24|Synthesizing module rd_sel_reg_clr_cls

@N: CG179 :"E:\mips789\mips789\rtl\verilog\ulit.v":84:188:84:195|Removing redundant assignment
@N:"E:\mips789\mips789\rtl\verilog\ulit.v":91:7:91:24|Synthesizing module alu_we_reg_clr_cls

@N: CG179 :"E:\mips789\mips789\rtl\verilog\ulit.v":91:188:91:195|Removing redundant assignment
@N:"E:\mips789\mips789\rtl\verilog\ulit.v":88:7:88:26|Synthesizing module muxa_ctl_reg_clr_cls

@N: CG179 :"E:\mips789\mips789\rtl\verilog\ulit.v":88:202:88:211|Removing redundant assignment
@N:"E:\mips789\mips789\rtl\verilog\ulit.v":86:7:86:28|Synthesizing module pc_gen_ctl_reg_clr_cls

@N: CG179 :"E:\mips789\mips789\rtl\verilog\ulit.v":86:216:86:227|Removing redundant assignment
@N:"E:\mips789\mips789\rtl\verilog\ulit.v":138:7:138:18|Synthesizing module dmem_ctl_reg

@N:"E:\mips789\mips789\rtl\verilog\decode_pipe.v":1090:7:1090:19|Synthesizing module pipelinedregs

@N:"E:\mips789\mips789\rtl\verilog\decode_pipe.v":1419:7:1419:17|Synthesizing module decode_pipe

@N:"E:\mips789\mips789\rtl\verilog\forward.v":12:7:12:18|Synthesizing module forward_node

@N:"E:\mips789\mips789\rtl\verilog\forward.v":4:7:4:15|Synthesizing module fw_latch5

@N:"E:\mips789\mips789\rtl\verilog\forward.v":41:7:41:13|Synthesizing module forward

@N:"E:\mips789\mips789\rtl\verilog\ulit.v":148:7:148:12|Synthesizing module r5_reg

@N:"E:\mips789\mips789\rtl\verilog\ulit.v":43:7:43:12|Synthesizing module wb_mux

@N:"E:\mips789\mips789\rtl\verilog\mips_core.v":3:7:3:15|Synthesizing module mips_core

@N:"E:\mips789\mips789\rtl\verilog\mips_uart.v":210:7:210:15|Synthesizing module uart_read

@N: CL201 :"E:\mips789\mips789\rtl\verilog\mips_uart.v":274:4:274:9|Trying to extract state machine for register ua_state
Extracted state machine for register ua_state
State machine has 5 reachable states with original encodings of:
   000
   001
   010
   011
   100
@N:"E:\mips789\mips789\rtl\verilog\mips_uart.v":3:7:3:11|Synthesizing module rxd_d

@N:"C:\Program Files\Synplicity\fpga_81\lib\altera\altera_mf.v":3709:7:3709:12|Synthesizing module scfifo

        lpm_width=32'b00000000000000000000000000001000
        lpm_widthu=32'b00000000000000000000000000001001
        lpm_numwords=32'b00000000000000000000001000000000
        lpm_showahead=24'b010011110100011001000110
        intended_device_family=56'b01000011011110010110001101101100011011110110111001100101
        almost_full_value=32'b00000000000000000000000000000000
        almost_empty_value=32'b00000000000000000000000000000000
        underflow_checking=16'b0100111101001110
        overflow_checking=16'b0100111101001110
        allow_rwcycle_when_full=24'b010011110100011001000110
        lpm_hint=152'b01010010010000010100110101011111010000100100110001001111010000110100101101011111010101000101100101010000010001010011110101000001010101010101010001001111
        use_eab=16'b0100111101001110
        add_ram_output_register=24'b010011110100011001000110
        maximum_depth=32'b00000000000000000000000000000000
        lpm_type=48'b011100110110001101100110011010010110011001101111
   Generated name = scfifo_Z1
@N:"E:\mips789\mips789\rtl\verilog\altera\fifo512_cyclone.v":42:7:42:21|Synthesizing module fifo512_cyclone

@N:"E:\mips789\mips789\rtl\verilog\mips_uart.v":70:7:70:16|Synthesizing module uart_write

@W: CG133 :"E:\mips789\mips789\rtl\verilog\mips_uart.v":94:9:94:20|No assignment to write_done_n
@N: CL201 :"E:\mips789\mips789\rtl\verilog\mips_uart.v":168:4:168:9|Trying to extract state machine for register ua_state
Extracted state machine for register ua_state
State machine has 8 reachable states with original encodings of:
   000
   001
   010
   011
   100
   101
   110
   111
@N:"E:\mips789\mips789\rtl\verilog\mips_uart.v":12:7:12:11|Synthesizing module uart0

@W:"E:\mips789\mips789\rtl\verilog\mips_uart.v":38:9:38:17|No assignment to wire w_rxd_clr

@N:"E:\mips789\mips789\rtl\verilog\dvc.v":52:7:52:16|Synthesizing module seg7led_cv

@N:"E:\mips789\mips789\rtl\verilog\dvc.v":43:7:43:11|Synthesizing module tmr_d

@N:"E:\mips789\mips789\rtl\verilog\dvc.v":3:7:3:10|Synthesizing module tmr0

@N:"E:\mips789\mips789\rtl\verilog\mips_dvc.v":3:7:3:14|Synthesizing module mips_dvc

@N:"E:\mips789\mips789\rtl\verilog\mips_sys.v":4:7:4:14|Synthesizing module mips_sys

@W:"E:\mips789\mips789\rtl\verilog\mips_sys.v":78:16:78:24|No assignment to wire data2core

@W:"E:\mips789\mips789\rtl\verilog\mips_sys.v":79:16:79:23|No assignment to wire data2mem

@W:"E:\mips789\mips789\rtl\verilog\mips_sys.v":80:16:80:23|No assignment to wire ins2core

@W:"E:\mips789\mips789\rtl\verilog\mips_sys.v":81:16:81:23|No assignment to wire mem_Addr

@W:"E:\mips789\mips789\rtl\verilog\mips_sys.v":82:16:82:17|No assignment to wire pc

@W:"E:\mips789\mips789\rtl\verilog\mips_sys.v":83:15:83:19|No assignment to wire wr_en
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[/] [mips789/] [branches/] [avendor/] [synplify_prj/] [rev_1/] [mips_sys.tlg] - Rev 15
