Subversion Repositories mips789

@TM:1223821882
@N: FA174 :"":0:0:0:-1|The following device usage report estimates place and route data. Please look at the place and route report for final resource usage..
@N: MF197 :"":0:0:0:-1|Retiming summary : 0 registers retimed to 0 
@N: MT195 :"":0:0:0:-1|This timing report estimates place and route data. Please look at the place and route timing report for final timing..
@N: MT197 :"":0:0:0:-1|Clock constraints cover only FF-to-FF paths associated with the clock..
@N:  :"c:\program files\synplicity\fpga_81\lib\altera\altera_mf.v":3709:7:3709:12|Synthesizing module scfifo
@N:  :"e:\mips789\mips789\rtl\verilog\altera\fifo512_cyclone.v":39:12:39:24|M
@N:  :"e:\mips789\mips789\rtl\verilog\altera\fifo512_cyclone.v":41:12:41:23|M
@N:  :"e:\mips789\mips789\rtl\verilog\altera\fifo512_cyclone.v":42:7:42:21|Synthesizing module fifo512_cyclone
@W: MT253 :"e:\mips789\mips789\rtl\verilog\altera\fifo512_cyclone.v":66:8:66:23|M
@N:  :"e:\mips789\mips789\rtl\verilog\altera\fifo512_cyclone.v":74:16:74:28|M
@N:  :"e:\mips789\mips789\rtl\verilog\altera\fifo512_cyclone.v":81:16:81:27|M
@N:  :"e:\mips789\mips789\rtl\verilog\ctl_fsm.v":2:7:2:13|Synthesizing module ctl_FSM
@W:  :"e:\mips789\mips789\rtl\verilog\ctl_fsm.v":58:8:58:11|M
@W: CG286 :"e:\mips789\mips789\rtl\verilog\ctl_fsm.v":58:8:58:11|M
@W: CL113 :"e:\mips789\mips789\rtl\verilog\ctl_fsm.v":58:8:58:11|M
@W: CL118 :"e:\mips789\mips789\rtl\verilog\ctl_fsm.v":58:8:58:11|M
@W: CL118 :"e:\mips789\mips789\rtl\verilog\ctl_fsm.v":58:8:58:11|M
@W: MO127 :"e:\mips789\mips789\rtl\verilog\ctl_fsm.v":58:8:58:11|M
@N:  :"e:\mips789\mips789\rtl\verilog\ctl_fsm.v":58:43:58:55|M
@N:  :"e:\mips789\mips789\rtl\verilog\ctl_fsm.v":58:57:58:65|M
@W: BN116 :"e:\mips789\mips789\rtl\verilog\ctl_fsm.v":138:16:138:16|M
@W: FA140 :"e:\mips789\mips789\rtl\verilog\ctl_fsm.v":138:16:138:16|M
@N: CL201 :"e:\mips789\mips789\rtl\verilog\ctl_fsm.v":255:4:255:9|M
@W:  :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":1:1:961:15|M
@N:  :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":2:7:2:13|Synthesizing module decoder
@W:  :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":3:20:3:24|M
@W:  :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":3:20:3:24|M
@W:  :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":3:20:3:24|M
@W:  :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":3:20:3:24|M
@W:  :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":3:20:3:24|M
@W:  :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":3:20:3:24|M
@W:  :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":3:20:3:24|M
@W:  :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":3:20:3:24|M
@W:  :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":3:20:3:24|M
@W:  :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":3:20:3:24|M
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|M
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|M
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|M
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|M
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|M
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|M
@W: CL118 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|M
@N:  :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:34:31:46|M
@N:  :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":34:45:34:57|M
@N:  :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":533:47:533:59|M
@N:  :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":835:49:835:61|M
@N:  :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":1090:7:1090:19|Synthesizing module pipelinedregs
@N:  :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":1419:7:1419:17|Synthesizing module decode_pipe
@N:  :"e:\mips789\mips789\rtl\verilog\dvc.v":3:7:3:10|Synthesizing module tmr0
@N:  :"e:\mips789\mips789\rtl\verilog\dvc.v":23:4:23:9|M
@N:  :"e:\mips789\mips789\rtl\verilog\dvc.v":43:7:43:11|Synthesizing module tmr_d
@W: BN116 :"e:\mips789\mips789\rtl\verilog\dvc.v":45:4:45:9|M
@N:  :"e:\mips789\mips789\rtl\verilog\dvc.v":52:7:52:16|Synthesizing module seg7led_cv
@N: MO106 :"e:\mips789\mips789\rtl\verilog\dvc.v":67:12:67:15|M
@N:  :"e:\mips789\mips789\rtl\verilog\exec_stage.v":3:7:3:16|Synthesizing module exec_stage
@N:  :"e:\mips789\mips789\rtl\verilog\exec_stage.v":132:7:132:13|Synthesizing module big_alu
@N:  :"e:\mips789\mips789\rtl\verilog\exec_stage.v":182:7:182:14|Synthesizing module alu_muxa
@N:  :"e:\mips789\mips789\rtl\verilog\exec_stage.v":206:7:206:14|Synthesizing module alu_muxb
@N:  :"e:\mips789\mips789\rtl\verilog\exec_stage.v":227:7:227:9|Synthesizing module alu
@N:  :"e:\mips789\mips789\rtl\verilog\exec_stage.v":259:4:259:14|Synthesizing module shifter_tak
@W:  :"e:\mips789\mips789\rtl\verilog\exec_stage.v":263:25:263:50|M
@W:  :"e:\mips789\mips789\rtl\verilog\exec_stage.v":263:25:263:50|M
@W:  :"e:\mips789\mips789\rtl\verilog\exec_stage.v":263:25:263:50|M
@W:  :"e:\mips789\mips789\rtl\verilog\exec_stage.v":263:25:263:50|M
@W:  :"e:\mips789\mips789\rtl\verilog\exec_stage.v":263:25:263:50|M
@W:  :"e:\mips789\mips789\rtl\verilog\exec_stage.v":263:25:263:50|M
@W:  :"e:\mips789\mips789\rtl\verilog\exec_stage.v":263:25:263:50|M
@W:  :"e:\mips789\mips789\rtl\verilog\exec_stage.v":263:25:263:50|M
@W:  :"e:\mips789\mips789\rtl\verilog\exec_stage.v":263:25:263:50|M
@W:  :"e:\mips789\mips789\rtl\verilog\exec_stage.v":263:25:263:50|M
@W:  :"e:\mips789\mips789\rtl\verilog\exec_stage.v":263:25:263:50|M
@W:  :"e:\mips789\mips789\rtl\verilog\exec_stage.v":263:25:263:50|M
@W:  :"e:\mips789\mips789\rtl\verilog\exec_stage.v":263:25:263:50|M
@W:  :"e:\mips789\mips789\rtl\verilog\exec_stage.v":263:25:263:50|M
@W:  :"e:\mips789\mips789\rtl\verilog\exec_stage.v":263:25:263:50|M
@W:  :"e:\mips789\mips789\rtl\verilog\exec_stage.v":263:25:263:50|M
@W:  :"e:\mips789\mips789\rtl\verilog\exec_stage.v":263:25:263:50|M
@W:  :"e:\mips789\mips789\rtl\verilog\exec_stage.v":263:25:263:50|M
@W:  :"e:\mips789\mips789\rtl\verilog\exec_stage.v":263:25:263:50|M
@W:  :"e:\mips789\mips789\rtl\verilog\exec_stage.v":263:25:263:50|M
@W:  :"e:\mips789\mips789\rtl\verilog\exec_stage.v":263:25:263:50|M
@W:  :"e:\mips789\mips789\rtl\verilog\exec_stage.v":263:25:263:50|M
@W:  :"e:\mips789\mips789\rtl\verilog\exec_stage.v":263:25:263:50|M
@W:  :"e:\mips789\mips789\rtl\verilog\exec_stage.v":263:25:263:50|M
@W:  :"e:\mips789\mips789\rtl\verilog\exec_stage.v":263:25:263:50|M
@W:  :"e:\mips789\mips789\rtl\verilog\exec_stage.v":263:25:263:50|M
@W:  :"e:\mips789\mips789\rtl\verilog\exec_stage.v":263:25:263:50|M
@N:  :"e:\mips789\mips789\rtl\verilog\exec_stage.v":512:7:512:15|Synthesizing module muldiv_ff
@N:  :"e:\mips789\mips789\rtl\verilog\exec_stage.v":563:4:563:9|M
@W: CL169 :"e:\mips789\mips789\rtl\verilog\exec_stage.v":563:4:563:9|M
@N:  :"e:\mips789\mips789\rtl\verilog\exec_stage.v":685:80:685:92|M
@N:  :"e:\mips789\mips789\rtl\verilog\forward.v":4:7:4:15|Synthesizing module fw_latch5
@N:  :"e:\mips789\mips789\rtl\verilog\forward.v":12:7:12:18|Synthesizing module forward_node
@N:  :"e:\mips789\mips789\rtl\verilog\forward.v":25:7:25:13|Synthesizing module fwd_mux
@N:  :"e:\mips789\mips789\rtl\verilog\forward.v":41:7:41:13|Synthesizing module forward
@N:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":4:7:4:16|Synthesizing module mem_module
@N:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":78:7:78:25|Synthesizing module infile_dmem_ctl_reg
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|M
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|M
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|M
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|M
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|M
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|M
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|M
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|M
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|M
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|M
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|M
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|M
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|M
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|M
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|M
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|M
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|M
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|M
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|M
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|M
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|M
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|M
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|M
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|M
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|M
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|M
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|M
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|M
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|M
@N:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":96:7:96:18|Synthesizing module mem_addr_ctl
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|M
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|M
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|M
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|M
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|M
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|M
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|M
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|M
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|M
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|M
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|M
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|M
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|M
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|M
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|M
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|M
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|M
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|M
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|M
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|M
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|M
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|M
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|M
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|M
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|M
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|M
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|M
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|M
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|M
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|M
@W: CL118 :"e:\mips789\mips789\rtl\verilog\mem_module.v":102:4:102:7|M
@N:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":130:7:130:18|Synthesizing module mem_dout_ctl
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":161:4:161:7|M
@W: CL118 :"e:\mips789\mips789\rtl\verilog\mem_module.v":161:4:161:7|M
@N:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":199:7:199:17|Synthesizing module mem_din_ctl
@N:  :"e:\mips789\mips789\rtl\verilog\mips_core.v":3:7:3:15|Synthesizing module mips_core
@N:  :"e:\mips789\mips789\rtl\verilog\mips_dvc.v":3:7:3:14|Synthesizing module mips_dvc
@W: BN116 :"e:\mips789\mips789\rtl\verilog\mips_dvc.v":113:4:113:9|M
@N:  :"e:\mips789\mips789\rtl\verilog\mips_sys.v":4:7:4:14|Synthesizing module mips_sys
@W:  :"e:\mips789\mips789\rtl\verilog\mips_sys.v":78:16:78:24|M
@W:  :"e:\mips789\mips789\rtl\verilog\mips_sys.v":79:16:79:23|M
@W:  :"e:\mips789\mips789\rtl\verilog\mips_sys.v":80:16:80:23|M
@W:  :"e:\mips789\mips789\rtl\verilog\mips_sys.v":81:16:81:23|M
@W:  :"e:\mips789\mips789\rtl\verilog\mips_sys.v":82:16:82:17|M
@W:  :"e:\mips789\mips789\rtl\verilog\mips_sys.v":83:15:83:19|M
@N:  :"e:\mips789\mips789\rtl\verilog\mips_uart.v":3:7:3:11|Synthesizing module rxd_d
@N:  :"e:\mips789\mips789\rtl\verilog\mips_uart.v":12:7:12:11|Synthesizing module uart0
@W:  :"e:\mips789\mips789\rtl\verilog\mips_uart.v":38:9:38:17|M
@N:  :"e:\mips789\mips789\rtl\verilog\mips_uart.v":70:7:70:16|Synthesizing module uart_write
@W: CG133 :"e:\mips789\mips789\rtl\verilog\mips_uart.v":94:9:94:20|M
@N:  :"e:\mips789\mips789\rtl\verilog\mips_uart.v":138:4:138:9|M
@N:  :"e:\mips789\mips789\rtl\verilog\mips_uart.v":151:4:151:9|M
@N: CL201 :"e:\mips789\mips789\rtl\verilog\mips_uart.v":168:4:168:9|M
@N:  :"e:\mips789\mips789\rtl\verilog\mips_uart.v":210:7:210:15|Synthesizing module uart_read
@N:  :"e:\mips789\mips789\rtl\verilog\mips_uart.v":243:4:243:9|M
@N:  :"e:\mips789\mips789\rtl\verilog\mips_uart.v":256:4:256:9|M
@N: CL201 :"e:\mips789\mips789\rtl\verilog\mips_uart.v":274:4:274:9|M
@N:  :"e:\mips789\mips789\rtl\verilog\rf_components.v":2:7:2:9|Synthesizing module ext
@W:  :"e:\mips789\mips789\rtl\verilog\rf_components.v":3:21:3:25|M
@W:  :"e:\mips789\mips789\rtl\verilog\rf_components.v":3:21:3:25|M
@W:  :"e:\mips789\mips789\rtl\verilog\rf_components.v":3:21:3:25|M
@W:  :"e:\mips789\mips789\rtl\verilog\rf_components.v":3:21:3:25|M
@W:  :"e:\mips789\mips789\rtl\verilog\rf_components.v":3:21:3:25|M
@W:  :"e:\mips789\mips789\rtl\verilog\rf_components.v":3:21:3:25|M
@N:  :"e:\mips789\mips789\rtl\verilog\rf_components.v":30:7:30:13|Synthesizing module compare
@N:  :"e:\mips789\mips789\rtl\verilog\rf_components.v":49:7:49:12|Synthesizing module pc_gen
@N:  :"e:\mips789\mips789\rtl\verilog\rf_components.v":89:7:89:15|Synthesizing module reg_array
@N: CL134 :"e:\mips789\mips789\rtl\verilog\rf_components.v":139:4:139:9|M
@N:  :"e:\mips789\mips789\rtl\verilog\rf_stage.v":3:7:3:14|Synthesizing module rf_stage
@W: CL168 :"e:\mips789\mips789\rtl\verilog\rf_stage.v":87:12:87:18|M
@W: CS149 :"e:\mips789\mips789\rtl\verilog\rf_stage.v":90:24:90:29|M
@W: CS149 :"e:\mips789\mips789\rtl\verilog\rf_stage.v":91:24:91:29|M
@N:  :"e:\mips789\mips789\rtl\verilog\ulit.v":3:7:3:13|Synthesizing module cal_cpi
@N:  :"e:\mips789\mips789\rtl\verilog\ulit.v":22:7:22:11|Synthesizing module add32
@N:  :"e:\mips789\mips789\rtl\verilog\ulit.v":30:7:30:10|Synthesizing module jack
@W:  :"e:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|M
@W:  :"e:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|M
@W:  :"e:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|M
@W:  :"e:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|M
@W:  :"e:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|M
@W:  :"e:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|M
@W:  :"e:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|M
@W:  :"e:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|M
@W:  :"e:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|M
@W:  :"e:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|M
@W:  :"e:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|M
@W:  :"e:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|M
@W:  :"e:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|M
@W:  :"e:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|M
@W:  :"e:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|M
@W:  :"e:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|M
@W:  :"e:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|M
@N:  :"e:\mips789\mips789\rtl\verilog\ulit.v":43:7:43:12|Synthesizing module wb_mux
@N:  :"e:\mips789\mips789\rtl\verilog\ulit.v":54:7:54:10|Synthesizing module or32
@N:  :"e:\mips789\mips789\rtl\verilog\ulit.v":64:7:64:12|Synthesizing module rd_sel
@N:  :"e:\mips789\mips789\rtl\verilog\ulit.v":83:7:83:25|Synthesizing module ext_ctl_reg_clr_cls
@N: CG179 :"e:\mips789\mips789\rtl\verilog\ulit.v":83:195:83:203|M
@N:  :"e:\mips789\mips789\rtl\verilog\ulit.v":84:7:84:24|Synthesizing module rd_sel_reg_clr_cls
@N: CG179 :"e:\mips789\mips789\rtl\verilog\ulit.v":84:188:84:195|M
@N:  :"e:\mips789\mips789\rtl\verilog\ulit.v":85:7:85:25|Synthesizing module cmp_ctl_reg_clr_cls
@N: CG179 :"e:\mips789\mips789\rtl\verilog\ulit.v":85:195:85:203|M
@N:  :"e:\mips789\mips789\rtl\verilog\ulit.v":86:7:86:28|Synthesizing module pc_gen_ctl_reg_clr_cls
@N: CG179 :"e:\mips789\mips789\rtl\verilog\ulit.v":86:216:86:227|M
@N:  :"e:\mips789\mips789\rtl\verilog\ulit.v":88:7:88:26|Synthesizing module muxa_ctl_reg_clr_cls
@N: CG179 :"e:\mips789\mips789\rtl\verilog\ulit.v":88:202:88:211|M
@N:  :"e:\mips789\mips789\rtl\verilog\ulit.v":89:7:89:26|Synthesizing module muxb_ctl_reg_clr_cls
@N: CG179 :"e:\mips789\mips789\rtl\verilog\ulit.v":89:202:89:211|M
@N:  :"e:\mips789\mips789\rtl\verilog\ulit.v":90:7:90:26|Synthesizing module alu_func_reg_clr_cls
@N: CG179 :"e:\mips789\mips789\rtl\verilog\ulit.v":90:202:90:211|M
@N:  :"e:\mips789\mips789\rtl\verilog\ulit.v":91:7:91:24|Synthesizing module alu_we_reg_clr_cls
@N: CG179 :"e:\mips789\mips789\rtl\verilog\ulit.v":91:188:91:195|M
@N:  :"e:\mips789\mips789\rtl\verilog\ulit.v":92:7:92:26|Synthesizing module dmem_ctl_reg_clr_cls
@N: CG179 :"e:\mips789\mips789\rtl\verilog\ulit.v":92:202:92:211|M
@N:  :"e:\mips789\mips789\rtl\verilog\ulit.v":93:7:93:28|Synthesizing module wb_mux_ctl_reg_clr_cls
@N: CG179 :"e:\mips789\mips789\rtl\verilog\ulit.v":93:216:93:227|M
@N:  :"e:\mips789\mips789\rtl\verilog\ulit.v":94:7:94:23|Synthesizing module wb_we_reg_clr_cls
@N: CG179 :"e:\mips789\mips789\rtl\verilog\ulit.v":94:181:94:187|M
@N:  :"e:\mips789\mips789\rtl\verilog\ulit.v":103:7:103:21|Synthesizing module r32_reg_clr_cls
@W: BN116 :"e:\mips789\mips789\rtl\verilog\ulit.v":103:111:103:116|M
@N: CG179 :"e:\mips789\mips789\rtl\verilog\ulit.v":103:167:103:171|M
@N:  :"e:\mips789\mips789\rtl\verilog\ulit.v":111:7:111:22|Synthesizing module muxa_ctl_reg_clr
@N:  :"e:\mips789\mips789\rtl\verilog\ulit.v":112:7:112:22|Synthesizing module muxb_ctl_reg_clr
@N:  :"e:\mips789\mips789\rtl\verilog\ulit.v":113:7:113:22|Synthesizing module alu_func_reg_clr
@N:  :"e:\mips789\mips789\rtl\verilog\ulit.v":114:7:114:20|Synthesizing module alu_we_reg_clr
@N:  :"e:\mips789\mips789\rtl\verilog\ulit.v":115:7:115:22|Synthesizing module dmem_ctl_reg_clr
@N:  :"e:\mips789\mips789\rtl\verilog\ulit.v":116:7:116:24|Synthesizing module wb_mux_ctl_reg_clr
@N:  :"e:\mips789\mips789\rtl\verilog\ulit.v":117:7:117:19|Synthesizing module wb_we_reg_clr
@N:  :"e:\mips789\mips789\rtl\verilog\ulit.v":138:7:138:18|Synthesizing module dmem_ctl_reg
@N:  :"e:\mips789\mips789\rtl\verilog\ulit.v":139:7:139:20|Synthesizing module wb_mux_ctl_reg
@N:  :"e:\mips789\mips789\rtl\verilog\ulit.v":140:7:140:15|Synthesizing module wb_we_reg
@N:  :"e:\mips789\mips789\rtl\verilog\ulit.v":148:7:148:12|Synthesizing module r5_reg
@N:  :"e:\mips789\mips789\rtl\verilog\ulit.v":149:7:149:13|Synthesizing module r32_reg
@W: BN132 :"e:\mips789\mips789\rtl\verilog\ulit.v":149:83:149:88|M
@N:  :"e:\mips789\mips789\rtl\verilog\ulit.v":172:7:172:17|Synthesizing module r32_reg_cls
@N: CG179 :"e:\mips789\mips789\rtl\verilog\ulit.v":172:132:172:136|M