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https://opencores.org/ocsvn/mips789/mips789/trunk
Subversion Repositories mips789
[/] [mips789/] [branches/] [avendor/] [synplify_prj/] [rev_1/] [syntmp/] [mips_sys_srr.htm] - Rev 55
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<!@TC:1223827000>
#Program: Synplify Pro 8.1
#OS: Windows_NT
<a name=compilerReport16>$ Start of Compile
#Sun Oct 12 23:56:39 2008
Synplicity Verilog Compiler, version 3.1.0, Build 049R, built May 3 2005
Copyright (C) 1994-2005, Synplicity Inc. All Rights Reserved
@I::"C:\Program Files\Synplicity\fpga_81\lib\altera\altera.v"
@I::"C:\Program Files\Synplicity\fpga_81\lib\altera\cyclone.v"
@I::"C:\Program Files\Synplicity\fpga_81\lib\altera\altera_mf.v"
@I::"C:\Program Files\Synplicity\fpga_81\lib\altera\altera_lpm.v"
@I::"E:\mips789\mips789\rtl\verilog\EXEC_stage.v"
@I:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":"E:\mips789\mips789\rtl\verilog\include.h"
@N: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:685:80:685:93:@N::@XP_MSG">exec_stage.v(685)</a><!@TM:1223827000> | Read parallel_case directive
@I::"E:\mips789\mips789\rtl\verilog\RF_components.v"
@I:"E:\mips789\mips789\rtl\verilog\RF_components.v":"E:\mips789\mips789\rtl\verilog\include.h"
@I::"E:\mips789\mips789\rtl\verilog\RF_stage.v"
@I:"E:\mips789\mips789\rtl\verilog\RF_stage.v":"E:\mips789\mips789\rtl\verilog\include.h"
@I::"E:\mips789\mips789\rtl\verilog\ctl_fsm.v"
@I:"E:\mips789\mips789\rtl\verilog\ctl_fsm.v":"E:\mips789\mips789\rtl\verilog\include.h"
@N: : <a href="e:\mips789\mips789\rtl\verilog\ctl_fsm.v:58:43:58:56:@N::@XP_MSG">ctl_fsm.v(58)</a><!@TM:1223827000> | Read parallel_case directive
@N: : <a href="e:\mips789\mips789\rtl\verilog\ctl_fsm.v:58:57:58:66:@N::@XP_MSG">ctl_fsm.v(58)</a><!@TM:1223827000> | Read full_case directive
<font color=#A52A2A>@W:<a href="@W:CG286:@XP_HELP">CG286</a> : <a href="e:\mips789\mips789\rtl\verilog\ctl_fsm.v:58:8:58:12:@W:CG286:@XP_MSG">ctl_fsm.v(58)</a><!@TM:1223827000> | Case statement has both a full_case directive and a default clause. The full_case directive is ignored.</font>
@I::"E:\mips789\mips789\rtl\verilog\decode_pipe.v"
@I:"E:\mips789\mips789\rtl\verilog\decode_pipe.v":"E:\mips789\mips789\rtl\verilog\include.h"
@N: : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:34:31:47:@N::@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827000> | Read parallel_case directive
@N: : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:34:45:34:58:@N::@XP_MSG">decode_pipe.v(34)</a><!@TM:1223827000> | Read parallel_case directive
@N: : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:533:47:533:60:@N::@XP_MSG">decode_pipe.v(533)</a><!@TM:1223827000> | Read parallel_case directive
@N: : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:835:49:835:62:@N::@XP_MSG">decode_pipe.v(835)</a><!@TM:1223827000> | Read parallel_case directive
@I::"E:\mips789\mips789\rtl\verilog\dvc.v"
@I:"E:\mips789\mips789\rtl\verilog\dvc.v":"E:\mips789\mips789\rtl\verilog\include.h"
@I::"E:\mips789\mips789\rtl\verilog\fifo.v"
@I:"E:\mips789\mips789\rtl\verilog\fifo.v":"E:\mips789\mips789\rtl\verilog\include.h"
@I::"E:\mips789\mips789\rtl\verilog\forward.v"
@I:"E:\mips789\mips789\rtl\verilog\forward.v":"E:\mips789\mips789\rtl\verilog\include.h"
@I::"E:\mips789\mips789\rtl\verilog\mem_module.v"
@I:"E:\mips789\mips789\rtl\verilog\mem_module.v":"E:\mips789\mips789\rtl\verilog\include.h"
@I::"E:\mips789\mips789\rtl\verilog\mips_core.v"
@I:"E:\mips789\mips789\rtl\verilog\mips_core.v":"E:\mips789\mips789\rtl\verilog\include.h"
@I::"E:\mips789\mips789\rtl\verilog\mips_dvc.v"
@I:"E:\mips789\mips789\rtl\verilog\mips_dvc.v":"E:\mips789\mips789\rtl\verilog\include.h"
@I::"E:\mips789\mips789\rtl\verilog\mips_sys.v"
@I:"E:\mips789\mips789\rtl\verilog\mips_sys.v":"E:\mips789\mips789\rtl\verilog\include.h"
@I::"E:\mips789\mips789\rtl\verilog\mips_uart.v"
@I:"E:\mips789\mips789\rtl\verilog\mips_uart.v":"E:\mips789\mips789\rtl\verilog\include.h"
@I::"E:\mips789\mips789\rtl\verilog\ram_module.v"
@I:"E:\mips789\mips789\rtl\verilog\ram_module.v":"E:\mips789\mips789\rtl\verilog\include.h"
@I::"E:\mips789\mips789\rtl\verilog\sim_ram.v"
@I::"E:\mips789\mips789\rtl\verilog\ulit.v"
@I:"E:\mips789\mips789\rtl\verilog\ulit.v":"E:\mips789\mips789\rtl\verilog\include.h"
@I::"E:\mips789\mips789\rtl\verilog\altera\fifo512_cyclone.v"
@N: : <a href="e:\mips789\mips789\rtl\verilog\altera\fifo512_cyclone.v:39:12:39:25:@N::@XP_MSG">fifo512_cyclone.v(39)</a><!@TM:1223827000> | Read directive translate_off
@N: : <a href="e:\mips789\mips789\rtl\verilog\altera\fifo512_cyclone.v:41:12:41:24:@N::@XP_MSG">fifo512_cyclone.v(41)</a><!@TM:1223827000> | Read directive translate_on
@N: : <a href="e:\mips789\mips789\rtl\verilog\altera\fifo512_cyclone.v:74:16:74:29:@N::@XP_MSG">fifo512_cyclone.v(74)</a><!@TM:1223827000> | Read directive translate_off
@N: : <a href="e:\mips789\mips789\rtl\verilog\altera\fifo512_cyclone.v:81:16:81:28:@N::@XP_MSG">fifo512_cyclone.v(81)</a><!@TM:1223827000> | Read directive translate_on
Verilog syntax check successful!
File E:\mips789\mips789\rtl\verilog\ctl_fsm.v changed - recompiling
Selecting top level module mips_sys
@N: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:78:7:78:26:@N::@XP_MSG">mem_module.v(78)</a><!@TM:1223827012> | Synthesizing module infile_dmem_ctl_reg
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1223827012> | Input port bit <30> of dmem_addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1223827012> | Input port bit <29> of dmem_addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1223827012> | Input port bit <28> of dmem_addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1223827012> | Input port bit <27> of dmem_addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1223827012> | Input port bit <26> of dmem_addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1223827012> | Input port bit <25> of dmem_addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1223827012> | Input port bit <24> of dmem_addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1223827012> | Input port bit <23> of dmem_addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1223827012> | Input port bit <22> of dmem_addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1223827012> | Input port bit <21> of dmem_addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1223827012> | Input port bit <20> of dmem_addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1223827012> | Input port bit <19> of dmem_addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1223827012> | Input port bit <18> of dmem_addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1223827012> | Input port bit <17> of dmem_addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1223827012> | Input port bit <16> of dmem_addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1223827012> | Input port bit <15> of dmem_addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1223827012> | Input port bit <14> of dmem_addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1223827012> | Input port bit <13> of dmem_addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1223827012> | Input port bit <12> of dmem_addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1223827012> | Input port bit <11> of dmem_addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1223827012> | Input port bit <10> of dmem_addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1223827012> | Input port bit <9> of dmem_addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1223827012> | Input port bit <8> of dmem_addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1223827012> | Input port bit <7> of dmem_addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1223827012> | Input port bit <6> of dmem_addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1223827012> | Input port bit <5> of dmem_addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1223827012> | Input port bit <4> of dmem_addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1223827012> | Input port bit <3> of dmem_addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1223827012> | Input port bit <2> of dmem_addr_i[31:0] is unused</font>
@N: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:96:7:96:19:@N::@XP_MSG">mem_module.v(96)</a><!@TM:1223827012> | Synthesizing module mem_addr_ctl
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:102:4:102:8:@W:CL118:@XP_MSG">mem_module.v(102)</a><!@TM:1223827012> | Latch generated from always block for signal wr_en[3:0], probably caused by a missing assignment in an if or case stmt</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1223827012> | Input port bit <31> of addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1223827012> | Input port bit <30> of addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1223827012> | Input port bit <29> of addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1223827012> | Input port bit <28> of addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1223827012> | Input port bit <27> of addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1223827012> | Input port bit <26> of addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1223827012> | Input port bit <25> of addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1223827012> | Input port bit <24> of addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1223827012> | Input port bit <23> of addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1223827012> | Input port bit <22> of addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1223827012> | Input port bit <21> of addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1223827012> | Input port bit <20> of addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1223827012> | Input port bit <19> of addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1223827012> | Input port bit <18> of addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1223827012> | Input port bit <17> of addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1223827012> | Input port bit <16> of addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1223827012> | Input port bit <15> of addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1223827012> | Input port bit <14> of addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1223827012> | Input port bit <13> of addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1223827012> | Input port bit <12> of addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1223827012> | Input port bit <11> of addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1223827012> | Input port bit <10> of addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1223827012> | Input port bit <9> of addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1223827012> | Input port bit <8> of addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1223827012> | Input port bit <7> of addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1223827012> | Input port bit <6> of addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1223827012> | Input port bit <5> of addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1223827012> | Input port bit <4> of addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1223827012> | Input port bit <3> of addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1223827012> | Input port bit <2> of addr_i[31:0] is unused</font>
@N: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:199:7:199:18:@N::@XP_MSG">mem_module.v(199)</a><!@TM:1223827012> | Synthesizing module mem_din_ctl
@N: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:130:7:130:19:@N::@XP_MSG">mem_module.v(130)</a><!@TM:1223827012> | Synthesizing module mem_dout_ctl
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:161:4:161:8:@W:CL118:@XP_MSG">mem_module.v(161)</a><!@TM:1223827012> | Latch generated from always block for signal dout[31:0], probably caused by a missing assignment in an if or case stmt</font>
@N: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:4:7:4:17:@N::@XP_MSG">mem_module.v(4)</a><!@TM:1223827012> | Synthesizing module mem_module
@N: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:3:7:3:14:@N::@XP_MSG">ulit.v(3)</a><!@TM:1223827012> | Synthesizing module cal_cpi
@N: : <a href="e:\mips789\mips789\rtl\verilog\ctl_fsm.v:2:7:2:14:@N::@XP_MSG">ctl_fsm.v(2)</a><!@TM:1223827012> | Synthesizing module ctl_FSM
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="e:\mips789\mips789\rtl\verilog\ctl_fsm.v:58:8:58:12:@W:CL118:@XP_MSG">ctl_fsm.v(58)</a><!@TM:1223827012> | Latch generated from always block for signal zz_is_nop, probably caused by a missing assignment in an if or case stmt</font>
<font color=#A52A2A>@W:<a href="@W:CL113:@XP_HELP">CL113</a> : <a href="e:\mips789\mips789\rtl\verilog\ctl_fsm.v:58:8:58:12:@W:CL113:@XP_MSG">ctl_fsm.v(58)</a><!@TM:1223827012> | Feedback mux created for signal iack.</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="e:\mips789\mips789\rtl\verilog\ctl_fsm.v:58:8:58:12:@W:CL118:@XP_MSG">ctl_fsm.v(58)</a><!@TM:1223827012> | Latch generated from always block for signal iack, probably caused by a missing assignment in an if or case stmt</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="e:\mips789\mips789\rtl\verilog\ctl_fsm.v:58:8:58:12:@W:CL118:@XP_MSG">ctl_fsm.v(58)</a><!@TM:1223827012> | Latch generated from always block for signal next_delay_counter_Sreg0[5:0], probably caused by a missing assignment in an if or case stmt</font>
@N:<a href="@N:CL201:@XP_HELP">CL201</a> : <a href="e:\mips789\mips789\rtl\verilog\ctl_fsm.v:255:4:255:10:@N:CL201:@XP_MSG">ctl_fsm.v(255)</a><!@TM:1223827012> | Trying to extract state machine for register CurrState_Sreg0
Extracted state machine for register CurrState_Sreg0
State machine has 9 reachable states with original encodings of:
0000
0001
0010
0011
0100
0101
0110
0111
1000
@N: : <a href="e:\mips789\mips789\rtl\verilog\rf_components.v:49:7:49:13:@N::@XP_MSG">rf_components.v(49)</a><!@TM:1223827012> | Synthesizing module pc_gen
@N: : <a href="e:\mips789\mips789\rtl\verilog\rf_components.v:30:7:30:14:@N::@XP_MSG">rf_components.v(30)</a><!@TM:1223827012> | Synthesizing module compare
@N: : <a href="e:\mips789\mips789\rtl\verilog\rf_components.v:2:7:2:10:@N::@XP_MSG">rf_components.v(2)</a><!@TM:1223827012> | Synthesizing module ext
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\rf_components.v:3:21:3:26:@W::@XP_MSG">rf_components.v(3)</a><!@TM:1223827012> | Input port bit <31> of ins_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\rf_components.v:3:21:3:26:@W::@XP_MSG">rf_components.v(3)</a><!@TM:1223827012> | Input port bit <30> of ins_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\rf_components.v:3:21:3:26:@W::@XP_MSG">rf_components.v(3)</a><!@TM:1223827012> | Input port bit <29> of ins_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\rf_components.v:3:21:3:26:@W::@XP_MSG">rf_components.v(3)</a><!@TM:1223827012> | Input port bit <28> of ins_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\rf_components.v:3:21:3:26:@W::@XP_MSG">rf_components.v(3)</a><!@TM:1223827012> | Input port bit <27> of ins_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\rf_components.v:3:21:3:26:@W::@XP_MSG">rf_components.v(3)</a><!@TM:1223827012> | Input port bit <26> of ins_i[31:0] is unused</font>
@N: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:103:7:103:22:@N::@XP_MSG">ulit.v(103)</a><!@TM:1223827012> | Synthesizing module r32_reg_clr_cls
@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:103:167:103:172:@N:CG179:@XP_MSG">ulit.v(103)</a><!@TM:1223827012> | Removing redundant assignment
@N: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:30:7:30:11:@N::@XP_MSG">ulit.v(30)</a><!@TM:1223827012> | Synthesizing module jack
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:31:21:31:26:@W::@XP_MSG">ulit.v(31)</a><!@TM:1223827012> | Input port bit <31> of ins_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:31:21:31:26:@W::@XP_MSG">ulit.v(31)</a><!@TM:1223827012> | Input port bit <30> of ins_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:31:21:31:26:@W::@XP_MSG">ulit.v(31)</a><!@TM:1223827012> | Input port bit <29> of ins_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:31:21:31:26:@W::@XP_MSG">ulit.v(31)</a><!@TM:1223827012> | Input port bit <28> of ins_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:31:21:31:26:@W::@XP_MSG">ulit.v(31)</a><!@TM:1223827012> | Input port bit <27> of ins_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:31:21:31:26:@W::@XP_MSG">ulit.v(31)</a><!@TM:1223827012> | Input port bit <26> of ins_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:31:21:31:26:@W::@XP_MSG">ulit.v(31)</a><!@TM:1223827012> | Input port bit <10> of ins_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:31:21:31:26:@W::@XP_MSG">ulit.v(31)</a><!@TM:1223827012> | Input port bit <9> of ins_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:31:21:31:26:@W::@XP_MSG">ulit.v(31)</a><!@TM:1223827012> | Input port bit <8> of ins_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:31:21:31:26:@W::@XP_MSG">ulit.v(31)</a><!@TM:1223827012> | Input port bit <7> of ins_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:31:21:31:26:@W::@XP_MSG">ulit.v(31)</a><!@TM:1223827012> | Input port bit <6> of ins_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:31:21:31:26:@W::@XP_MSG">ulit.v(31)</a><!@TM:1223827012> | Input port bit <5> of ins_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:31:21:31:26:@W::@XP_MSG">ulit.v(31)</a><!@TM:1223827012> | Input port bit <4> of ins_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:31:21:31:26:@W::@XP_MSG">ulit.v(31)</a><!@TM:1223827012> | Input port bit <3> of ins_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:31:21:31:26:@W::@XP_MSG">ulit.v(31)</a><!@TM:1223827012> | Input port bit <2> of ins_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:31:21:31:26:@W::@XP_MSG">ulit.v(31)</a><!@TM:1223827012> | Input port bit <1> of ins_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:31:21:31:26:@W::@XP_MSG">ulit.v(31)</a><!@TM:1223827012> | Input port bit <0> of ins_i[31:0] is unused</font>
@N: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:64:7:64:13:@N::@XP_MSG">ulit.v(64)</a><!@TM:1223827012> | Synthesizing module rd_sel
@N: : <a href="e:\mips789\mips789\rtl\verilog\rf_components.v:89:7:89:16:@N::@XP_MSG">rf_components.v(89)</a><!@TM:1223827012> | Synthesizing module reg_array
@N:<a href="@N:CL134:@XP_HELP">CL134</a> : <a href="e:\mips789\mips789\rtl\verilog\rf_components.v:139:4:139:10:@N:CL134:@XP_MSG">rf_components.v(139)</a><!@TM:1223827012> | Found RAM reg_bank, depth=32, width=32
@N:<a href="@N:CL134:@XP_HELP">CL134</a> : <a href="e:\mips789\mips789\rtl\verilog\rf_components.v:139:4:139:10:@N:CL134:@XP_MSG">rf_components.v(139)</a><!@TM:1223827012> | Found RAM reg_bank, depth=32, width=32
@N: : <a href="e:\mips789\mips789\rtl\verilog\forward.v:25:7:25:14:@N::@XP_MSG">forward.v(25)</a><!@TM:1223827012> | Synthesizing module fwd_mux
@N: : <a href="e:\mips789\mips789\rtl\verilog\rf_stage.v:3:7:3:15:@N::@XP_MSG">rf_stage.v(3)</a><!@TM:1223827012> | Synthesizing module rf_stage
<font color=#A52A2A>@W:<a href="@W:CS149:@XP_HELP">CS149</a> : <a href="e:\mips789\mips789\rtl\verilog\rf_stage.v:91:24:91:30:@W:CS149:@XP_MSG">rf_stage.v(91)</a><!@TM:1223827012> | Port width mismatch for port ins_no. Formal has width 101, Actual 1</font>
<font color=#A52A2A>@W:<a href="@W:CS149:@XP_HELP">CS149</a> : <a href="e:\mips789\mips789\rtl\verilog\rf_stage.v:90:24:90:30:@W:CS149:@XP_MSG">rf_stage.v(90)</a><!@TM:1223827012> | Port width mismatch for port clk_no. Formal has width 101, Actual 1</font>
<font color=#A52A2A>@W:<a href="@W:CL168:@XP_HELP">CL168</a> : <a href="e:\mips789\mips789\rtl\verilog\rf_stage.v:87:12:87:19:@W:CL168:@XP_MSG">rf_stage.v(87)</a><!@TM:1223827012> | Pruning instance CAL_CPI - not in use ...</font>
@N: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:512:7:512:16:@N::@XP_MSG">exec_stage.v(512)</a><!@TM:1223827012> | Synthesizing module muldiv_ff
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:563:4:563:10:@W:CL169:@XP_MSG">exec_stage.v(563)</a><!@TM:1223827012> | Pruning Register LAST_CYCLE_DEAL_SECTION.eqop2 </font>
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:563:4:563:10:@W:CL169:@XP_MSG">exec_stage.v(563)</a><!@TM:1223827012> | Pruning Register LAST_CYCLE_DEAL_SECTION.eqnop2 </font>
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:563:4:563:10:@W:CL169:@XP_MSG">exec_stage.v(563)</a><!@TM:1223827012> | Pruning Register LAST_CYCLE_DEAL_SECTION.LAST_CYCLE_DEAL_SECTION_DEFAULT.op1s_eq_op2s </font>
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:563:4:563:10:@W:CL169:@XP_MSG">exec_stage.v(563)</a><!@TM:1223827012> | Pruning Register START_SECTION.over[32:0] </font>
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:563:4:563:10:@W:CL169:@XP_MSG">exec_stage.v(563)</a><!@TM:1223827012> | Pruning Register LAST_CYCLE_DEAL_SECTION.LAST_CYCLE_DEAL_SECTION_DEFAULT.op1s_eq_h64 </font>
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:563:4:563:10:@W:CL169:@XP_MSG">exec_stage.v(563)</a><!@TM:1223827012> | Pruning Register LAST_CYCLE_DEAL_SECTION.eqz </font>
@N: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:227:7:227:10:@N::@XP_MSG">exec_stage.v(227)</a><!@TM:1223827012> | Synthesizing module alu
@N: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:259:4:259:15:@N::@XP_MSG">exec_stage.v(259)</a><!@TM:1223827012> | Synthesizing module shifter_tak
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:263:25:263:51:@W::@XP_MSG">exec_stage.v(263)</a><!@TM:1223827012> | Input port bit <31> of shift_amount[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:263:25:263:51:@W::@XP_MSG">exec_stage.v(263)</a><!@TM:1223827012> | Input port bit <30> of shift_amount[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:263:25:263:51:@W::@XP_MSG">exec_stage.v(263)</a><!@TM:1223827012> | Input port bit <29> of shift_amount[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:263:25:263:51:@W::@XP_MSG">exec_stage.v(263)</a><!@TM:1223827012> | Input port bit <28> of shift_amount[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:263:25:263:51:@W::@XP_MSG">exec_stage.v(263)</a><!@TM:1223827012> | Input port bit <27> of shift_amount[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:263:25:263:51:@W::@XP_MSG">exec_stage.v(263)</a><!@TM:1223827012> | Input port bit <26> of shift_amount[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:263:25:263:51:@W::@XP_MSG">exec_stage.v(263)</a><!@TM:1223827012> | Input port bit <25> of shift_amount[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:263:25:263:51:@W::@XP_MSG">exec_stage.v(263)</a><!@TM:1223827012> | Input port bit <24> of shift_amount[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:263:25:263:51:@W::@XP_MSG">exec_stage.v(263)</a><!@TM:1223827012> | Input port bit <23> of shift_amount[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:263:25:263:51:@W::@XP_MSG">exec_stage.v(263)</a><!@TM:1223827012> | Input port bit <22> of shift_amount[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:263:25:263:51:@W::@XP_MSG">exec_stage.v(263)</a><!@TM:1223827012> | Input port bit <21> of shift_amount[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:263:25:263:51:@W::@XP_MSG">exec_stage.v(263)</a><!@TM:1223827012> | Input port bit <20> of shift_amount[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:263:25:263:51:@W::@XP_MSG">exec_stage.v(263)</a><!@TM:1223827012> | Input port bit <19> of shift_amount[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:263:25:263:51:@W::@XP_MSG">exec_stage.v(263)</a><!@TM:1223827012> | Input port bit <18> of shift_amount[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:263:25:263:51:@W::@XP_MSG">exec_stage.v(263)</a><!@TM:1223827012> | Input port bit <17> of shift_amount[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:263:25:263:51:@W::@XP_MSG">exec_stage.v(263)</a><!@TM:1223827012> | Input port bit <16> of shift_amount[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:263:25:263:51:@W::@XP_MSG">exec_stage.v(263)</a><!@TM:1223827012> | Input port bit <15> of shift_amount[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:263:25:263:51:@W::@XP_MSG">exec_stage.v(263)</a><!@TM:1223827012> | Input port bit <14> of shift_amount[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:263:25:263:51:@W::@XP_MSG">exec_stage.v(263)</a><!@TM:1223827012> | Input port bit <13> of shift_amount[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:263:25:263:51:@W::@XP_MSG">exec_stage.v(263)</a><!@TM:1223827012> | Input port bit <12> of shift_amount[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:263:25:263:51:@W::@XP_MSG">exec_stage.v(263)</a><!@TM:1223827012> | Input port bit <11> of shift_amount[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:263:25:263:51:@W::@XP_MSG">exec_stage.v(263)</a><!@TM:1223827012> | Input port bit <10> of shift_amount[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:263:25:263:51:@W::@XP_MSG">exec_stage.v(263)</a><!@TM:1223827012> | Input port bit <9> of shift_amount[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:263:25:263:51:@W::@XP_MSG">exec_stage.v(263)</a><!@TM:1223827012> | Input port bit <8> of shift_amount[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:263:25:263:51:@W::@XP_MSG">exec_stage.v(263)</a><!@TM:1223827012> | Input port bit <7> of shift_amount[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:263:25:263:51:@W::@XP_MSG">exec_stage.v(263)</a><!@TM:1223827012> | Input port bit <6> of shift_amount[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:263:25:263:51:@W::@XP_MSG">exec_stage.v(263)</a><!@TM:1223827012> | Input port bit <5> of shift_amount[31:0] is unused</font>
@N: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:132:7:132:14:@N::@XP_MSG">exec_stage.v(132)</a><!@TM:1223827012> | Synthesizing module big_alu
@N: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:22:7:22:12:@N::@XP_MSG">ulit.v(22)</a><!@TM:1223827012> | Synthesizing module add32
@N: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:182:7:182:15:@N::@XP_MSG">exec_stage.v(182)</a><!@TM:1223827012> | Synthesizing module alu_muxa
@N: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:206:7:206:15:@N::@XP_MSG">exec_stage.v(206)</a><!@TM:1223827012> | Synthesizing module alu_muxb
@N: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:149:7:149:14:@N::@XP_MSG">ulit.v(149)</a><!@TM:1223827012> | Synthesizing module r32_reg
@N: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:172:7:172:18:@N::@XP_MSG">ulit.v(172)</a><!@TM:1223827012> | Synthesizing module r32_reg_cls
@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:172:132:172:137:@N:CG179:@XP_MSG">ulit.v(172)</a><!@TM:1223827012> | Removing redundant assignment
@N: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:3:7:3:17:@N::@XP_MSG">exec_stage.v(3)</a><!@TM:1223827012> | Synthesizing module exec_stage
@N: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:54:7:54:11:@N::@XP_MSG">ulit.v(54)</a><!@TM:1223827012> | Synthesizing module or32
@N: : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:2:7:2:14:@N::@XP_MSG">decode_pipe.v(2)</a><!@TM:1223827012> | Synthesizing module decoder
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:CL118:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Latch generated from always block for signal alu_func[4:0], probably caused by a missing assignment in an if or case stmt</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:CL118:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Latch generated from always block for signal pc_gen_ctl[2:0], probably caused by a missing assignment in an if or case stmt</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:CL118:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Latch generated from always block for signal fsm_dly[2:0], probably caused by a missing assignment in an if or case stmt</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:CL118:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Latch generated from always block for signal ext_ctl[2:0], probably caused by a missing assignment in an if or case stmt</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:CL118:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Latch generated from always block for signal rd_sel[1:0], probably caused by a missing assignment in an if or case stmt</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:CL118:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Latch generated from always block for signal muxb_ctl[1:0], probably caused by a missing assignment in an if or case stmt</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:CL118:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Latch generated from always block for signal muxa_ctl[1:0], probably caused by a missing assignment in an if or case stmt</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:CL118:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Latch generated from always block for signal alu_we[0], probably caused by a missing assignment in an if or case stmt</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:CL118:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Latch generated from always block for signal dmem_ctl[3:0], probably caused by a missing assignment in an if or case stmt</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:CL118:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Latch generated from always block for signal cmp_ctl[2:0], probably caused by a missing assignment in an if or case stmt</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:CL118:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Latch generated from always block for signal wb_we[0], probably caused by a missing assignment in an if or case stmt</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:CL118:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Latch generated from always block for signal wb_mux[0], probably caused by a missing assignment in an if or case stmt</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:3:20:3:25:@W::@XP_MSG">decode_pipe.v(3)</a><!@TM:1223827012> | Input port bit <15> of ins_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:3:20:3:25:@W::@XP_MSG">decode_pipe.v(3)</a><!@TM:1223827012> | Input port bit <14> of ins_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:3:20:3:25:@W::@XP_MSG">decode_pipe.v(3)</a><!@TM:1223827012> | Input port bit <13> of ins_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:3:20:3:25:@W::@XP_MSG">decode_pipe.v(3)</a><!@TM:1223827012> | Input port bit <12> of ins_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:3:20:3:25:@W::@XP_MSG">decode_pipe.v(3)</a><!@TM:1223827012> | Input port bit <11> of ins_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:3:20:3:25:@W::@XP_MSG">decode_pipe.v(3)</a><!@TM:1223827012> | Input port bit <10> of ins_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:3:20:3:25:@W::@XP_MSG">decode_pipe.v(3)</a><!@TM:1223827012> | Input port bit <9> of ins_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:3:20:3:25:@W::@XP_MSG">decode_pipe.v(3)</a><!@TM:1223827012> | Input port bit <8> of ins_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:3:20:3:25:@W::@XP_MSG">decode_pipe.v(3)</a><!@TM:1223827012> | Input port bit <7> of ins_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:3:20:3:25:@W::@XP_MSG">decode_pipe.v(3)</a><!@TM:1223827012> | Input port bit <6> of ins_i[31:0] is unused</font>
@N: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:89:7:89:27:@N::@XP_MSG">ulit.v(89)</a><!@TM:1223827012> | Synthesizing module muxb_ctl_reg_clr_cls
@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:89:202:89:212:@N:CG179:@XP_MSG">ulit.v(89)</a><!@TM:1223827012> | Removing redundant assignment
@N: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:93:7:93:29:@N::@XP_MSG">ulit.v(93)</a><!@TM:1223827012> | Synthesizing module wb_mux_ctl_reg_clr_cls
@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:93:216:93:228:@N:CG179:@XP_MSG">ulit.v(93)</a><!@TM:1223827012> | Removing redundant assignment
@N: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:94:7:94:24:@N::@XP_MSG">ulit.v(94)</a><!@TM:1223827012> | Synthesizing module wb_we_reg_clr_cls
@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:94:181:94:188:@N:CG179:@XP_MSG">ulit.v(94)</a><!@TM:1223827012> | Removing redundant assignment
@N: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:140:7:140:16:@N::@XP_MSG">ulit.v(140)</a><!@TM:1223827012> | Synthesizing module wb_we_reg
@N: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:116:7:116:25:@N::@XP_MSG">ulit.v(116)</a><!@TM:1223827012> | Synthesizing module wb_mux_ctl_reg_clr
@N: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:112:7:112:23:@N::@XP_MSG">ulit.v(112)</a><!@TM:1223827012> | Synthesizing module muxb_ctl_reg_clr
@N: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:115:7:115:23:@N::@XP_MSG">ulit.v(115)</a><!@TM:1223827012> | Synthesizing module dmem_ctl_reg_clr
@N: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:113:7:113:23:@N::@XP_MSG">ulit.v(113)</a><!@TM:1223827012> | Synthesizing module alu_func_reg_clr
@N: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:111:7:111:23:@N::@XP_MSG">ulit.v(111)</a><!@TM:1223827012> | Synthesizing module muxa_ctl_reg_clr
@N: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:139:7:139:21:@N::@XP_MSG">ulit.v(139)</a><!@TM:1223827012> | Synthesizing module wb_mux_ctl_reg
@N: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:117:7:117:20:@N::@XP_MSG">ulit.v(117)</a><!@TM:1223827012> | Synthesizing module wb_we_reg_clr
@N: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:85:7:85:26:@N::@XP_MSG">ulit.v(85)</a><!@TM:1223827012> | Synthesizing module cmp_ctl_reg_clr_cls
@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:85:195:85:204:@N:CG179:@XP_MSG">ulit.v(85)</a><!@TM:1223827012> | Removing redundant assignment
@N: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:114:7:114:21:@N::@XP_MSG">ulit.v(114)</a><!@TM:1223827012> | Synthesizing module alu_we_reg_clr
@N: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:90:7:90:27:@N::@XP_MSG">ulit.v(90)</a><!@TM:1223827012> | Synthesizing module alu_func_reg_clr_cls
@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:90:202:90:212:@N:CG179:@XP_MSG">ulit.v(90)</a><!@TM:1223827012> | Removing redundant assignment
@N: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:92:7:92:27:@N::@XP_MSG">ulit.v(92)</a><!@TM:1223827012> | Synthesizing module dmem_ctl_reg_clr_cls
@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:92:202:92:212:@N:CG179:@XP_MSG">ulit.v(92)</a><!@TM:1223827012> | Removing redundant assignment
@N: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:83:7:83:26:@N::@XP_MSG">ulit.v(83)</a><!@TM:1223827012> | Synthesizing module ext_ctl_reg_clr_cls
@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:83:195:83:204:@N:CG179:@XP_MSG">ulit.v(83)</a><!@TM:1223827012> | Removing redundant assignment
@N: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:84:7:84:25:@N::@XP_MSG">ulit.v(84)</a><!@TM:1223827012> | Synthesizing module rd_sel_reg_clr_cls
@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:84:188:84:196:@N:CG179:@XP_MSG">ulit.v(84)</a><!@TM:1223827012> | Removing redundant assignment
@N: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:91:7:91:25:@N::@XP_MSG">ulit.v(91)</a><!@TM:1223827012> | Synthesizing module alu_we_reg_clr_cls
@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:91:188:91:196:@N:CG179:@XP_MSG">ulit.v(91)</a><!@TM:1223827012> | Removing redundant assignment
@N: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:88:7:88:27:@N::@XP_MSG">ulit.v(88)</a><!@TM:1223827012> | Synthesizing module muxa_ctl_reg_clr_cls
@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:88:202:88:212:@N:CG179:@XP_MSG">ulit.v(88)</a><!@TM:1223827012> | Removing redundant assignment
@N: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:86:7:86:29:@N::@XP_MSG">ulit.v(86)</a><!@TM:1223827012> | Synthesizing module pc_gen_ctl_reg_clr_cls
@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:86:216:86:228:@N:CG179:@XP_MSG">ulit.v(86)</a><!@TM:1223827012> | Removing redundant assignment
@N: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:138:7:138:19:@N::@XP_MSG">ulit.v(138)</a><!@TM:1223827012> | Synthesizing module dmem_ctl_reg
@N: : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:1090:7:1090:20:@N::@XP_MSG">decode_pipe.v(1090)</a><!@TM:1223827012> | Synthesizing module pipelinedregs
@N: : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:1419:7:1419:18:@N::@XP_MSG">decode_pipe.v(1419)</a><!@TM:1223827012> | Synthesizing module decode_pipe
@N: : <a href="e:\mips789\mips789\rtl\verilog\forward.v:12:7:12:19:@N::@XP_MSG">forward.v(12)</a><!@TM:1223827012> | Synthesizing module forward_node
@N: : <a href="e:\mips789\mips789\rtl\verilog\forward.v:4:7:4:16:@N::@XP_MSG">forward.v(4)</a><!@TM:1223827012> | Synthesizing module fw_latch5
@N: : <a href="e:\mips789\mips789\rtl\verilog\forward.v:41:7:41:14:@N::@XP_MSG">forward.v(41)</a><!@TM:1223827012> | Synthesizing module forward
@N: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:148:7:148:13:@N::@XP_MSG">ulit.v(148)</a><!@TM:1223827012> | Synthesizing module r5_reg
@N: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:43:7:43:13:@N::@XP_MSG">ulit.v(43)</a><!@TM:1223827012> | Synthesizing module wb_mux
@N: : <a href="e:\mips789\mips789\rtl\verilog\mips_core.v:3:7:3:16:@N::@XP_MSG">mips_core.v(3)</a><!@TM:1223827012> | Synthesizing module mips_core
@N: : <a href="e:\mips789\mips789\rtl\verilog\mips_uart.v:210:7:210:16:@N::@XP_MSG">mips_uart.v(210)</a><!@TM:1223827012> | Synthesizing module uart_read
@N:<a href="@N:CL201:@XP_HELP">CL201</a> : <a href="e:\mips789\mips789\rtl\verilog\mips_uart.v:274:4:274:10:@N:CL201:@XP_MSG">mips_uart.v(274)</a><!@TM:1223827012> | Trying to extract state machine for register ua_state
Extracted state machine for register ua_state
State machine has 5 reachable states with original encodings of:
000
001
010
011
100
@N: : <a href="e:\mips789\mips789\rtl\verilog\mips_uart.v:3:7:3:12:@N::@XP_MSG">mips_uart.v(3)</a><!@TM:1223827012> | Synthesizing module rxd_d
@N: : <a href="c:\program files\synplicity\fpga_81\lib\altera\altera_mf.v:3709:7:3709:13:@N::@XP_MSG">altera_mf.v(3709)</a><!@TM:1223827012> | Synthesizing module scfifo
lpm_width=32'b00000000000000000000000000001000
lpm_widthu=32'b00000000000000000000000000001001
lpm_numwords=32'b00000000000000000000001000000000
lpm_showahead=24'b010011110100011001000110
intended_device_family=56'b01000011011110010110001101101100011011110110111001100101
almost_full_value=32'b00000000000000000000000000000000
almost_empty_value=32'b00000000000000000000000000000000
underflow_checking=16'b0100111101001110
overflow_checking=16'b0100111101001110
allow_rwcycle_when_full=24'b010011110100011001000110
lpm_hint=152'b01010010010000010100110101011111010000100100110001001111010000110100101101011111010101000101100101010000010001010011110101000001010101010101010001001111
use_eab=16'b0100111101001110
add_ram_output_register=24'b010011110100011001000110
maximum_depth=32'b00000000000000000000000000000000
lpm_type=48'b011100110110001101100110011010010110011001101111
Generated name = scfifo_Z1
@N: : <a href="e:\mips789\mips789\rtl\verilog\altera\fifo512_cyclone.v:42:7:42:22:@N::@XP_MSG">fifo512_cyclone.v(42)</a><!@TM:1223827012> | Synthesizing module fifo512_cyclone
@N: : <a href="e:\mips789\mips789\rtl\verilog\mips_uart.v:70:7:70:17:@N::@XP_MSG">mips_uart.v(70)</a><!@TM:1223827012> | Synthesizing module uart_write
<font color=#A52A2A>@W:<a href="@W:CG133:@XP_HELP">CG133</a> : <a href="e:\mips789\mips789\rtl\verilog\mips_uart.v:94:9:94:21:@W:CG133:@XP_MSG">mips_uart.v(94)</a><!@TM:1223827012> | No assignment to write_done_n</font>
@N:<a href="@N:CL201:@XP_HELP">CL201</a> : <a href="e:\mips789\mips789\rtl\verilog\mips_uart.v:168:4:168:10:@N:CL201:@XP_MSG">mips_uart.v(168)</a><!@TM:1223827012> | Trying to extract state machine for register ua_state
Extracted state machine for register ua_state
State machine has 8 reachable states with original encodings of:
000
001
010
011
100
101
110
111
@N: : <a href="e:\mips789\mips789\rtl\verilog\mips_uart.v:12:7:12:12:@N::@XP_MSG">mips_uart.v(12)</a><!@TM:1223827012> | Synthesizing module uart0
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mips_uart.v:38:9:38:18:@W::@XP_MSG">mips_uart.v(38)</a><!@TM:1223827012> | No assignment to wire w_rxd_clr</font>
@N: : <a href="e:\mips789\mips789\rtl\verilog\dvc.v:52:7:52:17:@N::@XP_MSG">dvc.v(52)</a><!@TM:1223827012> | Synthesizing module seg7led_cv
@N: : <a href="e:\mips789\mips789\rtl\verilog\dvc.v:43:7:43:12:@N::@XP_MSG">dvc.v(43)</a><!@TM:1223827012> | Synthesizing module tmr_d
@N: : <a href="e:\mips789\mips789\rtl\verilog\dvc.v:3:7:3:11:@N::@XP_MSG">dvc.v(3)</a><!@TM:1223827012> | Synthesizing module tmr0
@N: : <a href="e:\mips789\mips789\rtl\verilog\mips_dvc.v:3:7:3:15:@N::@XP_MSG">mips_dvc.v(3)</a><!@TM:1223827012> | Synthesizing module mips_dvc
@N: : <a href="e:\mips789\mips789\rtl\verilog\mips_sys.v:4:7:4:15:@N::@XP_MSG">mips_sys.v(4)</a><!@TM:1223827012> | Synthesizing module mips_sys
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mips_sys.v:78:16:78:25:@W::@XP_MSG">mips_sys.v(78)</a><!@TM:1223827012> | No assignment to wire data2core</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mips_sys.v:79:16:79:24:@W::@XP_MSG">mips_sys.v(79)</a><!@TM:1223827012> | No assignment to wire data2mem</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mips_sys.v:80:16:80:24:@W::@XP_MSG">mips_sys.v(80)</a><!@TM:1223827012> | No assignment to wire ins2core</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mips_sys.v:81:16:81:24:@W::@XP_MSG">mips_sys.v(81)</a><!@TM:1223827012> | No assignment to wire mem_Addr</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mips_sys.v:82:16:82:18:@W::@XP_MSG">mips_sys.v(82)</a><!@TM:1223827012> | No assignment to wire pc</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mips_sys.v:83:15:83:20:@W::@XP_MSG">mips_sys.v(83)</a><!@TM:1223827012> | No assignment to wire wr_en</font>
@END
Process took 0h:00m:11s realtime, 0h:00m:11s cputime
# Sun Oct 12 23:56:51 2008
###########################################################[
Version 8.1
<a name=mapperReport17>Synplicity Altera Technology Mapper, Version 8.1.0, Build 539R, Built May 6 2005
Copyright (C) 1994-2005, Synplicity Inc. All Rights Reserved
Reading constraint file: E:\mips789\mips789\synplify_prj\rev_1\mips_sys_fsm.sdc
Automatic dissolve at startup in view:work.mem_module(verilog) of i_mem_din_ctl(mem_din_ctl)
Automatic dissolve at startup in view:work.mem_module(verilog) of i_mem_addr_ctl(mem_addr_ctl)
Automatic dissolve at startup in view:work.mem_module(verilog) of dmem_ctl_post(infile_dmem_ctl_reg)
Automatic dissolve at startup in view:work.rf_stage(verilog) of rs_fwd_rs(fwd_mux)
Automatic dissolve at startup in view:work.rf_stage(verilog) of rf_fwd_rt(fwd_mux)
Automatic dissolve at startup in view:work.rf_stage(verilog) of jack2(jack)
Automatic dissolve at startup in view:work.rf_stage(verilog) of jack1(jack)
Automatic dissolve at startup in view:work.rf_stage(verilog) of ins_reg(r32_reg_clr_cls)
Automatic dissolve at startup in view:work.rf_stage(verilog) of i_pc_gen(pc_gen)
Automatic dissolve at startup in view:work.exec_stage(verilog) of spc(r32_reg_cls)
Automatic dissolve at startup in view:work.exec_stage(verilog) of pc_nxt(r32_reg)
Automatic dissolve at startup in view:work.exec_stage(verilog) of i_alu_muxb(alu_muxb)
Automatic dissolve at startup in view:work.exec_stage(verilog) of i_alu_muxa(alu_muxa)
Automatic dissolve at startup in view:work.exec_stage(verilog) of dmem_fw_mux(fwd_mux)
Automatic dissolve at startup in view:work.exec_stage(verilog) of add4(add32)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U9(dmem_ctl_reg)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U8(pc_gen_ctl_reg_clr_cls)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U7(muxa_ctl_reg_clr_cls)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U6(alu_we_reg_clr_cls)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U5(rd_sel_reg_clr_cls)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U4(ext_ctl_reg_clr_cls)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U3(dmem_ctl_reg_clr_cls)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U26(alu_func_reg_clr_cls)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U24(alu_we_reg_clr)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U22(wb_we_reg)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U21(wb_mux_ctl_reg)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U20(wb_we_reg)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U2(cmp_ctl_reg_clr_cls)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U19(wb_we_reg_clr)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U18(wb_mux_ctl_reg)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U17(muxa_ctl_reg_clr)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U16(alu_func_reg_clr)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U15(dmem_ctl_reg_clr)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U14(muxb_ctl_reg_clr)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U13(wb_mux_ctl_reg_clr)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U12(wb_we_reg)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U11(wb_we_reg_clr_cls)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U10(wb_mux_ctl_reg_clr_cls)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U1(muxb_ctl_reg_clr_cls)
Automatic dissolve at startup in view:work.decode_pipe(verilog) of pipereg(pipelinedregs)
Automatic dissolve at startup in view:work.forward(verilog) of fw_reg_rnt(fw_latch5)
Automatic dissolve at startup in view:work.forward(verilog) of fw_reg_rns(fw_latch5)
Automatic dissolve at startup in view:work.mips_core(verilog) of wb_mux(wb_mux)
Automatic dissolve at startup in view:work.mips_core(verilog) of rt_reg(r32_reg)
Automatic dissolve at startup in view:work.mips_core(verilog) of rs_reg(r32_reg)
Automatic dissolve at startup in view:work.mips_core(verilog) of rnd_pass2(r5_reg)
Automatic dissolve at startup in view:work.mips_core(verilog) of rnd_pass1(r5_reg)
Automatic dissolve at startup in view:work.mips_core(verilog) of rnd_pass0(r5_reg)
Automatic dissolve at startup in view:work.mips_core(verilog) of pc(r32_reg)
Automatic dissolve at startup in view:work.mips_core(verilog) of ext_reg(r32_reg)
Automatic dissolve at startup in view:work.mips_core(verilog) of cop_dout_reg(r32_reg)
Automatic dissolve at startup in view:work.mips_core(verilog) of cop_data_reg(r32_reg)
Automatic dissolve at startup in view:work.mips_core(verilog) of cop_data_or(or32)
Automatic dissolve at startup in view:work.mips_core(verilog) of alu_pass1(r32_reg)
Automatic dissolve at startup in view:work.mips_core(verilog) of alu_pass0(r32_reg)
Automatic dissolve at startup in view:work.mips_core(verilog) of iexec_stage(exec_stage)
Automatic dissolve at startup in view:work.mips_core(verilog) of iRF_stage(rf_stage)
Automatic dissolve at startup in view:work.mips_core(verilog) of MEM_CTL(mem_module)
Automatic dissolve at startup in view:work.uart_write(verilog) of fifo(fifo512_cyclone)
Automatic dissolve at startup in view:work.uart0(verilog) of rxd_rdy_hold_lw(rxd_d)
Automatic dissolve at startup in view:work.tmr0(verilog) of itmr_d(tmr_d)
Warning: Found 30 combinational loops!
Each loop is reported with an instance in the loop
and nets connected to that instance.
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net fsm_dly_1[0]</font>
1) instance work.decoder(verilog)-fsm_dly_1[0], output net "fsm_dly_1[0]" in work.decoder(verilog)
input nets to instance:
net "fsm_dly_2[0]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net fsm_dly_1[1]</font>
2) instance work.decoder(verilog)-fsm_dly_1[2:1], output net "fsm_dly_1[1]" in work.decoder(verilog)
input nets to instance:
net "fsm_dly_2[1]" in work.decoder(verilog)
net "fsm_dly_2[2]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net fsm_dly_1[2]</font>
3) instance work.decoder(verilog)-fsm_dly_1[2:1], output net "fsm_dly_1[2]" in work.decoder(verilog)
input nets to instance:
net "fsm_dly_2[1]" in work.decoder(verilog)
net "fsm_dly_2[2]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net ext_ctl_1[0]</font>
4) instance work.decoder(verilog)-ext_ctl_1[0], output net "ext_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "ext_ctl_2[0]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net ext_ctl_1[1]</font>
5) instance work.decoder(verilog)-ext_ctl_1[1], output net "ext_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "ext_ctl_2[1]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net ext_ctl_1[2]</font>
6) instance work.decoder(verilog)-ext_ctl_1[2], output net "ext_ctl_1[2]" in work.decoder(verilog)
input nets to instance:
net "ext_ctl_2[2]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net rd_sel_1[0]</font>
7) instance work.decoder(verilog)-rd_sel_1[0], output net "rd_sel_1[0]" in work.decoder(verilog)
input nets to instance:
net "rd_sel_2[0]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net rd_sel_1[1]</font>
8) instance work.decoder(verilog)-rd_sel_1[1], output net "rd_sel_1[1]" in work.decoder(verilog)
input nets to instance:
net "rd_sel_2[1]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_22" in work.decoder(verilog)
net "muxa_ctl373" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net cmp_ctl_1[0]</font>
9) instance work.decoder(verilog)-cmp_ctl_1[0], output net "cmp_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "cmp_ctl_2[0]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net cmp_ctl_1[1]</font>
10) instance work.decoder(verilog)-cmp_ctl_1[1], output net "cmp_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "cmp_ctl_2[1]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net cmp_ctl_1[2]</font>
11) instance work.decoder(verilog)-cmp_ctl_1[2], output net "cmp_ctl_1[2]" in work.decoder(verilog)
input nets to instance:
net "cmp_ctl_2[2]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net pc_gen_ctl_1[0]</font>
12) instance work.decoder(verilog)-pc_gen_ctl_1[0], output net "pc_gen_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "pc_gen_ctl_2[0]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net pc_gen_ctl_1[1]</font>
13) instance work.decoder(verilog)-pc_gen_ctl_1[1], output net "pc_gen_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "pc_gen_ctl_2[1]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net pc_gen_ctl_1[2]</font>
14) instance work.decoder(verilog)-pc_gen_ctl_1[2], output net "pc_gen_ctl_1[2]" in work.decoder(verilog)
input nets to instance:
net "pc_gen_ctl_2[2]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net muxa_ctl_1[0]</font>
15) instance work.decoder(verilog)-muxa_ctl_1[0], output net "muxa_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "muxa_ctl_2[0]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net muxa_ctl_1[1]</font>
16) instance work.decoder(verilog)-muxa_ctl_1[1], output net "muxa_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "muxa_ctl_2[1]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net muxb_ctl_1[0]</font>
17) instance work.decoder(verilog)-muxb_ctl_1[0], output net "muxb_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "muxb_ctl_2[0]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net muxb_ctl_1[1]</font>
18) instance work.decoder(verilog)-muxb_ctl_1[1], output net "muxb_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "muxb_ctl_2[1]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net alu_func_1[0]</font>
19) instance work.decoder(verilog)-alu_func_1[0], output net "alu_func_1[0]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[0]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net alu_func_1[1]</font>
20) instance work.decoder(verilog)-alu_func_1[1], output net "alu_func_1[1]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[1]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net alu_func_1[2]</font>
21) instance work.decoder(verilog)-alu_func_1[2], output net "alu_func_1[2]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[2]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net alu_func_1[3]</font>
22) instance work.decoder(verilog)-alu_func_1[3], output net "alu_func_1[3]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[3]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net alu_func_1[4]</font>
23) instance work.decoder(verilog)-alu_func_1[4], output net "alu_func_1[4]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[4]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net dmem_ctl_1[0]</font>
24) instance work.decoder(verilog)-dmem_ctl_1[0], output net "dmem_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "dmem_ctl_2[0]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net dmem_ctl_1[1]</font>
25) instance work.decoder(verilog)-dmem_ctl_1[1], output net "dmem_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "dmem_ctl_2[1]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_22" in work.decoder(verilog)
net "muxa_ctl373" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net dmem_ctl_1[2]</font>
26) instance work.decoder(verilog)-dmem_ctl_1[2], output net "dmem_ctl_1[2]" in work.decoder(verilog)
input nets to instance:
net "dmem_ctl_2[2]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_24" in work.decoder(verilog)
net "un1_ins_i_15" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net dmem_ctl_1[3]</font>
27) instance work.decoder(verilog)-dmem_ctl_1[3], output net "dmem_ctl_1[3]" in work.decoder(verilog)
input nets to instance:
net "dmem_ctl_2[3]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net alu_we[0]</font>
28) instance work.decoder(verilog)-alu_we[0], output net "alu_we[0]" in work.decoder(verilog)
input nets to instance:
net "alu_we_1[0]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net wb_mux[0]</font>
29) instance work.decoder(verilog)-wb_mux[0], output net "wb_mux[0]" in work.decoder(verilog)
input nets to instance:
net "wb_mux_1[0]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net wb_we[0]</font>
30) instance work.decoder(verilog)-wb_we[0], output net "wb_we[0]" in work.decoder(verilog)
input nets to instance:
net "wb_we_1[0]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
End of loops
RTL optimization done.
Warning: Found 30 combinational loops!
Each loop is reported with an instance in the loop
and nets connected to that instance.
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net fsm_dly_1[0]</font>
1) instance work.decoder(verilog)-fsm_dly_1[0], output net "fsm_dly_1[0]" in work.decoder(verilog)
input nets to instance:
net "fsm_dly_2[0]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net fsm_dly_1[1]</font>
2) instance work.decoder(verilog)-fsm_dly_1[2:1], output net "fsm_dly_1[1]" in work.decoder(verilog)
input nets to instance:
net "fsm_dly_2[1]" in work.decoder(verilog)
net "fsm_dly_2[2]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net fsm_dly_1[2]</font>
3) instance work.decoder(verilog)-fsm_dly_1[2:1], output net "fsm_dly_1[2]" in work.decoder(verilog)
input nets to instance:
net "fsm_dly_2[1]" in work.decoder(verilog)
net "fsm_dly_2[2]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net wb_mux_1[0]</font>
4) instance work.decoder(verilog)-wb_mux_1[0], output net "wb_mux_1[0]" in work.decoder(verilog)
input nets to instance:
net "un1_alu_we_3_sqmuxa_4" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "un1_alu_we_3_sqmuxa" in work.decoder(verilog)
net "wb_mux[0]" in work.decoder(verilog)
net "un1_muxa_ctl365" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net wb_we_1[0]</font>
5) instance work.decoder(verilog)-wb_we_1[0], output net "wb_we_1[0]" in work.decoder(verilog)
input nets to instance:
net "un1_alu_we_3_sqmuxa_3" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "un1_alu_we_3_sqmuxa" in work.decoder(verilog)
net "wb_we[0]" in work.decoder(verilog)
net "un1_muxa_ctl362" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net alu_func_2[0]</font>
6) instance work.decoder(verilog)-alu_func_2[4:0], output net "alu_func_2[0]" in work.decoder(verilog)
input nets to instance:
net "alu_func_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_1_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_3_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_4_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_5_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_6_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_7_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_8_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_9_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_10_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_11_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_12_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_13_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_14_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_15_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_16_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_17_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_18_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_19_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_20_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_21_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_22_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_23_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_24_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_25_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_26_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_27_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_28_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_3_sqmuxa" in work.decoder(verilog)
net "alu_func_1[0]" in work.decoder(verilog)
net "alu_func_1[1]" in work.decoder(verilog)
net "alu_func_1[2]" in work.decoder(verilog)
net "alu_func_1[3]" in work.decoder(verilog)
net "alu_func_1[4]" in work.decoder(verilog)
net "alu_we_4_sqmuxa" in work.decoder(verilog)
net "alu_func_1[0]" in work.decoder(verilog)
net "alu_func_1[1]" in work.decoder(verilog)
net "alu_func_1[2]" in work.decoder(verilog)
net "alu_func_1[3]" in work.decoder(verilog)
net "alu_func_1[4]" in work.decoder(verilog)
net "muxa_ctl350" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl351" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl352" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl353" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl354" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl355" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl356" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl357" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl358" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl359" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl360" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl361" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl362" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl363" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
net "alu_func_1[0]" in work.decoder(verilog)
net "alu_func_1[1]" in work.decoder(verilog)
net "alu_func_1[2]" in work.decoder(verilog)
net "alu_func_1[3]" in work.decoder(verilog)
net "alu_func_1[4]" in work.decoder(verilog)
net "muxa_ctl365" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl366" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl367" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl368" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl369" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl370" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net alu_func_2[1]</font>
7) instance work.decoder(verilog)-alu_func_2[4:0], output net "alu_func_2[1]" in work.decoder(verilog)
input nets to instance:
net "alu_func_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_1_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_3_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_4_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_5_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_6_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_7_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_8_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_9_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_10_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_11_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_12_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_13_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_14_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_15_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_16_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_17_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_18_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_19_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_20_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_21_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_22_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_23_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_24_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_25_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_26_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_27_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_28_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_3_sqmuxa" in work.decoder(verilog)
net "alu_func_1[0]" in work.decoder(verilog)
net "alu_func_1[1]" in work.decoder(verilog)
net "alu_func_1[2]" in work.decoder(verilog)
net "alu_func_1[3]" in work.decoder(verilog)
net "alu_func_1[4]" in work.decoder(verilog)
net "alu_we_4_sqmuxa" in work.decoder(verilog)
net "alu_func_1[0]" in work.decoder(verilog)
net "alu_func_1[1]" in work.decoder(verilog)
net "alu_func_1[2]" in work.decoder(verilog)
net "alu_func_1[3]" in work.decoder(verilog)
net "alu_func_1[4]" in work.decoder(verilog)
net "muxa_ctl350" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl351" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl352" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl353" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl354" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl355" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl356" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl357" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl358" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl359" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl360" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl361" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl362" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl363" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
net "alu_func_1[0]" in work.decoder(verilog)
net "alu_func_1[1]" in work.decoder(verilog)
net "alu_func_1[2]" in work.decoder(verilog)
net "alu_func_1[3]" in work.decoder(verilog)
net "alu_func_1[4]" in work.decoder(verilog)
net "muxa_ctl365" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl366" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl367" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl368" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl369" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl370" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net alu_func_2[2]</font>
8) instance work.decoder(verilog)-alu_func_2[4:0], output net "alu_func_2[2]" in work.decoder(verilog)
input nets to instance:
net "alu_func_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_1_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_3_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_4_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_5_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_6_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_7_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_8_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_9_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_10_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_11_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_12_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_13_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_14_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_15_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_16_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_17_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_18_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_19_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_20_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_21_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_22_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_23_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_24_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_25_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_26_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_27_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_28_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_3_sqmuxa" in work.decoder(verilog)
net "alu_func_1[0]" in work.decoder(verilog)
net "alu_func_1[1]" in work.decoder(verilog)
net "alu_func_1[2]" in work.decoder(verilog)
net "alu_func_1[3]" in work.decoder(verilog)
net "alu_func_1[4]" in work.decoder(verilog)
net "alu_we_4_sqmuxa" in work.decoder(verilog)
net "alu_func_1[0]" in work.decoder(verilog)
net "alu_func_1[1]" in work.decoder(verilog)
net "alu_func_1[2]" in work.decoder(verilog)
net "alu_func_1[3]" in work.decoder(verilog)
net "alu_func_1[4]" in work.decoder(verilog)
net "muxa_ctl350" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl351" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl352" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl353" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl354" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl355" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl356" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl357" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl358" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl359" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl360" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl361" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl362" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl363" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
net "alu_func_1[0]" in work.decoder(verilog)
net "alu_func_1[1]" in work.decoder(verilog)
net "alu_func_1[2]" in work.decoder(verilog)
net "alu_func_1[3]" in work.decoder(verilog)
net "alu_func_1[4]" in work.decoder(verilog)
net "muxa_ctl365" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl366" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl367" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl368" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl369" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl370" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net alu_func_2[3]</font>
9) instance work.decoder(verilog)-alu_func_2[4:0], output net "alu_func_2[3]" in work.decoder(verilog)
input nets to instance:
net "alu_func_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_1_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_3_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_4_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_5_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_6_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_7_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_8_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_9_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_10_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_11_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_12_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_13_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_14_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_15_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_16_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_17_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_18_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_19_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_20_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_21_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_22_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_23_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_24_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_25_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_26_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_27_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_28_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_3_sqmuxa" in work.decoder(verilog)
net "alu_func_1[0]" in work.decoder(verilog)
net "alu_func_1[1]" in work.decoder(verilog)
net "alu_func_1[2]" in work.decoder(verilog)
net "alu_func_1[3]" in work.decoder(verilog)
net "alu_func_1[4]" in work.decoder(verilog)
net "alu_we_4_sqmuxa" in work.decoder(verilog)
net "alu_func_1[0]" in work.decoder(verilog)
net "alu_func_1[1]" in work.decoder(verilog)
net "alu_func_1[2]" in work.decoder(verilog)
net "alu_func_1[3]" in work.decoder(verilog)
net "alu_func_1[4]" in work.decoder(verilog)
net "muxa_ctl350" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl351" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl352" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl353" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl354" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl355" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl356" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl357" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl358" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl359" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl360" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl361" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl362" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl363" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
net "alu_func_1[0]" in work.decoder(verilog)
net "alu_func_1[1]" in work.decoder(verilog)
net "alu_func_1[2]" in work.decoder(verilog)
net "alu_func_1[3]" in work.decoder(verilog)
net "alu_func_1[4]" in work.decoder(verilog)
net "muxa_ctl365" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl366" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl367" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl368" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl369" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl370" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net alu_func_2[4]</font>
10) instance work.decoder(verilog)-alu_func_2[4:0], output net "alu_func_2[4]" in work.decoder(verilog)
input nets to instance:
net "alu_func_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_1_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_3_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_4_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_5_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_6_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_7_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_8_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_9_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_10_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_11_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_12_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_13_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_14_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_15_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_16_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_17_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_18_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_19_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_20_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_21_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_22_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_23_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_24_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_25_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_26_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_27_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_28_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_3_sqmuxa" in work.decoder(verilog)
net "alu_func_1[0]" in work.decoder(verilog)
net "alu_func_1[1]" in work.decoder(verilog)
net "alu_func_1[2]" in work.decoder(verilog)
net "alu_func_1[3]" in work.decoder(verilog)
net "alu_func_1[4]" in work.decoder(verilog)
net "alu_we_4_sqmuxa" in work.decoder(verilog)
net "alu_func_1[0]" in work.decoder(verilog)
net "alu_func_1[1]" in work.decoder(verilog)
net "alu_func_1[2]" in work.decoder(verilog)
net "alu_func_1[3]" in work.decoder(verilog)
net "alu_func_1[4]" in work.decoder(verilog)
net "muxa_ctl350" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl351" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl352" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl353" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl354" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl355" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl356" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl357" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl358" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl359" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl360" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl361" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl362" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl363" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
net "alu_func_1[0]" in work.decoder(verilog)
net "alu_func_1[1]" in work.decoder(verilog)
net "alu_func_1[2]" in work.decoder(verilog)
net "alu_func_1[3]" in work.decoder(verilog)
net "alu_func_1[4]" in work.decoder(verilog)
net "muxa_ctl365" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl366" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl367" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl368" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl369" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl370" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net alu_we_1[0]</font>
11) instance work.decoder(verilog)-alu_we_1[0], output net "alu_we_1[0]" in work.decoder(verilog)
input nets to instance:
net "alu_func_0_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_1_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_2_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_3_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_4_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_5_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_6_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_7_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_8_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_9_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_10_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_11_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_12_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_13_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_14_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_15_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_16_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_17_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_18_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_19_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_20_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_21_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_22_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_23_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_24_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_25_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_26_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_27_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_28_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_3_sqmuxa" in work.decoder(verilog)
net "alu_we[0]" in work.decoder(verilog)
net "alu_we_4_sqmuxa" in work.decoder(verilog)
net "alu_we[0]" in work.decoder(verilog)
net "muxa_ctl350" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl351" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl352" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl353" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl354" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl355" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl356" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl357" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl358" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl359" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl360" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl361" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl362" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl363" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
net "alu_we[0]" in work.decoder(verilog)
net "muxa_ctl365" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl366" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl367" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl368" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl369" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl370" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net ext_ctl_2[0]</font>
12) instance work.decoder(verilog)-ext_ctl_2[2:0], output net "ext_ctl_2[0]" in work.decoder(verilog)
input nets to instance:
net "alu_func_0_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_1_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_2_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_3_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_4_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_5_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_6_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_7_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_8_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_9_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_10_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_11_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_12_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_13_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_14_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_15_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_16_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_17_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_18_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_19_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_20_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_21_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_22_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_23_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_24_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_25_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_26_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_27_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_28_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_1_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_3_sqmuxa" in work.decoder(verilog)
net "ext_ctl_1[0]" in work.decoder(verilog)
net "ext_ctl_1[1]" in work.decoder(verilog)
net "ext_ctl_1[2]" in work.decoder(verilog)
net "alu_we_4_sqmuxa" in work.decoder(verilog)
net "ext_ctl_1[0]" in work.decoder(verilog)
net "ext_ctl_1[1]" in work.decoder(verilog)
net "ext_ctl_1[2]" in work.decoder(verilog)
net "muxa_ctl350" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl351" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl352" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl353" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl354" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl355" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl356" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl357" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl358" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl359" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl360" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl361" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl362" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl363" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
net "ext_ctl_1[0]" in work.decoder(verilog)
net "ext_ctl_1[1]" in work.decoder(verilog)
net "ext_ctl_1[2]" in work.decoder(verilog)
net "muxa_ctl365" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl366" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl367" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl368" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl369" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl370" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net ext_ctl_2[1]</font>
13) instance work.decoder(verilog)-ext_ctl_2[2:0], output net "ext_ctl_2[1]" in work.decoder(verilog)
input nets to instance:
net "alu_func_0_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_1_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_2_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_3_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_4_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_5_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_6_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_7_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_8_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_9_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_10_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_11_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_12_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_13_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_14_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_15_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_16_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_17_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_18_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_19_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_20_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_21_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_22_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_23_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_24_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_25_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_26_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_27_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_28_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_1_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_3_sqmuxa" in work.decoder(verilog)
net "ext_ctl_1[0]" in work.decoder(verilog)
net "ext_ctl_1[1]" in work.decoder(verilog)
net "ext_ctl_1[2]" in work.decoder(verilog)
net "alu_we_4_sqmuxa" in work.decoder(verilog)
net "ext_ctl_1[0]" in work.decoder(verilog)
net "ext_ctl_1[1]" in work.decoder(verilog)
net "ext_ctl_1[2]" in work.decoder(verilog)
net "muxa_ctl350" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl351" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl352" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl353" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl354" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl355" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl356" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl357" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl358" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl359" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl360" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl361" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl362" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl363" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
net "ext_ctl_1[0]" in work.decoder(verilog)
net "ext_ctl_1[1]" in work.decoder(verilog)
net "ext_ctl_1[2]" in work.decoder(verilog)
net "muxa_ctl365" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl366" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl367" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl368" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl369" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl370" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net ext_ctl_2[2]</font>
14) instance work.decoder(verilog)-ext_ctl_2[2:0], output net "ext_ctl_2[2]" in work.decoder(verilog)
input nets to instance:
net "alu_func_0_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_1_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_2_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_3_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_4_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_5_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_6_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_7_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_8_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_9_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_10_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_11_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_12_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_13_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_14_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_15_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_16_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_17_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_18_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_19_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_20_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_21_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_22_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_23_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_24_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_25_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_26_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_27_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_28_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_1_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_3_sqmuxa" in work.decoder(verilog)
net "ext_ctl_1[0]" in work.decoder(verilog)
net "ext_ctl_1[1]" in work.decoder(verilog)
net "ext_ctl_1[2]" in work.decoder(verilog)
net "alu_we_4_sqmuxa" in work.decoder(verilog)
net "ext_ctl_1[0]" in work.decoder(verilog)
net "ext_ctl_1[1]" in work.decoder(verilog)
net "ext_ctl_1[2]" in work.decoder(verilog)
net "muxa_ctl350" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl351" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl352" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl353" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl354" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl355" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl356" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl357" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl358" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl359" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl360" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl361" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl362" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl363" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
net "ext_ctl_1[0]" in work.decoder(verilog)
net "ext_ctl_1[1]" in work.decoder(verilog)
net "ext_ctl_1[2]" in work.decoder(verilog)
net "muxa_ctl365" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl366" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl367" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl368" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl369" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl370" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net muxa_ctl_2[0]</font>
15) instance work.decoder(verilog)-muxa_ctl_2[1:0], output net "muxa_ctl_2[0]" in work.decoder(verilog)
input nets to instance:
net "alu_func_0_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_1_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_2_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_3_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_4_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_5_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_6_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_7_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_8_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_9_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_10_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_11_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_12_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_13_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_14_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_15_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_16_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_17_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_18_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_19_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_20_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_21_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_22_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_23_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_24_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_25_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_26_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_27_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_28_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_3_sqmuxa" in work.decoder(verilog)
net "muxa_ctl_1[0]" in work.decoder(verilog)
net "muxa_ctl_1[1]" in work.decoder(verilog)
net "alu_we_4_sqmuxa" in work.decoder(verilog)
net "muxa_ctl_1[0]" in work.decoder(verilog)
net "muxa_ctl_1[1]" in work.decoder(verilog)
net "muxa_ctl350" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl351" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl352" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl353" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl354" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl355" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl356" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl357" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl358" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl359" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl360" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl361" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl362" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl363" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
net "muxa_ctl_1[0]" in work.decoder(verilog)
net "muxa_ctl_1[1]" in work.decoder(verilog)
net "muxa_ctl365" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl366" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl367" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl368" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl369" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl370" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net muxa_ctl_2[1]</font>
16) instance work.decoder(verilog)-muxa_ctl_2[1:0], output net "muxa_ctl_2[1]" in work.decoder(verilog)
input nets to instance:
net "alu_func_0_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_1_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_2_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_3_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_4_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_5_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_6_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_7_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_8_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_9_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_10_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_11_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_12_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_13_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_14_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_15_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_16_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_17_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_18_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_19_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_20_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_21_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_22_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_23_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_24_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_25_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_26_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_27_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_28_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_3_sqmuxa" in work.decoder(verilog)
net "muxa_ctl_1[0]" in work.decoder(verilog)
net "muxa_ctl_1[1]" in work.decoder(verilog)
net "alu_we_4_sqmuxa" in work.decoder(verilog)
net "muxa_ctl_1[0]" in work.decoder(verilog)
net "muxa_ctl_1[1]" in work.decoder(verilog)
net "muxa_ctl350" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl351" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl352" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl353" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl354" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl355" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl356" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl357" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl358" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl359" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl360" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl361" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl362" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl363" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
net "muxa_ctl_1[0]" in work.decoder(verilog)
net "muxa_ctl_1[1]" in work.decoder(verilog)
net "muxa_ctl365" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl366" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl367" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl368" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl369" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl370" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net muxb_ctl_2[0]</font>
17) instance work.decoder(verilog)-muxb_ctl_2[1:0], output net "muxb_ctl_2[0]" in work.decoder(verilog)
input nets to instance:
net "alu_func_0_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_1_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_2_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_3_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_4_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_5_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_6_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_7_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_8_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_9_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_10_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_11_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_12_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_13_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_14_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_15_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_16_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_17_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_18_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_19_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_20_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_21_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_22_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_23_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_24_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_25_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_26_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_27_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_28_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_3_sqmuxa" in work.decoder(verilog)
net "muxb_ctl_1[0]" in work.decoder(verilog)
net "muxb_ctl_1[1]" in work.decoder(verilog)
net "alu_we_4_sqmuxa" in work.decoder(verilog)
net "muxb_ctl_1[0]" in work.decoder(verilog)
net "muxb_ctl_1[1]" in work.decoder(verilog)
net "muxa_ctl350" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl351" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl352" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl353" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl354" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl355" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl356" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl357" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl358" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl359" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl360" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl361" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl362" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl363" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
net "muxb_ctl_1[0]" in work.decoder(verilog)
net "muxb_ctl_1[1]" in work.decoder(verilog)
net "muxa_ctl365" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl366" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl367" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl368" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl369" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl370" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net muxb_ctl_2[1]</font>
18) instance work.decoder(verilog)-muxb_ctl_2[1:0], output net "muxb_ctl_2[1]" in work.decoder(verilog)
input nets to instance:
net "alu_func_0_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_1_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_2_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_3_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_4_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_5_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_6_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_7_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_8_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_9_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_10_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_11_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_12_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_13_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_14_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_15_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_16_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_17_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_18_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_19_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_20_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_21_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_22_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_23_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_24_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_25_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_26_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_27_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_28_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_3_sqmuxa" in work.decoder(verilog)
net "muxb_ctl_1[0]" in work.decoder(verilog)
net "muxb_ctl_1[1]" in work.decoder(verilog)
net "alu_we_4_sqmuxa" in work.decoder(verilog)
net "muxb_ctl_1[0]" in work.decoder(verilog)
net "muxb_ctl_1[1]" in work.decoder(verilog)
net "muxa_ctl350" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl351" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl352" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl353" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl354" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl355" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl356" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl357" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl358" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl359" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl360" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl361" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl362" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl363" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
net "muxb_ctl_1[0]" in work.decoder(verilog)
net "muxb_ctl_1[1]" in work.decoder(verilog)
net "muxa_ctl365" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl366" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl367" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl368" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl369" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl370" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net pc_gen_ctl_2[0]</font>
19) instance work.decoder(verilog)-pc_gen_ctl_2[2:0], output net "pc_gen_ctl_2[0]" in work.decoder(verilog)
input nets to instance:
net "alu_func_0_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_1_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_2_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_3_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_4_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_5_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_6_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_7_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_8_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_9_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_10_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_11_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_12_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_13_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_14_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_15_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_16_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_17_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_18_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_19_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_20_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_21_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_22_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_23_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_24_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_25_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_26_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_27_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_28_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_1_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_3_sqmuxa" in work.decoder(verilog)
net "pc_gen_ctl_1[0]" in work.decoder(verilog)
net "pc_gen_ctl_1[1]" in work.decoder(verilog)
net "pc_gen_ctl_1[2]" in work.decoder(verilog)
net "alu_we_4_sqmuxa" in work.decoder(verilog)
net "pc_gen_ctl_1[0]" in work.decoder(verilog)
net "pc_gen_ctl_1[1]" in work.decoder(verilog)
net "pc_gen_ctl_1[2]" in work.decoder(verilog)
net "muxa_ctl350" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl351" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl352" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl353" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl354" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl355" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl356" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl357" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl358" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl359" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl360" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl361" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl362" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl363" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
net "pc_gen_ctl_1[0]" in work.decoder(verilog)
net "pc_gen_ctl_1[1]" in work.decoder(verilog)
net "pc_gen_ctl_1[2]" in work.decoder(verilog)
net "muxa_ctl365" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl366" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl367" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl368" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl369" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl370" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net pc_gen_ctl_2[1]</font>
20) instance work.decoder(verilog)-pc_gen_ctl_2[2:0], output net "pc_gen_ctl_2[1]" in work.decoder(verilog)
input nets to instance:
net "alu_func_0_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_1_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_2_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_3_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_4_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_5_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_6_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_7_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_8_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_9_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_10_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_11_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_12_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_13_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_14_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_15_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_16_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_17_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_18_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_19_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_20_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_21_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_22_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_23_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_24_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_25_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_26_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_27_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_28_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_1_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_3_sqmuxa" in work.decoder(verilog)
net "pc_gen_ctl_1[0]" in work.decoder(verilog)
net "pc_gen_ctl_1[1]" in work.decoder(verilog)
net "pc_gen_ctl_1[2]" in work.decoder(verilog)
net "alu_we_4_sqmuxa" in work.decoder(verilog)
net "pc_gen_ctl_1[0]" in work.decoder(verilog)
net "pc_gen_ctl_1[1]" in work.decoder(verilog)
net "pc_gen_ctl_1[2]" in work.decoder(verilog)
net "muxa_ctl350" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl351" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl352" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl353" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl354" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl355" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl356" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl357" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl358" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl359" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl360" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl361" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl362" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl363" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
net "pc_gen_ctl_1[0]" in work.decoder(verilog)
net "pc_gen_ctl_1[1]" in work.decoder(verilog)
net "pc_gen_ctl_1[2]" in work.decoder(verilog)
net "muxa_ctl365" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl366" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl367" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl368" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl369" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl370" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net pc_gen_ctl_2[2]</font>
21) instance work.decoder(verilog)-pc_gen_ctl_2[2:0], output net "pc_gen_ctl_2[2]" in work.decoder(verilog)
input nets to instance:
net "alu_func_0_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_1_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_2_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_3_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_4_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_5_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_6_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_7_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_8_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_9_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_10_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_11_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_12_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_13_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_14_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_15_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_16_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_17_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_18_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_19_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_20_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_21_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_22_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_23_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_24_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_25_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_26_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_27_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_28_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_1_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_3_sqmuxa" in work.decoder(verilog)
net "pc_gen_ctl_1[0]" in work.decoder(verilog)
net "pc_gen_ctl_1[1]" in work.decoder(verilog)
net "pc_gen_ctl_1[2]" in work.decoder(verilog)
net "alu_we_4_sqmuxa" in work.decoder(verilog)
net "pc_gen_ctl_1[0]" in work.decoder(verilog)
net "pc_gen_ctl_1[1]" in work.decoder(verilog)
net "pc_gen_ctl_1[2]" in work.decoder(verilog)
net "muxa_ctl350" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl351" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl352" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl353" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl354" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl355" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl356" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl357" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl358" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl359" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl360" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl361" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl362" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl363" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
net "pc_gen_ctl_1[0]" in work.decoder(verilog)
net "pc_gen_ctl_1[1]" in work.decoder(verilog)
net "pc_gen_ctl_1[2]" in work.decoder(verilog)
net "muxa_ctl365" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl366" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl367" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl368" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl369" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl370" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net rd_sel_2[0]</font>
22) instance work.decoder(verilog)-rd_sel_2[1:0], output net "rd_sel_2[0]" in work.decoder(verilog)
input nets to instance:
net "alu_func_0_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_1_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_2_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_3_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_4_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_5_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_6_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_7_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_8_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_9_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_10_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_11_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_12_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_13_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_14_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_15_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_16_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_17_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_18_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_19_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_20_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_21_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_22_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_23_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_24_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_25_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_26_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_27_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_28_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_3_sqmuxa" in work.decoder(verilog)
net "rd_sel_1[0]" in work.decoder(verilog)
net "rd_sel_1[1]" in work.decoder(verilog)
net "alu_we_4_sqmuxa" in work.decoder(verilog)
net "rd_sel_1[0]" in work.decoder(verilog)
net "rd_sel_1[1]" in work.decoder(verilog)
net "muxa_ctl350" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl351" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl352" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl353" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl354" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl355" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl356" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl357" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl358" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl359" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl360" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl361" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl362" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl363" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
net "rd_sel_1[0]" in work.decoder(verilog)
net "rd_sel_1[1]" in work.decoder(verilog)
net "muxa_ctl365" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl366" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl367" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl368" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl369" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl370" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net rd_sel_2[1]</font>
23) instance work.decoder(verilog)-rd_sel_2[1:0], output net "rd_sel_2[1]" in work.decoder(verilog)
input nets to instance:
net "alu_func_0_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_1_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_2_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_3_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_4_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_5_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_6_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_7_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_8_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_9_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_10_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_11_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_12_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_13_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_14_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_15_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_16_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_17_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_18_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_19_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_20_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_21_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_22_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_23_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_24_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_25_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_26_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_27_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_28_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_3_sqmuxa" in work.decoder(verilog)
net "rd_sel_1[0]" in work.decoder(verilog)
net "rd_sel_1[1]" in work.decoder(verilog)
net "alu_we_4_sqmuxa" in work.decoder(verilog)
net "rd_sel_1[0]" in work.decoder(verilog)
net "rd_sel_1[1]" in work.decoder(verilog)
net "muxa_ctl350" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl351" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl352" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl353" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl354" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl355" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl356" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl357" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl358" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl359" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl360" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl361" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl362" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl363" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
net "rd_sel_1[0]" in work.decoder(verilog)
net "rd_sel_1[1]" in work.decoder(verilog)
net "muxa_ctl365" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl366" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl367" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl368" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl369" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl370" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net cmp_ctl_2[0]</font>
24) instance work.decoder(verilog)-cmp_ctl_2[2:0], output net "cmp_ctl_2[0]" in work.decoder(verilog)
input nets to instance:
net "un1_muxa_ctl352_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_1_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "un1_alu_we_3_sqmuxa" in work.decoder(verilog)
net "cmp_ctl_1[0]" in work.decoder(verilog)
net "cmp_ctl_1[1]" in work.decoder(verilog)
net "cmp_ctl_1[2]" in work.decoder(verilog)
net "muxa_ctl352" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl353" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl354" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl355" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net cmp_ctl_2[1]</font>
25) instance work.decoder(verilog)-cmp_ctl_2[2:0], output net "cmp_ctl_2[1]" in work.decoder(verilog)
input nets to instance:
net "un1_muxa_ctl352_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_1_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "un1_alu_we_3_sqmuxa" in work.decoder(verilog)
net "cmp_ctl_1[0]" in work.decoder(verilog)
net "cmp_ctl_1[1]" in work.decoder(verilog)
net "cmp_ctl_1[2]" in work.decoder(verilog)
net "muxa_ctl352" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl353" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl354" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl355" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net cmp_ctl_2[2]</font>
26) instance work.decoder(verilog)-cmp_ctl_2[2:0], output net "cmp_ctl_2[2]" in work.decoder(verilog)
input nets to instance:
net "un1_muxa_ctl352_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_1_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "un1_alu_we_3_sqmuxa" in work.decoder(verilog)
net "cmp_ctl_1[0]" in work.decoder(verilog)
net "cmp_ctl_1[1]" in work.decoder(verilog)
net "cmp_ctl_1[2]" in work.decoder(verilog)
net "muxa_ctl352" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl353" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl354" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl355" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net dmem_ctl_2[0]</font>
27) instance work.decoder(verilog)-dmem_ctl_2[3:0], output net "dmem_ctl_2[0]" in work.decoder(verilog)
input nets to instance:
net "un1_muxa_ctl365_2" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "un1_alu_we_3_sqmuxa" in work.decoder(verilog)
net "dmem_ctl_1[0]" in work.decoder(verilog)
net "dmem_ctl_1[1]" in work.decoder(verilog)
net "dmem_ctl_1[2]" in work.decoder(verilog)
net "dmem_ctl_1[3]" in work.decoder(verilog)
net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl365" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl366" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl368" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl369" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl370" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net dmem_ctl_2[1]</font>
28) instance work.decoder(verilog)-dmem_ctl_2[3:0], output net "dmem_ctl_2[1]" in work.decoder(verilog)
input nets to instance:
net "un1_muxa_ctl365_2" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "un1_alu_we_3_sqmuxa" in work.decoder(verilog)
net "dmem_ctl_1[0]" in work.decoder(verilog)
net "dmem_ctl_1[1]" in work.decoder(verilog)
net "dmem_ctl_1[2]" in work.decoder(verilog)
net "dmem_ctl_1[3]" in work.decoder(verilog)
net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl365" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl366" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl368" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl369" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl370" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net dmem_ctl_2[2]</font>
29) instance work.decoder(verilog)-dmem_ctl_2[3:0], output net "dmem_ctl_2[2]" in work.decoder(verilog)
input nets to instance:
net "un1_muxa_ctl365_2" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "un1_alu_we_3_sqmuxa" in work.decoder(verilog)
net "dmem_ctl_1[0]" in work.decoder(verilog)
net "dmem_ctl_1[1]" in work.decoder(verilog)
net "dmem_ctl_1[2]" in work.decoder(verilog)
net "dmem_ctl_1[3]" in work.decoder(verilog)
net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl365" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl366" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl368" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl369" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl370" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net dmem_ctl_2[3]</font>
30) instance work.decoder(verilog)-dmem_ctl_2[3:0], output net "dmem_ctl_2[3]" in work.decoder(verilog)
input nets to instance:
net "un1_muxa_ctl365_2" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "un1_alu_we_3_sqmuxa" in work.decoder(verilog)
net "dmem_ctl_1[0]" in work.decoder(verilog)
net "dmem_ctl_1[1]" in work.decoder(verilog)
net "dmem_ctl_1[2]" in work.decoder(verilog)
net "dmem_ctl_1[3]" in work.decoder(verilog)
net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl365" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl366" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl368" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl369" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl370" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
End of loops
<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:149:83:149:89:@W:BN132:@XP_MSG">ulit.v(149)</a><!@TM:1223827012> | Removing sequential instance mips_core.alu_pass0.r32_o[0], because it is equivalent to instance mips_core.MEM_CTL.dmem_ctl_post.byte_addr_o[0]</font>
<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:149:83:149:89:@W:BN132:@XP_MSG">ulit.v(149)</a><!@TM:1223827012> | Removing sequential instance mips_core.alu_pass0.r32_o[1], because it is equivalent to instance mips_core.MEM_CTL.dmem_ctl_post.byte_addr_o[1]</font>
Encoding state machine work.ctl_FSM(verilog)-CurrState_Sreg0[8:0]
original code -> new code
0000 -> 000000000
0001 -> 000000011
0010 -> 000000101
0011 -> 000001001
0100 -> 000010001
0101 -> 000100001
0110 -> 001000001
0111 -> 010000001
1000 -> 100000001
<font color=#A52A2A>@W:<a href="@W:FA140:@XP_HELP">FA140</a> : <a href="e:\mips789\mips789\rtl\verilog\ctl_fsm.v:138:16:138:17:@W:FA140:@XP_MSG">ctl_fsm.v(138)</a><!@TM:1223827012> | DFF work.ctl_FSM(verilog)-CurrState_Sreg0[5] is stuck at '0', removing ... </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\ctl_fsm.v:138:16:138:17:@W:BN116:@XP_MSG">ctl_fsm.v(138)</a><!@TM:1223827012> | Removing sequential instance CurrState_Sreg0[5] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:MO127:@XP_HELP">MO127</a> : <a href="e:\mips789\mips789\rtl\verilog\ctl_fsm.v:58:8:58:12:@W:MO127:@XP_MSG">ctl_fsm.v(58)</a><!@TM:1223827012> | Sequential instance mips_core.iRF_stage.MIAN_FSM.iack_1 has been reduced to a combinational gate by constant propagation</font>
@N: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:563:4:563:10:@N::@XP_MSG">exec_stage.v(563)</a><!@TM:1223827012> | Found counter in view:work.muldiv_ff(verilog) inst count[5:0]
Warning: Found 30 combinational loops!
Each loop is reported with an instance in the loop
and nets connected to that instance.
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
1) instance fsm_dly_2[2:0] work.decoder(verilog)-fsm_dly_2[2:0], output net "fsm_dly_2[0]" in work.decoder(verilog)
input nets to instance:
net "alu_func_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_1_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_3_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_4_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_5_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_6_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_7_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_8_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_9_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_10_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_11_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_12_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_13_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_14_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_15_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_16_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_17_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_18_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_19_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_20_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_21_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_22_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_23_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_24_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_25_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_26_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_27_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_28_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_3_sqmuxa" in work.decoder(verilog)
net "fsm_dly_1[0]" in work.decoder(verilog)
net "fsm_dly_1[1]" in work.decoder(verilog)
net "fsm_dly_1[2]" in work.decoder(verilog)
net "alu_we_4_sqmuxa" in work.decoder(verilog)
net "fsm_dly_1[0]" in work.decoder(verilog)
net "fsm_dly_1[1]" in work.decoder(verilog)
net "fsm_dly_1[2]" in work.decoder(verilog)
net "muxa_ctl350" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl351" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl352" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl353" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl354" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl355" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl356" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl357" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl358" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl359" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl360" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl361" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl362" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl363" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
net "fsm_dly_1[0]" in work.decoder(verilog)
net "fsm_dly_1[1]" in work.decoder(verilog)
net "fsm_dly_1[2]" in work.decoder(verilog)
net "muxa_ctl365" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl366" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl367" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl368" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl369" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl370" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
2) instance fsm_dly_2[2:0] work.decoder(verilog)-fsm_dly_2[2:0], output net "fsm_dly_2[1]" in work.decoder(verilog)
input nets to instance:
net "alu_func_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_1_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_3_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_4_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_5_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_6_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_7_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_8_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_9_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_10_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_11_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_12_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_13_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_14_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_15_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_16_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_17_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_18_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_19_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_20_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_21_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_22_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_23_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_24_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_25_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_26_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_27_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_28_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_3_sqmuxa" in work.decoder(verilog)
net "fsm_dly_1[0]" in work.decoder(verilog)
net "fsm_dly_1[1]" in work.decoder(verilog)
net "fsm_dly_1[2]" in work.decoder(verilog)
net "alu_we_4_sqmuxa" in work.decoder(verilog)
net "fsm_dly_1[0]" in work.decoder(verilog)
net "fsm_dly_1[1]" in work.decoder(verilog)
net "fsm_dly_1[2]" in work.decoder(verilog)
net "muxa_ctl350" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl351" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl352" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl353" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl354" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl355" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl356" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl357" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl358" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl359" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl360" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl361" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl362" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl363" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
net "fsm_dly_1[0]" in work.decoder(verilog)
net "fsm_dly_1[1]" in work.decoder(verilog)
net "fsm_dly_1[2]" in work.decoder(verilog)
net "muxa_ctl365" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl366" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl367" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl368" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl369" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl370" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
3) instance fsm_dly_2[2:0] work.decoder(verilog)-fsm_dly_2[2:0], output net "fsm_dly_2[2]" in work.decoder(verilog)
input nets to instance:
net "alu_func_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_1_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_3_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_4_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_5_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_6_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_7_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_8_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_9_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_10_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_11_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_12_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_13_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_14_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_15_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_16_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_17_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_18_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_19_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_20_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_21_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_22_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_23_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_24_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_25_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_26_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_27_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_28_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_3_sqmuxa" in work.decoder(verilog)
net "fsm_dly_1[0]" in work.decoder(verilog)
net "fsm_dly_1[1]" in work.decoder(verilog)
net "fsm_dly_1[2]" in work.decoder(verilog)
net "alu_we_4_sqmuxa" in work.decoder(verilog)
net "fsm_dly_1[0]" in work.decoder(verilog)
net "fsm_dly_1[1]" in work.decoder(verilog)
net "fsm_dly_1[2]" in work.decoder(verilog)
net "muxa_ctl350" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl351" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl352" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl353" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl354" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl355" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl356" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl357" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl358" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl359" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl360" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl361" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl362" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl363" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
net "fsm_dly_1[0]" in work.decoder(verilog)
net "fsm_dly_1[1]" in work.decoder(verilog)
net "fsm_dly_1[2]" in work.decoder(verilog)
net "muxa_ctl365" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl366" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl367" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl368" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl369" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl370" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
4) instance ext_ctl_1[0] work.decoder(verilog)-ext_ctl_1[0], output net "ext_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "ext_ctl_2[0]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
5) instance ext_ctl_1[1] work.decoder(verilog)-ext_ctl_1[1], output net "ext_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "ext_ctl_2[1]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
6) instance ext_ctl_1[2] work.decoder(verilog)-ext_ctl_1[2], output net "ext_ctl_1[2]" in work.decoder(verilog)
input nets to instance:
net "ext_ctl_2[2]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
7) instance rd_sel_1[0] work.decoder(verilog)-rd_sel_1[0], output net "rd_sel_1[0]" in work.decoder(verilog)
input nets to instance:
net "rd_sel_2[0]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
8) instance rd_sel_1[1] work.decoder(verilog)-rd_sel_1[1], output net "rd_sel_1[1]" in work.decoder(verilog)
input nets to instance:
net "rd_sel_2[1]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_22" in work.decoder(verilog)
net "muxa_ctl373" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
9) instance cmp_ctl_1[0] work.decoder(verilog)-cmp_ctl_1[0], output net "cmp_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "cmp_ctl_2[0]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
10) instance cmp_ctl_1[1] work.decoder(verilog)-cmp_ctl_1[1], output net "cmp_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "cmp_ctl_2[1]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
11) instance cmp_ctl_1[2] work.decoder(verilog)-cmp_ctl_1[2], output net "cmp_ctl_1[2]" in work.decoder(verilog)
input nets to instance:
net "cmp_ctl_2[2]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
12) instance pc_gen_ctl_1[0] work.decoder(verilog)-pc_gen_ctl_1[0], output net "pc_gen_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "pc_gen_ctl_2[0]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
13) instance pc_gen_ctl_1[1] work.decoder(verilog)-pc_gen_ctl_1[1], output net "pc_gen_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "pc_gen_ctl_2[1]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
14) instance pc_gen_ctl_1[2] work.decoder(verilog)-pc_gen_ctl_1[2], output net "pc_gen_ctl_1[2]" in work.decoder(verilog)
input nets to instance:
net "pc_gen_ctl_2[2]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
15) instance muxa_ctl_1[0] work.decoder(verilog)-muxa_ctl_1[0], output net "muxa_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "muxa_ctl_2[0]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
16) instance muxa_ctl_1[1] work.decoder(verilog)-muxa_ctl_1[1], output net "muxa_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "muxa_ctl_2[1]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
17) instance muxb_ctl_1[0] work.decoder(verilog)-muxb_ctl_1[0], output net "muxb_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "muxb_ctl_2[0]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
18) instance muxb_ctl_1[1] work.decoder(verilog)-muxb_ctl_1[1], output net "muxb_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "muxb_ctl_2[1]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
19) instance alu_func_1[0] work.decoder(verilog)-alu_func_1[0], output net "alu_func_1[0]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[0]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
20) instance alu_func_1[1] work.decoder(verilog)-alu_func_1[1], output net "alu_func_1[1]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[1]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
21) instance alu_func_1[2] work.decoder(verilog)-alu_func_1[2], output net "alu_func_1[2]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[2]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
22) instance alu_func_1[3] work.decoder(verilog)-alu_func_1[3], output net "alu_func_1[3]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[3]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
23) instance alu_func_1[4] work.decoder(verilog)-alu_func_1[4], output net "alu_func_1[4]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[4]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
24) instance dmem_ctl_1[0] work.decoder(verilog)-dmem_ctl_1[0], output net "dmem_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "dmem_ctl_2[0]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
25) instance dmem_ctl_1[1] work.decoder(verilog)-dmem_ctl_1[1], output net "dmem_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "dmem_ctl_2[1]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_22" in work.decoder(verilog)
net "muxa_ctl373" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
26) instance dmem_ctl_1[2] work.decoder(verilog)-dmem_ctl_1[2], output net "dmem_ctl_1[2]" in work.decoder(verilog)
input nets to instance:
net "dmem_ctl_2[2]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_24" in work.decoder(verilog)
net "un1_ins_i_15" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
27) instance dmem_ctl_1[3] work.decoder(verilog)-dmem_ctl_1[3], output net "dmem_ctl_1[3]" in work.decoder(verilog)
input nets to instance:
net "dmem_ctl_2[3]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
28) instance alu_we[0] work.decoder(verilog)-alu_we[0], output net "alu_we[0]" in work.decoder(verilog)
input nets to instance:
net "alu_we_1[0]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
29) instance wb_mux[0] work.decoder(verilog)-wb_mux[0], output net "wb_mux[0]" in work.decoder(verilog)
input nets to instance:
net "wb_mux_1[0]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
30) instance wb_we[0] work.decoder(verilog)-wb_we[0], output net "wb_we[0]" in work.decoder(verilog)
input nets to instance:
net "wb_we_1[0]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
End of loops
Warning: Found 28 combinational loops!
Each loop is reported with an instance in the loop
and nets connected to that instance.
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
1) instance fsm_dly_2[2:0] work.decoder(verilog)-fsm_dly_2[2:0], output net "fsm_dly_2[0]" in work.decoder(verilog)
input nets to instance:
net "alu_func_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_1_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_3_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_4_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_5_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_6_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_7_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_8_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_9_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_10_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_11_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_12_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_13_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_14_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_15_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_16_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_17_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_18_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_19_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_20_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_21_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_22_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_23_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_24_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_25_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_26_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_27_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_28_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_3_sqmuxa" in work.decoder(verilog)
net "fsm_dly_1[0]" in work.decoder(verilog)
net "fsm_dly_1[1]" in work.decoder(verilog)
net "fsm_dly_1[2]" in work.decoder(verilog)
net "alu_we_4_sqmuxa" in work.decoder(verilog)
net "fsm_dly_1[0]" in work.decoder(verilog)
net "fsm_dly_1[1]" in work.decoder(verilog)
net "fsm_dly_1[2]" in work.decoder(verilog)
net "muxa_ctl350" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl351" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "muxa_ctl352" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl353" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl354" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl355" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl356" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl357" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl358" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl359" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl360" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl361" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl362" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl363" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
net "fsm_dly_1[0]" in work.decoder(verilog)
net "fsm_dly_1[1]" in work.decoder(verilog)
net "fsm_dly_1[2]" in work.decoder(verilog)
net "muxa_ctl365" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl366" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl367" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl368" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl369" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "muxa_ctl370" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
2) instance ext_ctl_1[0] work.decoder(verilog)-ext_ctl_1[0], output net "ext_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "ext_ctl_2[0]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
3) instance ext_ctl_1[1] work.decoder(verilog)-ext_ctl_1[1], output net "ext_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "ext_ctl_2[1]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
4) instance ext_ctl_1[2] work.decoder(verilog)-ext_ctl_1[2], output net "ext_ctl_1[2]" in work.decoder(verilog)
input nets to instance:
net "ext_ctl_2[2]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
5) instance rd_sel_1[0] work.decoder(verilog)-rd_sel_1[0], output net "rd_sel_1[0]" in work.decoder(verilog)
input nets to instance:
net "rd_sel_2[0]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
6) instance rd_sel_1[1] work.decoder(verilog)-rd_sel_1[1], output net "rd_sel_1[1]" in work.decoder(verilog)
input nets to instance:
net "rd_sel_2[1]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_22" in work.decoder(verilog)
net "muxa_ctl373" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
7) instance cmp_ctl_1[0] work.decoder(verilog)-cmp_ctl_1[0], output net "cmp_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "cmp_ctl_2[0]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
8) instance cmp_ctl_1[1] work.decoder(verilog)-cmp_ctl_1[1], output net "cmp_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "cmp_ctl_2[1]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
9) instance cmp_ctl_1[2] work.decoder(verilog)-cmp_ctl_1[2], output net "cmp_ctl_1[2]" in work.decoder(verilog)
input nets to instance:
net "cmp_ctl_2[2]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
10) instance pc_gen_ctl_1[0] work.decoder(verilog)-pc_gen_ctl_1[0], output net "pc_gen_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "pc_gen_ctl_2[0]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
11) instance pc_gen_ctl_1[1] work.decoder(verilog)-pc_gen_ctl_1[1], output net "pc_gen_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "pc_gen_ctl_2[1]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
12) instance pc_gen_ctl_1[2] work.decoder(verilog)-pc_gen_ctl_1[2], output net "pc_gen_ctl_1[2]" in work.decoder(verilog)
input nets to instance:
net "pc_gen_ctl_2[2]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
13) instance muxa_ctl_1[0] work.decoder(verilog)-muxa_ctl_1[0], output net "muxa_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "muxa_ctl_2[0]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
14) instance muxa_ctl_1[1] work.decoder(verilog)-muxa_ctl_1[1], output net "muxa_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "muxa_ctl_2[1]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
15) instance muxb_ctl_1[0] work.decoder(verilog)-muxb_ctl_1[0], output net "muxb_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "muxb_ctl_2[0]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
16) instance muxb_ctl_1[1] work.decoder(verilog)-muxb_ctl_1[1], output net "muxb_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "muxb_ctl_2[1]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
17) instance alu_func_1[0] work.decoder(verilog)-alu_func_1[0], output net "alu_func_1[0]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[0]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
18) instance alu_func_1[1] work.decoder(verilog)-alu_func_1[1], output net "alu_func_1[1]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[1]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
19) instance alu_func_1[2] work.decoder(verilog)-alu_func_1[2], output net "alu_func_1[2]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[2]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
20) instance alu_func_1[3] work.decoder(verilog)-alu_func_1[3], output net "alu_func_1[3]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[3]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
21) instance alu_func_1[4] work.decoder(verilog)-alu_func_1[4], output net "alu_func_1[4]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[4]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
22) instance dmem_ctl_1[0] work.decoder(verilog)-dmem_ctl_1[0], output net "dmem_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "dmem_ctl_2[0]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
23) instance dmem_ctl_1[1] work.decoder(verilog)-dmem_ctl_1[1], output net "dmem_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "dmem_ctl_2[1]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_22" in work.decoder(verilog)
net "muxa_ctl373" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
24) instance dmem_ctl_1[2] work.decoder(verilog)-dmem_ctl_1[2], output net "dmem_ctl_1[2]" in work.decoder(verilog)
input nets to instance:
net "dmem_ctl_2[2]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_24" in work.decoder(verilog)
net "un1_ins_i_15" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
25) instance dmem_ctl_1[3] work.decoder(verilog)-dmem_ctl_1[3], output net "dmem_ctl_1[3]" in work.decoder(verilog)
input nets to instance:
net "dmem_ctl_2[3]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
26) instance alu_we[0] work.decoder(verilog)-alu_we[0], output net "alu_we[0]" in work.decoder(verilog)
input nets to instance:
net "alu_we_1[0]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
27) instance wb_mux[0] work.decoder(verilog)-wb_mux[0], output net "wb_mux[0]" in work.decoder(verilog)
input nets to instance:
net "wb_mux_1[0]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
28) instance wb_we[0] work.decoder(verilog)-wb_we[0], output net "wb_we[0]" in work.decoder(verilog)
input nets to instance:
net "wb_we_1[0]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
End of loops
@N: : <a href="e:\mips789\mips789\rtl\verilog\mips_uart.v:243:4:243:10:@N::@XP_MSG">mips_uart.v(243)</a><!@TM:1223827012> | Found counter in view:work.uart_read(verilog) inst clk_ctr[15:0]
@N: : <a href="e:\mips789\mips789\rtl\verilog\mips_uart.v:256:4:256:10:@N::@XP_MSG">mips_uart.v(256)</a><!@TM:1223827012> | Found counter in view:work.uart_read(verilog) inst bit_ctr[2:0]
Encoding state machine work.uart_read(verilog)-ua_state[4:0]
original code -> new code
000 -> 00000
001 -> 00011
010 -> 00101
011 -> 01001
100 -> 10001
@N: : <a href="e:\mips789\mips789\rtl\verilog\mips_uart.v:138:4:138:10:@N::@XP_MSG">mips_uart.v(138)</a><!@TM:1223827012> | Found counter in view:work.uart_write(verilog) inst clk_ctr[15:0]
@N: : <a href="e:\mips789\mips789\rtl\verilog\mips_uart.v:151:4:151:10:@N::@XP_MSG">mips_uart.v(151)</a><!@TM:1223827012> | Found counter in view:work.uart_write(verilog) inst bit_ctr[2:0]
Encoding state machine work.uart_write(verilog)-ua_state[7:0]
original code -> new code
000 -> 00000000
001 -> 00000011
010 -> 00000101
011 -> 00001001
100 -> 00010001
101 -> 00100001
110 -> 01000001
111 -> 10000001
@N:<a href="@N:MO106:@XP_HELP">MO106</a> : <a href="e:\mips789\mips789\rtl\verilog\dvc.v:67:12:67:16:@N:MO106:@XP_MSG">dvc.v(67)</a><!@TM:1223827012> | Found ROM, 'seg_20[6:0]', 16 words by 7 bits
@N:<a href="@N:MO106:@XP_HELP">MO106</a> : <a href="e:\mips789\mips789\rtl\verilog\dvc.v:67:12:67:16:@N:MO106:@XP_MSG">dvc.v(67)</a><!@TM:1223827012> | Found ROM, 'seg[6:0]', 16 words by 7 bits
@N: : <a href="e:\mips789\mips789\rtl\verilog\dvc.v:23:4:23:10:@N::@XP_MSG">dvc.v(23)</a><!@TM:1223827012> | Found counter in view:work.tmr0(verilog) inst cntr[31:0]
Warning: Found 28 combinational loops!
Each loop is reported with an instance in the loop
and nets connected to that instance.
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
1) instance fsm_dly_2[0] work.decoder(verilog)-fsm_dly_2[0], output net "fsm_dly_2[0]" in work.decoder(verilog)
input nets to instance:
net "N_172" in work.decoder(verilog)
net "fsm_dly_1[0]" in work.decoder(verilog)
net "N_415" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
2) instance ext_ctl_1[0] work.decoder(verilog)-ext_ctl_1[0], output net "ext_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "ext_ctl_2[0]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
3) instance ext_ctl_1[1] work.decoder(verilog)-ext_ctl_1[1], output net "ext_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "ext_ctl_2[1]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
4) instance ext_ctl_1[2] work.decoder(verilog)-ext_ctl_1[2], output net "ext_ctl_1[2]" in work.decoder(verilog)
input nets to instance:
net "ext_ctl_2[2]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
5) instance rd_sel_1[0] work.decoder(verilog)-rd_sel_1[0], output net "rd_sel_1[0]" in work.decoder(verilog)
input nets to instance:
net "rd_sel_2[0]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
6) instance rd_sel_1[1] work.decoder(verilog)-rd_sel_1[1], output net "rd_sel_1[1]" in work.decoder(verilog)
input nets to instance:
net "rd_sel_2[1]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "N_438" in work.decoder(verilog)
net "muxa_ctl373" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
7) instance cmp_ctl_1[0] work.decoder(verilog)-cmp_ctl_1[0], output net "cmp_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "cmp_ctl_2[0]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
8) instance cmp_ctl_1[1] work.decoder(verilog)-cmp_ctl_1[1], output net "cmp_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "cmp_ctl_2[1]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
9) instance cmp_ctl_1[2] work.decoder(verilog)-cmp_ctl_1[2], output net "cmp_ctl_1[2]" in work.decoder(verilog)
input nets to instance:
net "cmp_ctl_2[2]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
10) instance pc_gen_ctl_1[0] work.decoder(verilog)-pc_gen_ctl_1[0], output net "pc_gen_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "pc_gen_ctl_2[0]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
11) instance pc_gen_ctl_1[1] work.decoder(verilog)-pc_gen_ctl_1[1], output net "pc_gen_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "pc_gen_ctl_2[1]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
12) instance pc_gen_ctl_1[2] work.decoder(verilog)-pc_gen_ctl_1[2], output net "pc_gen_ctl_1[2]" in work.decoder(verilog)
input nets to instance:
net "pc_gen_ctl_2[2]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
13) instance muxa_ctl_1[0] work.decoder(verilog)-muxa_ctl_1[0], output net "muxa_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "muxa_ctl_2[0]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
14) instance muxa_ctl_1[1] work.decoder(verilog)-muxa_ctl_1[1], output net "muxa_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "muxa_ctl_2[1]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
15) instance muxb_ctl_1[0] work.decoder(verilog)-muxb_ctl_1[0], output net "muxb_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "muxb_ctl_2[0]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
16) instance muxb_ctl_1[1] work.decoder(verilog)-muxb_ctl_1[1], output net "muxb_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "muxb_ctl_2[1]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
17) instance alu_func_1[0] work.decoder(verilog)-alu_func_1[0], output net "alu_func_1[0]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[0]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
18) instance alu_func_1[1] work.decoder(verilog)-alu_func_1[1], output net "alu_func_1[1]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[1]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
19) instance alu_func_1[2] work.decoder(verilog)-alu_func_1[2], output net "alu_func_1[2]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[2]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
20) instance alu_func_1[3] work.decoder(verilog)-alu_func_1[3], output net "alu_func_1[3]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[3]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
21) instance alu_func_1[4] work.decoder(verilog)-alu_func_1[4], output net "alu_func_1[4]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[4]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
22) instance dmem_ctl_1[0] work.decoder(verilog)-dmem_ctl_1[0], output net "dmem_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "dmem_ctl_2[0]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
23) instance dmem_ctl_1[1] work.decoder(verilog)-dmem_ctl_1[1], output net "dmem_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "dmem_ctl_2[1]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "N_438" in work.decoder(verilog)
net "muxa_ctl373" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
24) instance dmem_ctl_1[2] work.decoder(verilog)-dmem_ctl_1[2], output net "dmem_ctl_1[2]" in work.decoder(verilog)
input nets to instance:
net "dmem_ctl_2[2]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_24" in work.decoder(verilog)
net "un1_ins_i_15" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
25) instance dmem_ctl_1[3] work.decoder(verilog)-dmem_ctl_1[3], output net "dmem_ctl_1[3]" in work.decoder(verilog)
input nets to instance:
net "dmem_ctl_2[3]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
26) instance alu_we[0] work.decoder(verilog)-alu_we[0], output net "alu_we[0]" in work.decoder(verilog)
input nets to instance:
net "alu_we_1[0]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
27) instance wb_mux[0] work.decoder(verilog)-wb_mux[0], output net "wb_mux[0]" in work.decoder(verilog)
input nets to instance:
net "wb_mux_1[0]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
28) instance wb_we[0] work.decoder(verilog)-wb_we[0], output net "wb_we[0]" in work.decoder(verilog)
input nets to instance:
net "wb_we_1[0]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
End of loops
Warning: Found 28 combinational loops!
Each loop is reported with an instance in the loop
and nets connected to that instance.
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
1) instance fsm_dly_2[0] work.decoder(verilog)-fsm_dly_2[0], output net "fsm_dly_2[0]" in work.decoder(verilog)
input nets to instance:
net "N_172" in work.decoder(verilog)
net "fsm_dly_1[0]" in work.decoder(verilog)
net "N_415" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
2) instance ext_ctl_1[0] work.decoder(verilog)-ext_ctl_1[0], output net "ext_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "ext_ctl_2[0]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
3) instance ext_ctl_1[1] work.decoder(verilog)-ext_ctl_1[1], output net "ext_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "ext_ctl_2[1]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
4) instance ext_ctl_1[2] work.decoder(verilog)-ext_ctl_1[2], output net "ext_ctl_1[2]" in work.decoder(verilog)
input nets to instance:
net "ext_ctl_2[2]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
5) instance rd_sel_1[0] work.decoder(verilog)-rd_sel_1[0], output net "rd_sel_1[0]" in work.decoder(verilog)
input nets to instance:
net "rd_sel_2[0]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
6) instance rd_sel_1[1] work.decoder(verilog)-rd_sel_1[1], output net "rd_sel_1[1]" in work.decoder(verilog)
input nets to instance:
net "rd_sel_2[1]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "N_438" in work.decoder(verilog)
net "muxa_ctl373" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
7) instance cmp_ctl_1[0] work.decoder(verilog)-cmp_ctl_1[0], output net "cmp_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "cmp_ctl_2[0]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
8) instance cmp_ctl_1[1] work.decoder(verilog)-cmp_ctl_1[1], output net "cmp_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "cmp_ctl_2[1]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
9) instance cmp_ctl_1[2] work.decoder(verilog)-cmp_ctl_1[2], output net "cmp_ctl_1[2]" in work.decoder(verilog)
input nets to instance:
net "cmp_ctl_2[2]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
10) instance pc_gen_ctl_1[0] work.decoder(verilog)-pc_gen_ctl_1[0], output net "pc_gen_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "pc_gen_ctl_2[0]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
11) instance pc_gen_ctl_1[1] work.decoder(verilog)-pc_gen_ctl_1[1], output net "pc_gen_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "pc_gen_ctl_2[1]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
12) instance pc_gen_ctl_1[2] work.decoder(verilog)-pc_gen_ctl_1[2], output net "pc_gen_ctl_1[2]" in work.decoder(verilog)
input nets to instance:
net "pc_gen_ctl_2[2]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
13) instance muxa_ctl_1[0] work.decoder(verilog)-muxa_ctl_1[0], output net "muxa_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "muxa_ctl_2[0]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
14) instance muxa_ctl_1[1] work.decoder(verilog)-muxa_ctl_1[1], output net "muxa_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "muxa_ctl_2[1]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
15) instance muxb_ctl_1[0] work.decoder(verilog)-muxb_ctl_1[0], output net "muxb_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "muxb_ctl_2[0]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
16) instance muxb_ctl_1[1] work.decoder(verilog)-muxb_ctl_1[1], output net "muxb_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "muxb_ctl_2[1]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
17) instance alu_func_1[0] work.decoder(verilog)-alu_func_1[0], output net "alu_func_1[0]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[0]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
18) instance alu_func_1[1] work.decoder(verilog)-alu_func_1[1], output net "alu_func_1[1]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[1]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
19) instance alu_func_1[2] work.decoder(verilog)-alu_func_1[2], output net "alu_func_1[2]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[2]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
20) instance alu_func_1[3] work.decoder(verilog)-alu_func_1[3], output net "alu_func_1[3]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[3]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
21) instance alu_func_1[4] work.decoder(verilog)-alu_func_1[4], output net "alu_func_1[4]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[4]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
22) instance dmem_ctl_1[0] work.decoder(verilog)-dmem_ctl_1[0], output net "dmem_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "dmem_ctl_2[0]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
23) instance dmem_ctl_1[1] work.decoder(verilog)-dmem_ctl_1[1], output net "dmem_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "dmem_ctl_2[1]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "N_438" in work.decoder(verilog)
net "muxa_ctl373" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
24) instance dmem_ctl_1[2] work.decoder(verilog)-dmem_ctl_1[2], output net "dmem_ctl_1[2]" in work.decoder(verilog)
input nets to instance:
net "dmem_ctl_2[2]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_24" in work.decoder(verilog)
net "un1_ins_i_15" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
25) instance dmem_ctl_1[3] work.decoder(verilog)-dmem_ctl_1[3], output net "dmem_ctl_1[3]" in work.decoder(verilog)
input nets to instance:
net "dmem_ctl_2[3]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
26) instance alu_we[0] work.decoder(verilog)-alu_we[0], output net "alu_we[0]" in work.decoder(verilog)
input nets to instance:
net "alu_we_1[0]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
27) instance wb_mux[0] work.decoder(verilog)-wb_mux[0], output net "wb_mux[0]" in work.decoder(verilog)
input nets to instance:
net "wb_mux_1[0]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
28) instance wb_we[0] work.decoder(verilog)-wb_we[0], output net "wb_we[0]" in work.decoder(verilog)
input nets to instance:
net "wb_we_1[0]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
End of loops
Warning: Found 28 combinational loops!
Each loop is reported with an instance in the loop
and nets connected to that instance.
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
1) instance fsm_dly_2[0] work.decoder(verilog)-fsm_dly_2[0], output net "fsm_dly_2[0]" in work.decoder(verilog)
input nets to instance:
net "N_172" in work.decoder(verilog)
net "fsm_dly_1[0]" in work.decoder(verilog)
net "N_415" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
2) instance ext_ctl_1[0] work.decoder(verilog)-ext_ctl_1[0], output net "ext_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "ext_ctl_2[0]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
3) instance ext_ctl_1[1] work.decoder(verilog)-ext_ctl_1[1], output net "ext_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "ext_ctl_2[1]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
4) instance ext_ctl_1[2] work.decoder(verilog)-ext_ctl_1[2], output net "ext_ctl_1[2]" in work.decoder(verilog)
input nets to instance:
net "ext_ctl_2[2]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
5) instance rd_sel_1[0] work.decoder(verilog)-rd_sel_1[0], output net "rd_sel_1[0]" in work.decoder(verilog)
input nets to instance:
net "rd_sel_2[0]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
6) instance rd_sel_1[1] work.decoder(verilog)-rd_sel_1[1], output net "rd_sel_1[1]" in work.decoder(verilog)
input nets to instance:
net "rd_sel_2[1]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "N_438" in work.decoder(verilog)
net "muxa_ctl373" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
7) instance cmp_ctl_1[0] work.decoder(verilog)-cmp_ctl_1[0], output net "cmp_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "cmp_ctl_2[0]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
8) instance cmp_ctl_1[1] work.decoder(verilog)-cmp_ctl_1[1], output net "cmp_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "cmp_ctl_2[1]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
9) instance cmp_ctl_1[2] work.decoder(verilog)-cmp_ctl_1[2], output net "cmp_ctl_1[2]" in work.decoder(verilog)
input nets to instance:
net "cmp_ctl_2[2]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
10) instance pc_gen_ctl_1[0] work.decoder(verilog)-pc_gen_ctl_1[0], output net "pc_gen_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "pc_gen_ctl_2[0]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
11) instance pc_gen_ctl_1[1] work.decoder(verilog)-pc_gen_ctl_1[1], output net "pc_gen_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "pc_gen_ctl_2[1]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
12) instance pc_gen_ctl_1[2] work.decoder(verilog)-pc_gen_ctl_1[2], output net "pc_gen_ctl_1[2]" in work.decoder(verilog)
input nets to instance:
net "pc_gen_ctl_2[2]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
13) instance muxa_ctl_1[0] work.decoder(verilog)-muxa_ctl_1[0], output net "muxa_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "muxa_ctl_2[0]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
14) instance muxa_ctl_1[1] work.decoder(verilog)-muxa_ctl_1[1], output net "muxa_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "muxa_ctl_2[1]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
15) instance muxb_ctl_1[0] work.decoder(verilog)-muxb_ctl_1[0], output net "muxb_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "muxb_ctl_2[0]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
16) instance muxb_ctl_1[1] work.decoder(verilog)-muxb_ctl_1[1], output net "muxb_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "muxb_ctl_2[1]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
17) instance alu_func_1[0] work.decoder(verilog)-alu_func_1[0], output net "alu_func_1[0]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[0]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
18) instance alu_func_1[1] work.decoder(verilog)-alu_func_1[1], output net "alu_func_1[1]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[1]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
19) instance alu_func_1[2] work.decoder(verilog)-alu_func_1[2], output net "alu_func_1[2]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[2]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
20) instance alu_func_1[3] work.decoder(verilog)-alu_func_1[3], output net "alu_func_1[3]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[3]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
21) instance alu_func_1[4] work.decoder(verilog)-alu_func_1[4], output net "alu_func_1[4]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[4]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
22) instance dmem_ctl_1[0] work.decoder(verilog)-dmem_ctl_1[0], output net "dmem_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "dmem_ctl_2[0]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
23) instance dmem_ctl_1[1] work.decoder(verilog)-dmem_ctl_1[1], output net "dmem_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "dmem_ctl_2[1]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "N_438" in work.decoder(verilog)
net "muxa_ctl373" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
24) instance dmem_ctl_1[2] work.decoder(verilog)-dmem_ctl_1[2], output net "dmem_ctl_1[2]" in work.decoder(verilog)
input nets to instance:
net "dmem_ctl_2[2]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "un1_ins_i_24" in work.decoder(verilog)
net "un1_ins_i_15" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
25) instance dmem_ctl_1[3] work.decoder(verilog)-dmem_ctl_1[3], output net "dmem_ctl_1[3]" in work.decoder(verilog)
input nets to instance:
net "dmem_ctl_2[3]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
26) instance alu_we[0] work.decoder(verilog)-alu_we[0], output net "alu_we[0]" in work.decoder(verilog)
input nets to instance:
net "alu_we_1[0]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
27) instance wb_mux[0] work.decoder(verilog)-wb_mux[0], output net "wb_mux[0]" in work.decoder(verilog)
input nets to instance:
net "wb_mux_1[0]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
28) instance wb_we[0] work.decoder(verilog)-wb_we[0], output net "wb_we[0]" in work.decoder(verilog)
input nets to instance:
net "wb_we_1[0]" in work.decoder(verilog)
net "un1_muxa_ctl370" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
End of loops
Automatic dissolve during optimization of view:work.mips_core(verilog) of iRF_stage.reg_bank(reg_array)
Auto Dissolve of decoder_pipe (inst of view:work.decode_pipe(verilog))
Auto Dissolve of iRF_stage.i_cmp (inst of view:work.compare(verilog))
Auto Dissolve of mips_tmr0 (inst of view:work.tmr0(verilog))
Warning: Found 28 combinational loops!
Each loop is reported with an instance in the loop
and nets connected to that instance.
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
1) instance mips_core.decoder_pipe.idecoder.fsm_dly_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.fsm_dly_1[0], output net "mips_core.BUS197[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.fsm_dly_2[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
2) instance mips_core.decoder_pipe.idecoder.ext_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.ext_ctl_1[0], output net "mips_core.decoder_pipe.BUS2072[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.N_1373" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
3) instance mips_core.decoder_pipe.idecoder.ext_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.ext_ctl_1[1], output net "mips_core.decoder_pipe.BUS2072[1]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.N_1374" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
4) instance mips_core.decoder_pipe.idecoder.ext_ctl_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.ext_ctl_1[2], output net "mips_core.decoder_pipe.BUS2072[2]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.ext_ctl_2[2]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
5) instance mips_core.decoder_pipe.idecoder.rd_sel_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.rd_sel_1[0], output net "mips_core.decoder_pipe.BUS2110[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.rd_sel_2[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
6) instance mips_core.decoder_pipe.idecoder.rd_sel_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.rd_sel_1[1], output net "mips_core.decoder_pipe.BUS2110[1]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.rd_sel_2[1]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_438" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.muxa_ctl373" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
7) instance mips_core.decoder_pipe.idecoder.cmp_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.cmp_ctl_1[0], output net "mips_core.decoder_pipe.BUS2056[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.cmp_ctl_2[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
8) instance mips_core.decoder_pipe.idecoder.cmp_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.cmp_ctl_1[1], output net "mips_core.decoder_pipe.BUS2056[1]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.cmp_ctl_2[1]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
9) instance mips_core.decoder_pipe.idecoder.cmp_ctl_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.cmp_ctl_1[2], output net "mips_core.decoder_pipe.BUS2056[2]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.cmp_ctl_2[2]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
10) instance mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[0], output net "mips_core.decoder_pipe.BUS2102[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.N_1376" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
11) instance mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[1], output net "mips_core.decoder_pipe.BUS2102[1]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.pc_gen_ctl_2[1]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
12) instance mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[2], output net "mips_core.decoder_pipe.BUS2102[2]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.N_1260_i" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
13) instance mips_core.decoder_pipe.idecoder.muxa_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxa_ctl_1[0], output net "mips_core.decoder_pipe.BUS2086[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.muxa_ctl_2[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
14) instance mips_core.decoder_pipe.idecoder.muxa_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxa_ctl_1[1], output net "mips_core.decoder_pipe.BUS2086[1]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.muxa_ctl_2[1]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
15) instance mips_core.decoder_pipe.idecoder.muxb_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxb_ctl_1[0], output net "mips_core.decoder_pipe.BUS2094[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.muxb_ctl_2[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
16) instance mips_core.decoder_pipe.idecoder.muxb_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxb_ctl_1[1], output net "mips_core.decoder_pipe.BUS2094[1]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.muxb_ctl_2[1]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
17) instance mips_core.decoder_pipe.idecoder.alu_func_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[0], output net "mips_core.decoder_pipe.BUS2040[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.alu_func_2[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
18) instance mips_core.decoder_pipe.idecoder.alu_func_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[1], output net "mips_core.decoder_pipe.BUS2040[1]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.alu_func_2[1]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
19) instance mips_core.decoder_pipe.idecoder.alu_func_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[2], output net "mips_core.decoder_pipe.BUS2040[2]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.N_1372" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
20) instance mips_core.decoder_pipe.idecoder.alu_func_1[3] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[3], output net "mips_core.decoder_pipe.BUS2040[3]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.alu_func_2[3]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
21) instance mips_core.decoder_pipe.idecoder.alu_func_1[4] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[4], output net "mips_core.decoder_pipe.BUS2040[4]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.alu_func_2[4]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
22) instance mips_core.decoder_pipe.idecoder.dmem_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[0], output net "mips_core.decoder_pipe.BUS2064[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
23) instance mips_core.decoder_pipe.idecoder.dmem_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[1], output net "mips_core.decoder_pipe.BUS2064[1]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[1]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_438" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.muxa_ctl373" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
24) instance mips_core.decoder_pipe.idecoder.dmem_ctl_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[2], output net "mips_core.decoder_pipe.BUS2064[2]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[2]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_24" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_15" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
25) instance mips_core.decoder_pipe.idecoder.dmem_ctl_1[3] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[3], output net "mips_core.decoder_pipe.BUS2064[3]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[3]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
26) instance mips_core.decoder_pipe.idecoder.alu_we[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_we[0], output net "mips_core.decoder_pipe.BUS2048[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.alu_we_1[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
27) instance mips_core.decoder_pipe.idecoder.wb_mux[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.wb_mux[0], output net "mips_core.decoder_pipe.BUS2118[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.wb_mux_1[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
28) instance mips_core.decoder_pipe.idecoder.wb_we[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.wb_we[0], output net "mips_core.decoder_pipe.BUS2126[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.wb_we_1[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
End of loops
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\mips_dvc.v:113:4:113:10:@W:BN116:@XP_MSG">mips_dvc.v(113)</a><!@TM:1223827012> | Removing sequential instance imips_dvc.key2_addr[31] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\mips_dvc.v:113:4:113:10:@W:BN116:@XP_MSG">mips_dvc.v(113)</a><!@TM:1223827012> | Removing sequential instance imips_dvc.key2_addr[30] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\mips_dvc.v:113:4:113:10:@W:BN116:@XP_MSG">mips_dvc.v(113)</a><!@TM:1223827012> | Removing sequential instance imips_dvc.key2_addr[29] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\mips_dvc.v:113:4:113:10:@W:BN116:@XP_MSG">mips_dvc.v(113)</a><!@TM:1223827012> | Removing sequential instance imips_dvc.key2_addr[28] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\mips_dvc.v:113:4:113:10:@W:BN116:@XP_MSG">mips_dvc.v(113)</a><!@TM:1223827012> | Removing sequential instance imips_dvc.key2_addr[27] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\mips_dvc.v:113:4:113:10:@W:BN116:@XP_MSG">mips_dvc.v(113)</a><!@TM:1223827012> | Removing sequential instance imips_dvc.key2_addr[26] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\mips_dvc.v:113:4:113:10:@W:BN116:@XP_MSG">mips_dvc.v(113)</a><!@TM:1223827012> | Removing sequential instance imips_dvc.key2_addr[25] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\mips_dvc.v:113:4:113:10:@W:BN116:@XP_MSG">mips_dvc.v(113)</a><!@TM:1223827012> | Removing sequential instance imips_dvc.key2_addr[24] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\mips_dvc.v:113:4:113:10:@W:BN116:@XP_MSG">mips_dvc.v(113)</a><!@TM:1223827012> | Removing sequential instance imips_dvc.key2_addr[23] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\mips_dvc.v:113:4:113:10:@W:BN116:@XP_MSG">mips_dvc.v(113)</a><!@TM:1223827012> | Removing sequential instance imips_dvc.key2_addr[22] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\mips_dvc.v:113:4:113:10:@W:BN116:@XP_MSG">mips_dvc.v(113)</a><!@TM:1223827012> | Removing sequential instance imips_dvc.key2_addr[21] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\mips_dvc.v:113:4:113:10:@W:BN116:@XP_MSG">mips_dvc.v(113)</a><!@TM:1223827012> | Removing sequential instance imips_dvc.key2_addr[20] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\mips_dvc.v:113:4:113:10:@W:BN116:@XP_MSG">mips_dvc.v(113)</a><!@TM:1223827012> | Removing sequential instance imips_dvc.key2_addr[19] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\mips_dvc.v:113:4:113:10:@W:BN116:@XP_MSG">mips_dvc.v(113)</a><!@TM:1223827012> | Removing sequential instance imips_dvc.key2_addr[18] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\mips_dvc.v:113:4:113:10:@W:BN116:@XP_MSG">mips_dvc.v(113)</a><!@TM:1223827012> | Removing sequential instance imips_dvc.key2_addr[17] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\mips_dvc.v:113:4:113:10:@W:BN116:@XP_MSG">mips_dvc.v(113)</a><!@TM:1223827012> | Removing sequential instance imips_dvc.key2_addr[16] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\mips_dvc.v:113:4:113:10:@W:BN116:@XP_MSG">mips_dvc.v(113)</a><!@TM:1223827012> | Removing sequential instance imips_dvc.key2_addr[15] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\mips_dvc.v:113:4:113:10:@W:BN116:@XP_MSG">mips_dvc.v(113)</a><!@TM:1223827012> | Removing sequential instance imips_dvc.key2_addr[14] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\mips_dvc.v:113:4:113:10:@W:BN116:@XP_MSG">mips_dvc.v(113)</a><!@TM:1223827012> | Removing sequential instance imips_dvc.key2_addr[13] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\mips_dvc.v:113:4:113:10:@W:BN116:@XP_MSG">mips_dvc.v(113)</a><!@TM:1223827012> | Removing sequential instance imips_dvc.key2_addr[12] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\mips_dvc.v:113:4:113:10:@W:BN116:@XP_MSG">mips_dvc.v(113)</a><!@TM:1223827012> | Removing sequential instance imips_dvc.key2_addr[11] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\mips_dvc.v:113:4:113:10:@W:BN116:@XP_MSG">mips_dvc.v(113)</a><!@TM:1223827012> | Removing sequential instance imips_dvc.key2_addr[10] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\mips_dvc.v:113:4:113:10:@W:BN116:@XP_MSG">mips_dvc.v(113)</a><!@TM:1223827012> | Removing sequential instance imips_dvc.key2_addr[9] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\mips_dvc.v:113:4:113:10:@W:BN116:@XP_MSG">mips_dvc.v(113)</a><!@TM:1223827012> | Removing sequential instance imips_dvc.key2_addr[8] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\mips_dvc.v:113:4:113:10:@W:BN116:@XP_MSG">mips_dvc.v(113)</a><!@TM:1223827012> | Removing sequential instance imips_dvc.key2_addr[7] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\mips_dvc.v:113:4:113:10:@W:BN116:@XP_MSG">mips_dvc.v(113)</a><!@TM:1223827012> | Removing sequential instance imips_dvc.key2_addr[6] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\mips_dvc.v:113:4:113:10:@W:BN116:@XP_MSG">mips_dvc.v(113)</a><!@TM:1223827012> | Removing sequential instance imips_dvc.key2_addr[5] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\mips_dvc.v:113:4:113:10:@W:BN116:@XP_MSG">mips_dvc.v(113)</a><!@TM:1223827012> | Removing sequential instance imips_dvc.key2_addr[4] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\mips_dvc.v:113:4:113:10:@W:BN116:@XP_MSG">mips_dvc.v(113)</a><!@TM:1223827012> | Removing sequential instance imips_dvc.key2_addr[3] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\mips_dvc.v:113:4:113:10:@W:BN116:@XP_MSG">mips_dvc.v(113)</a><!@TM:1223827012> | Removing sequential instance imips_dvc.key2_addr[2] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\mips_dvc.v:113:4:113:10:@W:BN116:@XP_MSG">mips_dvc.v(113)</a><!@TM:1223827012> | Removing sequential instance imips_dvc.key2_addr[1] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\mips_dvc.v:113:4:113:10:@W:BN116:@XP_MSG">mips_dvc.v(113)</a><!@TM:1223827012> | Removing sequential instance imips_dvc.key2_addr[0] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\mips_dvc.v:113:4:113:10:@W:BN116:@XP_MSG">mips_dvc.v(113)</a><!@TM:1223827012> | Removing sequential instance imips_dvc.key1_addr[31] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\mips_dvc.v:113:4:113:10:@W:BN116:@XP_MSG">mips_dvc.v(113)</a><!@TM:1223827012> | Removing sequential instance imips_dvc.key1_addr[30] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\mips_dvc.v:113:4:113:10:@W:BN116:@XP_MSG">mips_dvc.v(113)</a><!@TM:1223827012> | Removing sequential instance imips_dvc.key1_addr[29] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\mips_dvc.v:113:4:113:10:@W:BN116:@XP_MSG">mips_dvc.v(113)</a><!@TM:1223827012> | Removing sequential instance imips_dvc.key1_addr[28] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\mips_dvc.v:113:4:113:10:@W:BN116:@XP_MSG">mips_dvc.v(113)</a><!@TM:1223827012> | Removing sequential instance imips_dvc.key1_addr[27] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\mips_dvc.v:113:4:113:10:@W:BN116:@XP_MSG">mips_dvc.v(113)</a><!@TM:1223827012> | Removing sequential instance imips_dvc.key1_addr[26] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\mips_dvc.v:113:4:113:10:@W:BN116:@XP_MSG">mips_dvc.v(113)</a><!@TM:1223827012> | Removing sequential instance imips_dvc.key1_addr[25] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\mips_dvc.v:113:4:113:10:@W:BN116:@XP_MSG">mips_dvc.v(113)</a><!@TM:1223827012> | Removing sequential instance imips_dvc.key1_addr[24] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\mips_dvc.v:113:4:113:10:@W:BN116:@XP_MSG">mips_dvc.v(113)</a><!@TM:1223827012> | Removing sequential instance imips_dvc.key1_addr[23] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\mips_dvc.v:113:4:113:10:@W:BN116:@XP_MSG">mips_dvc.v(113)</a><!@TM:1223827012> | Removing sequential instance imips_dvc.key1_addr[22] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\mips_dvc.v:113:4:113:10:@W:BN116:@XP_MSG">mips_dvc.v(113)</a><!@TM:1223827012> | Removing sequential instance imips_dvc.key1_addr[21] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\mips_dvc.v:113:4:113:10:@W:BN116:@XP_MSG">mips_dvc.v(113)</a><!@TM:1223827012> | Removing sequential instance imips_dvc.key1_addr[20] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\mips_dvc.v:113:4:113:10:@W:BN116:@XP_MSG">mips_dvc.v(113)</a><!@TM:1223827012> | Removing sequential instance imips_dvc.key1_addr[19] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\mips_dvc.v:113:4:113:10:@W:BN116:@XP_MSG">mips_dvc.v(113)</a><!@TM:1223827012> | Removing sequential instance imips_dvc.key1_addr[18] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\mips_dvc.v:113:4:113:10:@W:BN116:@XP_MSG">mips_dvc.v(113)</a><!@TM:1223827012> | Removing sequential instance imips_dvc.key1_addr[17] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\mips_dvc.v:113:4:113:10:@W:BN116:@XP_MSG">mips_dvc.v(113)</a><!@TM:1223827012> | Removing sequential instance imips_dvc.key1_addr[16] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\mips_dvc.v:113:4:113:10:@W:BN116:@XP_MSG">mips_dvc.v(113)</a><!@TM:1223827012> | Removing sequential instance imips_dvc.key1_addr[15] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\mips_dvc.v:113:4:113:10:@W:BN116:@XP_MSG">mips_dvc.v(113)</a><!@TM:1223827012> | Removing sequential instance imips_dvc.key1_addr[14] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\mips_dvc.v:113:4:113:10:@W:BN116:@XP_MSG">mips_dvc.v(113)</a><!@TM:1223827012> | Removing sequential instance imips_dvc.key1_addr[13] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\mips_dvc.v:113:4:113:10:@W:BN116:@XP_MSG">mips_dvc.v(113)</a><!@TM:1223827012> | Removing sequential instance imips_dvc.key1_addr[12] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\mips_dvc.v:113:4:113:10:@W:BN116:@XP_MSG">mips_dvc.v(113)</a><!@TM:1223827012> | Removing sequential instance imips_dvc.key1_addr[11] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\mips_dvc.v:113:4:113:10:@W:BN116:@XP_MSG">mips_dvc.v(113)</a><!@TM:1223827012> | Removing sequential instance imips_dvc.key1_addr[10] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\mips_dvc.v:113:4:113:10:@W:BN116:@XP_MSG">mips_dvc.v(113)</a><!@TM:1223827012> | Removing sequential instance imips_dvc.key1_addr[9] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\mips_dvc.v:113:4:113:10:@W:BN116:@XP_MSG">mips_dvc.v(113)</a><!@TM:1223827012> | Removing sequential instance imips_dvc.key1_addr[8] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\mips_dvc.v:113:4:113:10:@W:BN116:@XP_MSG">mips_dvc.v(113)</a><!@TM:1223827012> | Removing sequential instance imips_dvc.key1_addr[7] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\mips_dvc.v:113:4:113:10:@W:BN116:@XP_MSG">mips_dvc.v(113)</a><!@TM:1223827012> | Removing sequential instance imips_dvc.key1_addr[6] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\mips_dvc.v:113:4:113:10:@W:BN116:@XP_MSG">mips_dvc.v(113)</a><!@TM:1223827012> | Removing sequential instance imips_dvc.key1_addr[5] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\mips_dvc.v:113:4:113:10:@W:BN116:@XP_MSG">mips_dvc.v(113)</a><!@TM:1223827012> | Removing sequential instance imips_dvc.key1_addr[4] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\mips_dvc.v:113:4:113:10:@W:BN116:@XP_MSG">mips_dvc.v(113)</a><!@TM:1223827012> | Removing sequential instance imips_dvc.key1_addr[3] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\mips_dvc.v:113:4:113:10:@W:BN116:@XP_MSG">mips_dvc.v(113)</a><!@TM:1223827012> | Removing sequential instance imips_dvc.key1_addr[2] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\mips_dvc.v:113:4:113:10:@W:BN116:@XP_MSG">mips_dvc.v(113)</a><!@TM:1223827012> | Removing sequential instance imips_dvc.key1_addr[1] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\mips_dvc.v:113:4:113:10:@W:BN116:@XP_MSG">mips_dvc.v(113)</a><!@TM:1223827012> | Removing sequential instance imips_dvc.key1_addr[0] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\mips_dvc.v:113:4:113:10:@W:BN116:@XP_MSG">mips_dvc.v(113)</a><!@TM:1223827012> | Removing sequential instance imips_dvc.tmr_addr[31] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\mips_dvc.v:113:4:113:10:@W:BN116:@XP_MSG">mips_dvc.v(113)</a><!@TM:1223827012> | Removing sequential instance imips_dvc.tmr_addr[30] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\mips_dvc.v:113:4:113:10:@W:BN116:@XP_MSG">mips_dvc.v(113)</a><!@TM:1223827012> | Removing sequential instance imips_dvc.tmr_addr[29] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\mips_dvc.v:113:4:113:10:@W:BN116:@XP_MSG">mips_dvc.v(113)</a><!@TM:1223827012> | Removing sequential instance imips_dvc.tmr_addr[28] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\mips_dvc.v:113:4:113:10:@W:BN116:@XP_MSG">mips_dvc.v(113)</a><!@TM:1223827012> | Removing sequential instance imips_dvc.tmr_addr[27] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\mips_dvc.v:113:4:113:10:@W:BN116:@XP_MSG">mips_dvc.v(113)</a><!@TM:1223827012> | Removing sequential instance imips_dvc.tmr_addr[26] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\mips_dvc.v:113:4:113:10:@W:BN116:@XP_MSG">mips_dvc.v(113)</a><!@TM:1223827012> | Removing sequential instance imips_dvc.tmr_addr[25] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\mips_dvc.v:113:4:113:10:@W:BN116:@XP_MSG">mips_dvc.v(113)</a><!@TM:1223827012> | Removing sequential instance imips_dvc.tmr_addr[24] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\mips_dvc.v:113:4:113:10:@W:BN116:@XP_MSG">mips_dvc.v(113)</a><!@TM:1223827012> | Removing sequential instance imips_dvc.tmr_addr[23] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\mips_dvc.v:113:4:113:10:@W:BN116:@XP_MSG">mips_dvc.v(113)</a><!@TM:1223827012> | Removing sequential instance imips_dvc.tmr_addr[22] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\mips_dvc.v:113:4:113:10:@W:BN116:@XP_MSG">mips_dvc.v(113)</a><!@TM:1223827012> | Removing sequential instance imips_dvc.tmr_addr[21] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\mips_dvc.v:113:4:113:10:@W:BN116:@XP_MSG">mips_dvc.v(113)</a><!@TM:1223827012> | Removing sequential instance imips_dvc.tmr_addr[20] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\mips_dvc.v:113:4:113:10:@W:BN116:@XP_MSG">mips_dvc.v(113)</a><!@TM:1223827012> | Removing sequential instance imips_dvc.tmr_addr[19] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\mips_dvc.v:113:4:113:10:@W:BN116:@XP_MSG">mips_dvc.v(113)</a><!@TM:1223827012> | Removing sequential instance imips_dvc.tmr_addr[18] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\mips_dvc.v:113:4:113:10:@W:BN116:@XP_MSG">mips_dvc.v(113)</a><!@TM:1223827012> | Removing sequential instance imips_dvc.tmr_addr[17] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\mips_dvc.v:113:4:113:10:@W:BN116:@XP_MSG">mips_dvc.v(113)</a><!@TM:1223827012> | Removing sequential instance imips_dvc.tmr_addr[16] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\mips_dvc.v:113:4:113:10:@W:BN116:@XP_MSG">mips_dvc.v(113)</a><!@TM:1223827012> | Removing sequential instance imips_dvc.tmr_addr[15] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\mips_dvc.v:113:4:113:10:@W:BN116:@XP_MSG">mips_dvc.v(113)</a><!@TM:1223827012> | Removing sequential instance imips_dvc.tmr_addr[14] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\mips_dvc.v:113:4:113:10:@W:BN116:@XP_MSG">mips_dvc.v(113)</a><!@TM:1223827012> | Removing sequential instance imips_dvc.tmr_addr[13] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\mips_dvc.v:113:4:113:10:@W:BN116:@XP_MSG">mips_dvc.v(113)</a><!@TM:1223827012> | Removing sequential instance imips_dvc.tmr_addr[12] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\mips_dvc.v:113:4:113:10:@W:BN116:@XP_MSG">mips_dvc.v(113)</a><!@TM:1223827012> | Removing sequential instance imips_dvc.tmr_addr[11] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\mips_dvc.v:113:4:113:10:@W:BN116:@XP_MSG">mips_dvc.v(113)</a><!@TM:1223827012> | Removing sequential instance imips_dvc.tmr_addr[10] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\mips_dvc.v:113:4:113:10:@W:BN116:@XP_MSG">mips_dvc.v(113)</a><!@TM:1223827012> | Removing sequential instance imips_dvc.tmr_addr[9] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\mips_dvc.v:113:4:113:10:@W:BN116:@XP_MSG">mips_dvc.v(113)</a><!@TM:1223827012> | Removing sequential instance imips_dvc.tmr_addr[8] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\mips_dvc.v:113:4:113:10:@W:BN116:@XP_MSG">mips_dvc.v(113)</a><!@TM:1223827012> | Removing sequential instance imips_dvc.tmr_addr[7] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\mips_dvc.v:113:4:113:10:@W:BN116:@XP_MSG">mips_dvc.v(113)</a><!@TM:1223827012> | Removing sequential instance imips_dvc.tmr_addr[6] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\mips_dvc.v:113:4:113:10:@W:BN116:@XP_MSG">mips_dvc.v(113)</a><!@TM:1223827012> | Removing sequential instance imips_dvc.tmr_addr[5] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\mips_dvc.v:113:4:113:10:@W:BN116:@XP_MSG">mips_dvc.v(113)</a><!@TM:1223827012> | Removing sequential instance imips_dvc.tmr_addr[4] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\mips_dvc.v:113:4:113:10:@W:BN116:@XP_MSG">mips_dvc.v(113)</a><!@TM:1223827012> | Removing sequential instance imips_dvc.tmr_addr[3] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\mips_dvc.v:113:4:113:10:@W:BN116:@XP_MSG">mips_dvc.v(113)</a><!@TM:1223827012> | Removing sequential instance imips_dvc.tmr_addr[2] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\mips_dvc.v:113:4:113:10:@W:BN116:@XP_MSG">mips_dvc.v(113)</a><!@TM:1223827012> | Removing sequential instance imips_dvc.tmr_addr[1] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\mips_dvc.v:113:4:113:10:@W:BN116:@XP_MSG">mips_dvc.v(113)</a><!@TM:1223827012> | Removing sequential instance imips_dvc.tmr_addr[0] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\dvc.v:45:4:45:10:@W:BN116:@XP_MSG">dvc.v(45)</a><!@TM:1223827012> | Removing sequential instance imips_dvc.mips_tmr0.itmr_d.q of view:PrimLib.dffr(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:103:111:103:117:@W:BN116:@XP_MSG">ulit.v(103)</a><!@TM:1223827012> | Removing sequential instance mips_core.iRF_stage.ins_reg.r32_o[31] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:103:111:103:117:@W:BN116:@XP_MSG">ulit.v(103)</a><!@TM:1223827012> | Removing sequential instance mips_core.iRF_stage.ins_reg.r32_o[30] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:103:111:103:117:@W:BN116:@XP_MSG">ulit.v(103)</a><!@TM:1223827012> | Removing sequential instance mips_core.iRF_stage.ins_reg.r32_o[29] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:103:111:103:117:@W:BN116:@XP_MSG">ulit.v(103)</a><!@TM:1223827012> | Removing sequential instance mips_core.iRF_stage.ins_reg.r32_o[28] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:103:111:103:117:@W:BN116:@XP_MSG">ulit.v(103)</a><!@TM:1223827012> | Removing sequential instance mips_core.iRF_stage.ins_reg.r32_o[27] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:103:111:103:117:@W:BN116:@XP_MSG">ulit.v(103)</a><!@TM:1223827012> | Removing sequential instance mips_core.iRF_stage.ins_reg.r32_o[26] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
Warning: Found 28 combinational loops!
Each loop is reported with an instance in the loop
and nets connected to that instance.
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
1) instance mips_core.decoder_pipe.idecoder.fsm_dly_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.fsm_dly_1[0], output net "mips_core.BUS197[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.fsm_dly_2[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
2) instance mips_core.decoder_pipe.idecoder.ext_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.ext_ctl_1[0], output net "mips_core.decoder_pipe.BUS2072[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.N_1373" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
3) instance mips_core.decoder_pipe.idecoder.ext_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.ext_ctl_1[1], output net "mips_core.decoder_pipe.BUS2072[1]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.N_1374" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
4) instance mips_core.decoder_pipe.idecoder.ext_ctl_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.ext_ctl_1[2], output net "mips_core.decoder_pipe.BUS2072[2]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.ext_ctl_2[2]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
5) instance mips_core.decoder_pipe.idecoder.rd_sel_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.rd_sel_1[0], output net "mips_core.decoder_pipe.BUS2110[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.rd_sel_2[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
6) instance mips_core.decoder_pipe.idecoder.rd_sel_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.rd_sel_1[1], output net "mips_core.decoder_pipe.BUS2110[1]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.rd_sel_2[1]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_438" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.muxa_ctl373" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
7) instance mips_core.decoder_pipe.idecoder.cmp_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.cmp_ctl_1[0], output net "mips_core.decoder_pipe.BUS2056[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.cmp_ctl_2[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
8) instance mips_core.decoder_pipe.idecoder.cmp_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.cmp_ctl_1[1], output net "mips_core.decoder_pipe.BUS2056[1]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.cmp_ctl_2[1]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
9) instance mips_core.decoder_pipe.idecoder.cmp_ctl_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.cmp_ctl_1[2], output net "mips_core.decoder_pipe.BUS2056[2]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.cmp_ctl_2[2]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
10) instance mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[0], output net "mips_core.decoder_pipe.BUS2102[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.N_1376" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
11) instance mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[1], output net "mips_core.decoder_pipe.BUS2102[1]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.pc_gen_ctl_2[1]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
12) instance mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[2], output net "mips_core.decoder_pipe.BUS2102[2]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.N_1260_i" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
13) instance mips_core.decoder_pipe.idecoder.muxa_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxa_ctl_1[0], output net "mips_core.decoder_pipe.BUS2086[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.muxa_ctl_2[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
14) instance mips_core.decoder_pipe.idecoder.muxa_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxa_ctl_1[1], output net "mips_core.decoder_pipe.BUS2086[1]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.muxa_ctl_2[1]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
15) instance mips_core.decoder_pipe.idecoder.muxb_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxb_ctl_1[0], output net "mips_core.decoder_pipe.BUS2094[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.muxb_ctl_2[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
16) instance mips_core.decoder_pipe.idecoder.muxb_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxb_ctl_1[1], output net "mips_core.decoder_pipe.BUS2094[1]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.muxb_ctl_2[1]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
17) instance mips_core.decoder_pipe.idecoder.alu_func_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[0], output net "mips_core.decoder_pipe.BUS2040[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.alu_func_2[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
18) instance mips_core.decoder_pipe.idecoder.alu_func_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[1], output net "mips_core.decoder_pipe.BUS2040[1]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.alu_func_2[1]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
19) instance mips_core.decoder_pipe.idecoder.alu_func_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[2], output net "mips_core.decoder_pipe.BUS2040[2]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.N_1372" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
20) instance mips_core.decoder_pipe.idecoder.alu_func_1[3] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[3], output net "mips_core.decoder_pipe.BUS2040[3]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.alu_func_2[3]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
21) instance mips_core.decoder_pipe.idecoder.alu_func_1[4] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[4], output net "mips_core.decoder_pipe.BUS2040[4]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.alu_func_2[4]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
22) instance mips_core.decoder_pipe.idecoder.dmem_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[0], output net "mips_core.decoder_pipe.BUS2064[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
23) instance mips_core.decoder_pipe.idecoder.dmem_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[1], output net "mips_core.decoder_pipe.BUS2064[1]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[1]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_438" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.muxa_ctl373" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
24) instance mips_core.decoder_pipe.idecoder.dmem_ctl_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[2], output net "mips_core.decoder_pipe.BUS2064[2]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[2]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_18_m" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_15" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
25) instance mips_core.decoder_pipe.idecoder.dmem_ctl_1[3] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[3], output net "mips_core.decoder_pipe.BUS2064[3]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[3]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
26) instance mips_core.decoder_pipe.idecoder.alu_we[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_we[0], output net "mips_core.decoder_pipe.BUS2048[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.alu_we_1[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
27) instance mips_core.decoder_pipe.idecoder.wb_mux[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.wb_mux[0], output net "mips_core.decoder_pipe.BUS2118[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.wb_mux_1[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
28) instance mips_core.decoder_pipe.idecoder.wb_we[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.wb_we[0], output net "mips_core.decoder_pipe.BUS2126[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.wb_we_1[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
End of loops
Warning: Found 28 combinational loops!
Each loop is reported with an instance in the loop
and nets connected to that instance.
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
1) instance mips_core.decoder_pipe.idecoder.fsm_dly_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.fsm_dly_1[0], output net "mips_core.BUS197[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.fsm_dly_2[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
2) instance mips_core.decoder_pipe.idecoder.ext_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.ext_ctl_1[0], output net "mips_core.decoder_pipe.BUS2072[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.N_1373" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
3) instance mips_core.decoder_pipe.idecoder.ext_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.ext_ctl_1[1], output net "mips_core.decoder_pipe.BUS2072[1]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.N_1374" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
4) instance mips_core.decoder_pipe.idecoder.ext_ctl_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.ext_ctl_1[2], output net "mips_core.decoder_pipe.BUS2072[2]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.ext_ctl_2[2]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
5) instance mips_core.decoder_pipe.idecoder.rd_sel_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.rd_sel_1[0], output net "mips_core.decoder_pipe.BUS2110[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.rd_sel_2[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
6) instance mips_core.decoder_pipe.idecoder.rd_sel_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.rd_sel_1[1], output net "mips_core.decoder_pipe.BUS2110[1]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.rd_sel_2[1]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_438" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.muxa_ctl373" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
7) instance mips_core.decoder_pipe.idecoder.cmp_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.cmp_ctl_1[0], output net "mips_core.decoder_pipe.BUS2056[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.cmp_ctl_2[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
8) instance mips_core.decoder_pipe.idecoder.cmp_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.cmp_ctl_1[1], output net "mips_core.decoder_pipe.BUS2056[1]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.cmp_ctl_2[1]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
9) instance mips_core.decoder_pipe.idecoder.cmp_ctl_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.cmp_ctl_1[2], output net "mips_core.decoder_pipe.BUS2056[2]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.cmp_ctl_2[2]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
10) instance mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[0], output net "mips_core.decoder_pipe.BUS2102[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.N_1376" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
11) instance mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[1], output net "mips_core.decoder_pipe.BUS2102[1]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.pc_gen_ctl_2[1]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
12) instance mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[2], output net "mips_core.decoder_pipe.BUS2102[2]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.N_1260_i" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
13) instance mips_core.decoder_pipe.idecoder.muxa_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxa_ctl_1[0], output net "mips_core.decoder_pipe.BUS2086[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.muxa_ctl_2[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
14) instance mips_core.decoder_pipe.idecoder.muxa_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxa_ctl_1[1], output net "mips_core.decoder_pipe.BUS2086[1]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.muxa_ctl_2[1]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
15) instance mips_core.decoder_pipe.idecoder.muxb_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxb_ctl_1[0], output net "mips_core.decoder_pipe.BUS2094[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.muxb_ctl_2[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
16) instance mips_core.decoder_pipe.idecoder.muxb_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxb_ctl_1[1], output net "mips_core.decoder_pipe.BUS2094[1]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.muxb_ctl_2[1]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
17) instance mips_core.decoder_pipe.idecoder.alu_func_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[0], output net "mips_core.decoder_pipe.BUS2040[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.alu_func_2[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
18) instance mips_core.decoder_pipe.idecoder.alu_func_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[1], output net "mips_core.decoder_pipe.BUS2040[1]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.alu_func_2[1]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
19) instance mips_core.decoder_pipe.idecoder.alu_func_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[2], output net "mips_core.decoder_pipe.BUS2040[2]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.N_1372" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
20) instance mips_core.decoder_pipe.idecoder.alu_func_1[3] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[3], output net "mips_core.decoder_pipe.BUS2040[3]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.alu_func_2[3]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
21) instance mips_core.decoder_pipe.idecoder.alu_func_1[4] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[4], output net "mips_core.decoder_pipe.BUS2040[4]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.alu_func_2[4]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
22) instance mips_core.decoder_pipe.idecoder.dmem_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[0], output net "mips_core.decoder_pipe.BUS2064[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
23) instance mips_core.decoder_pipe.idecoder.dmem_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[1], output net "mips_core.decoder_pipe.BUS2064[1]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[1]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_438" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.muxa_ctl373" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
24) instance mips_core.decoder_pipe.idecoder.dmem_ctl_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[2], output net "mips_core.decoder_pipe.BUS2064[2]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[2]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_18_m" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_15" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
25) instance mips_core.decoder_pipe.idecoder.dmem_ctl_1[3] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[3], output net "mips_core.decoder_pipe.BUS2064[3]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[3]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
26) instance mips_core.decoder_pipe.idecoder.alu_we[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_we[0], output net "mips_core.decoder_pipe.BUS2048[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.alu_we_1[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
27) instance mips_core.decoder_pipe.idecoder.wb_mux[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.wb_mux[0], output net "mips_core.decoder_pipe.BUS2118[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.wb_mux_1[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
28) instance mips_core.decoder_pipe.idecoder.wb_we[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.wb_we[0], output net "mips_core.decoder_pipe.BUS2126[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.wb_we_1[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
End of loops
Warning: Found 28 combinational loops!
Each loop is reported with an instance in the loop
and nets connected to that instance.
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
1) instance mips_core.decoder_pipe.idecoder.fsm_dly_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.fsm_dly_1[0], output net "mips_core.BUS197[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.fsm_dly_2[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
2) instance mips_core.decoder_pipe.idecoder.ext_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.ext_ctl_1[0], output net "mips_core.decoder_pipe.BUS2072[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.N_1373" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
3) instance mips_core.decoder_pipe.idecoder.ext_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.ext_ctl_1[1], output net "mips_core.decoder_pipe.BUS2072[1]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.N_1374" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
4) instance mips_core.decoder_pipe.idecoder.ext_ctl_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.ext_ctl_1[2], output net "mips_core.decoder_pipe.BUS2072[2]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.ext_ctl_2[2]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
5) instance mips_core.decoder_pipe.idecoder.rd_sel_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.rd_sel_1[0], output net "mips_core.decoder_pipe.BUS2110[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.rd_sel_2[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
6) instance mips_core.decoder_pipe.idecoder.rd_sel_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.rd_sel_1[1], output net "mips_core.decoder_pipe.BUS2110[1]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.rd_sel_2[1]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_438" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.muxa_ctl373" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
7) instance mips_core.decoder_pipe.idecoder.cmp_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.cmp_ctl_1[0], output net "mips_core.decoder_pipe.BUS2056[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.cmp_ctl_2[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
8) instance mips_core.decoder_pipe.idecoder.cmp_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.cmp_ctl_1[1], output net "mips_core.decoder_pipe.BUS2056[1]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.cmp_ctl_2[1]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
9) instance mips_core.decoder_pipe.idecoder.cmp_ctl_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.cmp_ctl_1[2], output net "mips_core.decoder_pipe.BUS2056[2]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.cmp_ctl_2[2]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
10) instance mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[0], output net "mips_core.decoder_pipe.BUS2102[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.N_1376" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
11) instance mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[1], output net "mips_core.decoder_pipe.BUS2102[1]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.pc_gen_ctl_2[1]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
12) instance mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[2], output net "mips_core.decoder_pipe.BUS2102[2]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.N_1260_i" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
13) instance mips_core.decoder_pipe.idecoder.muxa_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxa_ctl_1[0], output net "mips_core.decoder_pipe.BUS2086[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.muxa_ctl_2[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
14) instance mips_core.decoder_pipe.idecoder.muxa_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxa_ctl_1[1], output net "mips_core.decoder_pipe.BUS2086[1]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.muxa_ctl_2[1]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
15) instance mips_core.decoder_pipe.idecoder.muxb_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxb_ctl_1[0], output net "mips_core.decoder_pipe.BUS2094[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.muxb_ctl_2[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
16) instance mips_core.decoder_pipe.idecoder.muxb_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxb_ctl_1[1], output net "mips_core.decoder_pipe.BUS2094[1]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.muxb_ctl_2[1]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
17) instance mips_core.decoder_pipe.idecoder.alu_func_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[0], output net "mips_core.decoder_pipe.BUS2040[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.alu_func_2[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
18) instance mips_core.decoder_pipe.idecoder.alu_func_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[1], output net "mips_core.decoder_pipe.BUS2040[1]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.alu_func_2[1]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
19) instance mips_core.decoder_pipe.idecoder.alu_func_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[2], output net "mips_core.decoder_pipe.BUS2040[2]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.N_1372" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
20) instance mips_core.decoder_pipe.idecoder.alu_func_1[3] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[3], output net "mips_core.decoder_pipe.BUS2040[3]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.alu_func_2[3]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
21) instance mips_core.decoder_pipe.idecoder.alu_func_1[4] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[4], output net "mips_core.decoder_pipe.BUS2040[4]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.alu_func_2[4]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
22) instance mips_core.decoder_pipe.idecoder.dmem_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[0], output net "mips_core.decoder_pipe.BUS2064[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
23) instance mips_core.decoder_pipe.idecoder.dmem_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[1], output net "mips_core.decoder_pipe.BUS2064[1]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[1]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_438" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.muxa_ctl373" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
24) instance mips_core.decoder_pipe.idecoder.dmem_ctl_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[2], output net "mips_core.decoder_pipe.BUS2064[2]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[2]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_18_m" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_15" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
25) instance mips_core.decoder_pipe.idecoder.dmem_ctl_1[3] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[3], output net "mips_core.decoder_pipe.BUS2064[3]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[3]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
26) instance mips_core.decoder_pipe.idecoder.alu_we[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_we[0], output net "mips_core.decoder_pipe.BUS2048[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.alu_we_1[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
27) instance mips_core.decoder_pipe.idecoder.wb_mux[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.wb_mux[0], output net "mips_core.decoder_pipe.BUS2118[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.wb_mux_1[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
28) instance mips_core.decoder_pipe.idecoder.wb_we[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.wb_we[0], output net "mips_core.decoder_pipe.BUS2126[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.wb_we_1[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
End of loops
Warning: Found 28 combinational loops!
Each loop is reported with an instance in the loop
and nets connected to that instance.
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
1) instance mips_core.decoder_pipe.idecoder.fsm_dly_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.fsm_dly_1[0], output net "mips_core.BUS197[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.fsm_dly_2[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
2) instance mips_core.decoder_pipe.idecoder.ext_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.ext_ctl_1[0], output net "mips_core.decoder_pipe.BUS2072[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.N_1373" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
3) instance mips_core.decoder_pipe.idecoder.ext_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.ext_ctl_1[1], output net "mips_core.decoder_pipe.BUS2072[1]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.N_1374" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
4) instance mips_core.decoder_pipe.idecoder.ext_ctl_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.ext_ctl_1[2], output net "mips_core.decoder_pipe.BUS2072[2]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.ext_ctl_2[2]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
5) instance mips_core.decoder_pipe.idecoder.rd_sel_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.rd_sel_1[0], output net "mips_core.decoder_pipe.BUS2110[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.rd_sel_2[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
6) instance mips_core.decoder_pipe.idecoder.rd_sel_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.rd_sel_1[1], output net "mips_core.decoder_pipe.BUS2110[1]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.rd_sel_2[1]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_438" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.muxa_ctl373" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
7) instance mips_core.decoder_pipe.idecoder.cmp_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.cmp_ctl_1[0], output net "mips_core.decoder_pipe.BUS2056[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.cmp_ctl_2[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
8) instance mips_core.decoder_pipe.idecoder.cmp_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.cmp_ctl_1[1], output net "mips_core.decoder_pipe.BUS2056[1]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.cmp_ctl_2[1]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
9) instance mips_core.decoder_pipe.idecoder.cmp_ctl_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.cmp_ctl_1[2], output net "mips_core.decoder_pipe.BUS2056[2]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.cmp_ctl_2[2]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
10) instance mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[0], output net "mips_core.decoder_pipe.BUS2102[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.N_1376" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
11) instance mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[1], output net "mips_core.decoder_pipe.BUS2102[1]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.pc_gen_ctl_2[1]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
12) instance mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[2], output net "mips_core.decoder_pipe.BUS2102[2]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.N_1260_i" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
13) instance mips_core.decoder_pipe.idecoder.muxa_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxa_ctl_1[0], output net "mips_core.decoder_pipe.BUS2086[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.muxa_ctl_2[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
14) instance mips_core.decoder_pipe.idecoder.muxa_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxa_ctl_1[1], output net "mips_core.decoder_pipe.BUS2086[1]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.muxa_ctl_2[1]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
15) instance mips_core.decoder_pipe.idecoder.muxb_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxb_ctl_1[0], output net "mips_core.decoder_pipe.BUS2094[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.muxb_ctl_2[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
16) instance mips_core.decoder_pipe.idecoder.muxb_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxb_ctl_1[1], output net "mips_core.decoder_pipe.BUS2094[1]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.muxb_ctl_2[1]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
17) instance mips_core.decoder_pipe.idecoder.alu_func_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[0], output net "mips_core.decoder_pipe.BUS2040[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.alu_func_2[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
18) instance mips_core.decoder_pipe.idecoder.alu_func_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[1], output net "mips_core.decoder_pipe.BUS2040[1]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.alu_func_2[1]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
19) instance mips_core.decoder_pipe.idecoder.alu_func_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[2], output net "mips_core.decoder_pipe.BUS2040[2]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.N_1372" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
20) instance mips_core.decoder_pipe.idecoder.alu_func_1[3] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[3], output net "mips_core.decoder_pipe.BUS2040[3]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.alu_func_2[3]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
21) instance mips_core.decoder_pipe.idecoder.alu_func_1[4] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[4], output net "mips_core.decoder_pipe.BUS2040[4]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.alu_func_2[4]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
22) instance mips_core.decoder_pipe.idecoder.dmem_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[0], output net "mips_core.decoder_pipe.BUS2064[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
23) instance mips_core.decoder_pipe.idecoder.dmem_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[1], output net "mips_core.decoder_pipe.BUS2064[1]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[1]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_438" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.muxa_ctl373" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
24) instance mips_core.decoder_pipe.idecoder.dmem_ctl_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[2], output net "mips_core.decoder_pipe.BUS2064[2]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[2]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_18_m" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_15" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
25) instance mips_core.decoder_pipe.idecoder.dmem_ctl_1[3] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[3], output net "mips_core.decoder_pipe.BUS2064[3]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[3]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
26) instance mips_core.decoder_pipe.idecoder.alu_we[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_we[0], output net "mips_core.decoder_pipe.BUS2048[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.alu_we_1[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
27) instance mips_core.decoder_pipe.idecoder.wb_mux[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.wb_mux[0], output net "mips_core.decoder_pipe.BUS2118[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.wb_mux_1[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping</font>
28) instance mips_core.decoder_pipe.idecoder.wb_we[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.wb_we[0], output net "mips_core.decoder_pipe.BUS2126[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.wb_we_1[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
End of loops
Warning: Found 28 combinational loops!
Each loop is reported with an instance in the loop
and nets connected to that instance.
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net mips_core.BUS197[0]</font>
1) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.fsm_dly_1[0], output net "mips_core.BUS197[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.fsm_dly_2[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2072[0]</font>
2) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.ext_ctl_1[0], output net "mips_core.decoder_pipe.BUS2072[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.N_1373" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2072[1]</font>
3) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.ext_ctl_1[1], output net "mips_core.decoder_pipe.BUS2072[1]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.N_1374" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2072[2]</font>
4) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.ext_ctl_1[2], output net "mips_core.decoder_pipe.BUS2072[2]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.ext_ctl_2[2]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2110[0]</font>
5) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.rd_sel_1[0], output net "mips_core.decoder_pipe.BUS2110[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.rd_sel_2[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2110[1]</font>
6) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.rd_sel_1[1], output net "mips_core.decoder_pipe.BUS2110[1]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.rd_sel_2[1]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_438" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.muxa_ctl373" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2056[0]</font>
7) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.cmp_ctl_1[0], output net "mips_core.decoder_pipe.BUS2056[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.cmp_ctl_2[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2056[1]</font>
8) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.cmp_ctl_1[1], output net "mips_core.decoder_pipe.BUS2056[1]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.cmp_ctl_2[1]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2056[2]</font>
9) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.cmp_ctl_1[2], output net "mips_core.decoder_pipe.BUS2056[2]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.cmp_ctl_2[2]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2102[0]</font>
10) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[0], output net "mips_core.decoder_pipe.BUS2102[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.N_1376" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2102[1]</font>
11) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[1], output net "mips_core.decoder_pipe.BUS2102[1]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.pc_gen_ctl_2[1]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2102[2]</font>
12) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[2], output net "mips_core.decoder_pipe.BUS2102[2]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.N_1260_i_0" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2086[0]</font>
13) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxa_ctl_1[0], output net "mips_core.decoder_pipe.BUS2086[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.muxa_ctl_2[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2086[1]</font>
14) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxa_ctl_1[1], output net "mips_core.decoder_pipe.BUS2086[1]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.muxa_ctl_2[1]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2094[0]</font>
15) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxb_ctl_1[0], output net "mips_core.decoder_pipe.BUS2094[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.muxb_ctl_2[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2094[1]</font>
16) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxb_ctl_1[1], output net "mips_core.decoder_pipe.BUS2094[1]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.muxb_ctl_2[1]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2040[0]</font>
17) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[0], output net "mips_core.decoder_pipe.BUS2040[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.alu_func_2[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2040[1]</font>
18) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[1], output net "mips_core.decoder_pipe.BUS2040[1]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.alu_func_2[1]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2040[2]</font>
19) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[2], output net "mips_core.decoder_pipe.BUS2040[2]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.N_1372" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2040[3]</font>
20) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[3], output net "mips_core.decoder_pipe.BUS2040[3]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.alu_func_2[3]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2040[4]</font>
21) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[4], output net "mips_core.decoder_pipe.BUS2040[4]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.alu_func_2[4]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2064[0]</font>
22) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[0], output net "mips_core.decoder_pipe.BUS2064[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2064[1]</font>
23) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[1], output net "mips_core.decoder_pipe.BUS2064[1]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[1]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_438" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.muxa_ctl373" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2064[2]</font>
24) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[2], output net "mips_core.decoder_pipe.BUS2064[2]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[2]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_18_m" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_15" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2064[3]</font>
25) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[3], output net "mips_core.decoder_pipe.BUS2064[3]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[3]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2048[0]</font>
26) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_we[0], output net "mips_core.decoder_pipe.BUS2048[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.alu_we_1[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2118[0]</font>
27) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.wb_mux[0], output net "mips_core.decoder_pipe.BUS2118[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.wb_mux_1[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2126[0]</font>
28) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.wb_we[0], output net "mips_core.decoder_pipe.BUS2126[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.wb_we_1[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_muxa_ctl370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
End of loops
@N:<a href="@N:MF197:@XP_HELP">MF197</a> : <!@TM:1223827012> | Retiming summary : 0 registers retimed to 0
##### BEGIN RETIMING REPORT #####
Retiming summary : 0 registers retimed to 0
Original and Pipelined registers replaced by retiming :
None
New registers created by retiming :
None
##### END RETIMING REPORT #####
Warning: Found 28 combinational loops!
Each loop is reported with an instance in the loop
and nets connected to that instance.
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net mips_core.decoder_pipe.idecoder.fsm_dly_2_0_0[0]</font>
1) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.fsm_dly_2_0_0[0], output net "mips_core.decoder_pipe.idecoder.fsm_dly_2_0_0[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.BUS197[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.ext_ctl_2_0_0_a3_1_0[2]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.ext_ctl_2_0_0_o3[2]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.fsm_dly_2_0_0_a[0]" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net mips_core.decoder_pipe.idecoder.wb_mux_1_0_0[0]</font>
2) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.wb_mux_1_0_0[0], output net "mips_core.decoder_pipe.idecoder.wb_mux_1_0_0[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0_a2_0[1]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.BUS2118[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.wb_mux_1_0_0_a3[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.fsm_dly_2_0_0_o2_x[2]" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net mips_core.decoder_pipe.idecoder.wb_we_1_0_0[0]</font>
3) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.wb_we_1_0_0[0], output net "mips_core.decoder_pipe.idecoder.wb_we_1_0_0[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.BUS2126[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0_a2_0[1]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.fsm_dly_2_0_0_o2_x[2]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.wb_we_1_0_0_a[0]" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net mips_core.decoder_pipe.idecoder.alu_func_2_0_0[0]</font>
4) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_2_0_0[0], output net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0_a[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0_a3[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0_2_x[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0_a3_0[0]" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net mips_core.decoder_pipe.idecoder.alu_func_2_0_0[1]</font>
5) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_2_0_0[1], output net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0[1]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.BUS2040[1]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0_a2_3[1]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0_3[1]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0_a3_1[1]" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net mips_core.decoder_pipe.idecoder.alu_func_2_0_0[3]</font>
6) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_2_0_0[3], output net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0[3]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0_a3_0[3]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0_a3_1[3]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0_o3[3]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0_a[3]" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net mips_core.decoder_pipe.idecoder.alu_func_2_0_0[4]</font>
7) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_2_0_0[4], output net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0[4]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.BUS2040[4]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0_a2_3[1]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0_a[4]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0_2[4]" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net mips_core.decoder_pipe.idecoder.alu_we_1_0_0[0]</font>
8) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_we_1_0_0[0], output net "mips_core.decoder_pipe.idecoder.alu_we_1_0_0[0]" in work.mips_sys(verilog)
input nets to instance:
net "zz_ins_i_c[29]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.alu_we_1_0_0_0[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.alu_we_1_0_0_a3[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0_a3_1[1]" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net mips_core.decoder_pipe.idecoder.ext_ctl_2_0_0[2]</font>
9) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.ext_ctl_2_0_0[2], output net "mips_core.decoder_pipe.idecoder.ext_ctl_2_0_0[2]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.BUS2072[2]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.ext_ctl_2_0_0_a3_1_0[2]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.ext_ctl_2_0_0_a[2]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.ext_ctl_2_0_0_o3[2]" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net mips_core.decoder_pipe.idecoder.muxa_ctl_2_0_0[0]</font>
10) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxa_ctl_2_0_0[0], output net "mips_core.decoder_pipe.idecoder.muxa_ctl_2_0_0[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0_a2_0[1]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0_o2_x[3]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.ext_ctl_2_0_0_a2_2_x[2]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.muxa_ctl_2_0_0_a[0]" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net mips_core.decoder_pipe.idecoder.muxa_ctl_2_0_0_x[1]</font>
11) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxa_ctl_2_0_0_x[1], output net "mips_core.decoder_pipe.idecoder.muxa_ctl_2_0_0_x[1]" in work.mips_sys(verilog)
input nets to instance:
net "zz_ins_i_c[29]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.muxa_ctl_2_0_0_2[1]" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net mips_core.decoder_pipe.idecoder.muxb_ctl_2_0_0[0]</font>
12) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxb_ctl_2_0_0[0], output net "mips_core.decoder_pipe.idecoder.muxb_ctl_2_0_0[0]" in work.mips_sys(verilog)
input nets to instance:
net "zz_ins_i_c[4]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.muxa_ctl_2_0_0_a3_1[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.muxb_ctl_2_0_0_a3_0_0_x[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.muxb_ctl_2_0_0_a[0]" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net mips_core.decoder_pipe.idecoder.muxb_ctl_2_0_0[1]</font>
13) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxb_ctl_2_0_0[1], output net "mips_core.decoder_pipe.idecoder.muxb_ctl_2_0_0[1]" in work.mips_sys(verilog)
input nets to instance:
net "zz_ins_i_c[29]" in work.mips_sys(verilog)
net "zz_ins_i_c[30]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.muxb_ctl_2_0_0_0[1]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.muxb_ctl_2_0_0_a[1]" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net mips_core.decoder_pipe.idecoder.pc_gen_ctl_2_0_0[1]</font>
14) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.pc_gen_ctl_2_0_0[1], output net "mips_core.decoder_pipe.idecoder.pc_gen_ctl_2_0_0[1]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.pc_gen_ctl_2_0_0_a2_x[1]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0_a2_3_x[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.pc_gen_ctl_2_0_0_a[1]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0_a2_2_x[0]" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net mips_core.decoder_pipe.idecoder.rd_sel_2_0_0[0]</font>
15) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.rd_sel_2_0_0[0], output net "mips_core.decoder_pipe.idecoder.rd_sel_2_0_0[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.BUS2110[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0_a2_3[1]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.rd_sel_2_0_0_a[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0_a3_1[1]" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net mips_core.decoder_pipe.idecoder.rd_sel_2_0_0[1]</font>
16) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.rd_sel_2_0_0[1], output net "mips_core.decoder_pipe.idecoder.rd_sel_2_0_0[1]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.BUS2110[1]" in work.mips_sys(verilog)
net "zz_ins_i_c[31]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.rd_sel_2_0_0_0[1]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.rd_sel_2_0_0_a[1]" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net mips_core.decoder_pipe.idecoder.cmp_ctl_2_0_0[0]</font>
17) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.cmp_ctl_2_0_0[0], output net "mips_core.decoder_pipe.idecoder.cmp_ctl_2_0_0[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0_a2_0[1]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.cmp_ctl_2_0_0_a2_1[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.BUS2056[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.cmp_ctl_2_0_0_1[0]" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net mips_core.decoder_pipe.idecoder.cmp_ctl_2_0_0[1]</font>
18) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.cmp_ctl_2_0_0[1], output net "mips_core.decoder_pipe.idecoder.cmp_ctl_2_0_0[1]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.BUS2056[1]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.cmp_ctl_2_0_0_a2_0[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0_a2_0[1]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.cmp_ctl_2_0_0_a[1]" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net mips_core.decoder_pipe.idecoder.cmp_ctl_2_0_0[2]</font>
19) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.cmp_ctl_2_0_0[2], output net "mips_core.decoder_pipe.idecoder.cmp_ctl_2_0_0[2]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0_a2_0[1]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.cmp_ctl_2_0_0_a2_x[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0_a2_0_x[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.cmp_ctl_2_0_0_a[2]" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net mips_core.decoder_pipe.idecoder.dmem_ctl_2_0_0[0]</font>
20) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_2_0_0[0], output net "mips_core.decoder_pipe.idecoder.dmem_ctl_2_0_0[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0_a2_0[1]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.BUS2064[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.fsm_dly_2_0_0_o2_x[2]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0_a3_1_x[4]" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net mips_core.decoder_pipe.idecoder.dmem_ctl_2_0_0[1]</font>
21) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_2_0_0[1], output net "mips_core.decoder_pipe.idecoder.dmem_ctl_2_0_0[1]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.BUS2064[1]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0_a2_0[1]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.dmem_ctl_2_0_0_a_x[1]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.dmem_ctl_2_0_0_1[1]" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net mips_core.decoder_pipe.idecoder.dmem_ctl_2_0_0[2]</font>
22) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_2_0_0[2], output net "mips_core.decoder_pipe.idecoder.dmem_ctl_2_0_0[2]" in work.mips_sys(verilog)
input nets to instance:
net "zz_ins_i_c[29]" in work.mips_sys(verilog)
net "zz_ins_i_c[30]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.dmem_ctl_2_0_0_a3[2]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.dmem_ctl_2_0_0_a[2]" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net mips_core.decoder_pipe.idecoder.dmem_ctl_2_0_0[3]</font>
23) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_2_0_0[3], output net "mips_core.decoder_pipe.idecoder.dmem_ctl_2_0_0[3]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.BUS2064[3]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0_a2_0[1]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.fsm_dly_2_0_0_o2_x[2]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.dmem_ctl_2_0_0_a[3]" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net mips_core.decoder_pipe.idecoder.pc_gen_ctl_2_i_0[2]</font>
24) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.pc_gen_ctl_2_i_0[2], output net "mips_core.decoder_pipe.idecoder.pc_gen_ctl_2_i_0[2]" in work.mips_sys(verilog)
input nets to instance:
net "zz_ins_i_c[27]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.pc_gen_ctl_2_i_0_a[2]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.fsm_dly_2_0_0_a2_x[2]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.pc_gen_ctl_2_i_0_5[2]" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net mips_core.decoder_pipe.idecoder.alu_func_2_i_m3_0[2]</font>
25) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_2_i_m3_0[2], output net "mips_core.decoder_pipe.idecoder.alu_func_2_i_m3_0[2]" in work.mips_sys(verilog)
input nets to instance:
net "zz_ins_i_c[3]" in work.mips_sys(verilog)
net "zz_ins_i_c[28]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.alu_func_2_i_m3_0_a[2]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.alu_func_2_i_m3_0_5[2]" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net mips_core.decoder_pipe.idecoder.ext_ctl_2_i_m3_0[0]</font>
26) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.ext_ctl_2_i_m3_0[0], output net "mips_core.decoder_pipe.idecoder.ext_ctl_2_i_m3_0[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.ext_ctl_2_i_m3_0_a_x[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0_o3[3]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.ext_ctl_2_i_m3_0_2[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.fsm_dly_2_0_0_a2_x[2]" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net mips_core.decoder_pipe.idecoder.ext_ctl_2_i_m3_0[1]</font>
27) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.ext_ctl_2_i_m3_0[1], output net "mips_core.decoder_pipe.idecoder.ext_ctl_2_i_m3_0[1]" in work.mips_sys(verilog)
input nets to instance:
net "zz_ins_i_c[29]" in work.mips_sys(verilog)
net "zz_ins_i_c[28]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.alu_func_2_0_0_a2_0_x[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.ext_ctl_2_i_m3_0_a[1]" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net mips_core.decoder_pipe.idecoder.pc_gen_ctl_2_i_m3_0[0]</font>
28) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.pc_gen_ctl_2_i_m3_0[0], output net "mips_core.decoder_pipe.idecoder.pc_gen_ctl_2_i_m3_0[0]" in work.mips_sys(verilog)
input nets to instance:
net "zz_ins_i_c[4]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.pc_gen_ctl_2_i_m3_0_a_x[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.muxa_ctl_2_0_0_o2_0[1]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.pc_gen_ctl_2_i_m3_0_5[0]" in work.mips_sys(verilog)
End of loops
Writing Analyst data base E:\mips789\mips789\synplify_prj\rev_1\mips_sys.srm
Warning: Found 28 combinational loops!
Each loop is reported with an instance in the loop
and nets connected to that instance.
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net wb_mux_1_0_0_0</font>
1) instance work.decoder(netlist)-wb_mux_1_0_0[0], output net "wb_mux_1_0_0_0" in work.decoder(netlist)
input nets to instance:
net "alu_func_2_0_0_a2_0[1]" in work.decoder(netlist)
net "BUS2118_0" in work.decoder(netlist)
net "wb_mux_1_0_0_a3[0]" in work.decoder(netlist)
net "fsm_dly_2_0_0_o2_x[2]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net wb_we_1_0_0_0</font>
2) instance work.decoder(netlist)-wb_we_1_0_0[0], output net "wb_we_1_0_0_0" in work.decoder(netlist)
input nets to instance:
net "BUS2126_0" in work.decoder(netlist)
net "alu_func_2_0_0_a2_0[1]" in work.decoder(netlist)
net "fsm_dly_2_0_0_o2_x[2]" in work.decoder(netlist)
net "wb_we_1_0_0_a[0]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net muxa_ctl_2_0_0_0</font>
3) instance work.decoder(netlist)-muxa_ctl_2_0_0[0], output net "muxa_ctl_2_0_0_0" in work.decoder(netlist)
input nets to instance:
net "alu_func_2_0_0_a2_0[1]" in work.decoder(netlist)
net "alu_func_2_0_0_o2_x[3]" in work.decoder(netlist)
net "ext_ctl_2_0_0_a2_2_x[2]" in work.decoder(netlist)
net "muxa_ctl_2_0_0_a[0]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net rd_sel_2_0_0_1</font>
4) instance work.decoder(netlist)-rd_sel_2_0_0[1], output net "rd_sel_2_0_0_1" in work.decoder(netlist)
input nets to instance:
net "BUS2110_1" in work.decoder(netlist)
net "zz_ins_i_c_31" in work.decoder(netlist)
net "rd_sel_2_0_0_0[1]" in work.decoder(netlist)
net "rd_sel_2_0_0_a[1]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net rd_sel_2_0_0_0</font>
5) instance work.decoder(netlist)-rd_sel_2_0_0[0], output net "rd_sel_2_0_0_0" in work.decoder(netlist)
input nets to instance:
net "BUS2110_0" in work.decoder(netlist)
net "alu_func_2_0_0_a2_3[1]" in work.decoder(netlist)
net "rd_sel_2_0_0_a[0]" in work.decoder(netlist)
net "alu_func_2_0_0_a3_1[1]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net dmem_ctl_2_0_0_3</font>
6) instance work.decoder(netlist)-dmem_ctl_2_0_0[3], output net "dmem_ctl_2_0_0_3" in work.decoder(netlist)
input nets to instance:
net "BUS2064_3" in work.decoder(netlist)
net "alu_func_2_0_0_a2_0[1]" in work.decoder(netlist)
net "fsm_dly_2_0_0_o2_x[2]" in work.decoder(netlist)
net "dmem_ctl_2_0_0_a[3]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net dmem_ctl_2_0_0_2</font>
7) instance work.decoder(netlist)-dmem_ctl_2_0_0[2], output net "dmem_ctl_2_0_0_2" in work.decoder(netlist)
input nets to instance:
net "zz_ins_i_c_29" in work.decoder(netlist)
net "zz_ins_i_c_30" in work.decoder(netlist)
net "dmem_ctl_2_0_0_a3[2]" in work.decoder(netlist)
net "dmem_ctl_2_0_0_a[2]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net dmem_ctl_2_0_0_0</font>
8) instance work.decoder(netlist)-dmem_ctl_2_0_0[0], output net "dmem_ctl_2_0_0_0" in work.decoder(netlist)
input nets to instance:
net "alu_func_2_0_0_a2_0[1]" in work.decoder(netlist)
net "BUS2064_0" in work.decoder(netlist)
net "fsm_dly_2_0_0_o2_x[2]" in work.decoder(netlist)
net "alu_func_2_0_0_a3_1_x[4]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net dmem_ctl_2_0_0_1</font>
9) instance work.decoder(netlist)-dmem_ctl_2_0_0[1], output net "dmem_ctl_2_0_0_1" in work.decoder(netlist)
input nets to instance:
net "BUS2064_1" in work.decoder(netlist)
net "alu_func_2_0_0_a2_0[1]" in work.decoder(netlist)
net "dmem_ctl_2_0_0_a_x[1]" in work.decoder(netlist)
net "dmem_ctl_2_0_0_1[1]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net pc_gen_ctl_2_0_0_0</font>
10) instance work.decoder(netlist)-pc_gen_ctl_2_0_0[1], output net "pc_gen_ctl_2_0_0_0" in work.decoder(netlist)
input nets to instance:
net "pc_gen_ctl_2_0_0_a2_x[1]" in work.decoder(netlist)
net "alu_func_2_0_0_a2_3_x[0]" in work.decoder(netlist)
net "pc_gen_ctl_2_0_0_a[1]" in work.decoder(netlist)
net "alu_func_2_0_0_a2_2_x[0]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net muxb_ctl_2_0_0_1</font>
11) instance work.decoder(netlist)-muxb_ctl_2_0_0[1], output net "muxb_ctl_2_0_0_1" in work.decoder(netlist)
input nets to instance:
net "zz_ins_i_c_29" in work.decoder(netlist)
net "zz_ins_i_c_30" in work.decoder(netlist)
net "muxb_ctl_2_0_0_0[1]" in work.decoder(netlist)
net "muxb_ctl_2_0_0_a[1]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net muxb_ctl_2_0_0_0</font>
12) instance work.decoder(netlist)-muxb_ctl_2_0_0[0], output net "muxb_ctl_2_0_0_0" in work.decoder(netlist)
input nets to instance:
net "zz_ins_i_c_4" in work.decoder(netlist)
net "muxa_ctl_2_0_0_a3_1[0]" in work.decoder(netlist)
net "muxb_ctl_2_0_0_a3_0_0_x[0]" in work.decoder(netlist)
net "muxb_ctl_2_0_0_a[0]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net fsm_dly_2_0_0_0</font>
13) instance work.decoder(netlist)-fsm_dly_2_0_0[0], output net "fsm_dly_2_0_0_0" in work.decoder(netlist)
input nets to instance:
net "BUS197_0" in work.decoder(netlist)
net "ext_ctl_2_0_0_a3_1_0[2]" in work.decoder(netlist)
net "ext_ctl_2_0_0_o3[2]" in work.decoder(netlist)
net "fsm_dly_2_0_0_a[0]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net ext_ctl_2_0_0_0</font>
14) instance work.decoder(netlist)-ext_ctl_2_0_0[2], output net "ext_ctl_2_0_0_0" in work.decoder(netlist)
input nets to instance:
net "BUS2072_2" in work.decoder(netlist)
net "ext_ctl_2_0_0_a3_1_0[2]" in work.decoder(netlist)
net "ext_ctl_2_0_0_a[2]" in work.decoder(netlist)
net "ext_ctl_2_0_0_o3[2]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net alu_func_2_i_m3_0_0</font>
15) instance work.decoder(netlist)-alu_func_2_i_m3_0[2], output net "alu_func_2_i_m3_0_0" in work.decoder(netlist)
input nets to instance:
net "zz_ins_i_c_3" in work.decoder(netlist)
net "zz_ins_i_c_28" in work.decoder(netlist)
net "alu_func_2_i_m3_0_a[2]" in work.decoder(netlist)
net "alu_func_2_i_m3_0_5[2]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net cmp_ctl_2_0_0_0</font>
16) instance work.decoder(netlist)-cmp_ctl_2_0_0[0], output net "cmp_ctl_2_0_0_0" in work.decoder(netlist)
input nets to instance:
net "alu_func_2_0_0_a2_0[1]" in work.decoder(netlist)
net "cmp_ctl_2_0_0_a2_1[0]" in work.decoder(netlist)
net "BUS2056_0" in work.decoder(netlist)
net "cmp_ctl_2_0_0_1[0]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net cmp_ctl_2_0_0_2</font>
17) instance work.decoder(netlist)-cmp_ctl_2_0_0[2], output net "cmp_ctl_2_0_0_2" in work.decoder(netlist)
input nets to instance:
net "alu_func_2_0_0_a2_0[1]" in work.decoder(netlist)
net "cmp_ctl_2_0_0_a2_x[0]" in work.decoder(netlist)
net "alu_func_2_0_0_a2_0_x[0]" in work.decoder(netlist)
net "cmp_ctl_2_0_0_a[2]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net cmp_ctl_2_0_0_1</font>
18) instance work.decoder(netlist)-cmp_ctl_2_0_0[1], output net "cmp_ctl_2_0_0_1" in work.decoder(netlist)
input nets to instance:
net "BUS2056_1" in work.decoder(netlist)
net "cmp_ctl_2_0_0_a2_0[0]" in work.decoder(netlist)
net "alu_func_2_0_0_a2_0[1]" in work.decoder(netlist)
net "cmp_ctl_2_0_0_a[1]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net alu_we_1_0_0_0</font>
19) instance work.decoder(netlist)-alu_we_1_0_0[0], output net "alu_we_1_0_0_0" in work.decoder(netlist)
input nets to instance:
net "zz_ins_i_c_29" in work.decoder(netlist)
net "alu_we_1_0_0_0[0]" in work.decoder(netlist)
net "alu_we_1_0_0_a3[0]" in work.decoder(netlist)
net "alu_func_2_0_0_a3_1[1]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net alu_func_2_0_0_3</font>
20) instance work.decoder(netlist)-alu_func_2_0_0[3], output net "alu_func_2_0_0_3" in work.decoder(netlist)
input nets to instance:
net "alu_func_2_0_0_a3_0[3]" in work.decoder(netlist)
net "alu_func_2_0_0_a3_1[3]" in work.decoder(netlist)
net "alu_func_2_0_0_o3[3]" in work.decoder(netlist)
net "alu_func_2_0_0_a[3]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net alu_func_2_0_0_4</font>
21) instance work.decoder(netlist)-alu_func_2_0_0[4], output net "alu_func_2_0_0_4" in work.decoder(netlist)
input nets to instance:
net "BUS2040_4" in work.decoder(netlist)
net "alu_func_2_0_0_a2_3[1]" in work.decoder(netlist)
net "alu_func_2_0_0_a[4]" in work.decoder(netlist)
net "alu_func_2_0_0_2[4]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net alu_func_2_0_0_1</font>
22) instance work.decoder(netlist)-alu_func_2_0_0[1], output net "alu_func_2_0_0_1" in work.decoder(netlist)
input nets to instance:
net "BUS2040_1" in work.decoder(netlist)
net "alu_func_2_0_0_a2_3[1]" in work.decoder(netlist)
net "alu_func_2_0_0_3[1]" in work.decoder(netlist)
net "alu_func_2_0_0_a3_1[1]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net alu_func_2_0_0_0</font>
23) instance work.decoder(netlist)-alu_func_2_0_0[0], output net "alu_func_2_0_0_0" in work.decoder(netlist)
input nets to instance:
net "alu_func_2_0_0_a[0]" in work.decoder(netlist)
net "alu_func_2_0_0_a3[0]" in work.decoder(netlist)
net "alu_func_2_0_0_2_x[0]" in work.decoder(netlist)
net "alu_func_2_0_0_a3_0[0]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net pc_gen_ctl_2_i_m3_0_0</font>
24) instance work.decoder(netlist)-pc_gen_ctl_2_i_m3_0[0], output net "pc_gen_ctl_2_i_m3_0_0" in work.decoder(netlist)
input nets to instance:
net "zz_ins_i_c_4" in work.decoder(netlist)
net "pc_gen_ctl_2_i_m3_0_a_x[0]" in work.decoder(netlist)
net "muxa_ctl_2_0_0_o2_0[1]" in work.decoder(netlist)
net "pc_gen_ctl_2_i_m3_0_5[0]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net ext_ctl_2_i_m3_0_1</font>
25) instance work.decoder(netlist)-ext_ctl_2_i_m3_0[1], output net "ext_ctl_2_i_m3_0_1" in work.decoder(netlist)
input nets to instance:
net "zz_ins_i_c_29" in work.decoder(netlist)
net "zz_ins_i_c_28" in work.decoder(netlist)
net "alu_func_2_0_0_a2_0_x[0]" in work.decoder(netlist)
net "ext_ctl_2_i_m3_0_a[1]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net ext_ctl_2_i_m3_0_0</font>
26) instance work.decoder(netlist)-ext_ctl_2_i_m3_0[0], output net "ext_ctl_2_i_m3_0_0" in work.decoder(netlist)
input nets to instance:
net "ext_ctl_2_i_m3_0_a_x[0]" in work.decoder(netlist)
net "alu_func_2_0_0_o3[3]" in work.decoder(netlist)
net "ext_ctl_2_i_m3_0_2[0]" in work.decoder(netlist)
net "fsm_dly_2_0_0_a2_x[2]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net pc_gen_ctl_2_i_0_0</font>
27) instance work.decoder(netlist)-pc_gen_ctl_2_i_0[2], output net "pc_gen_ctl_2_i_0_0" in work.decoder(netlist)
input nets to instance:
net "zz_ins_i_c_27" in work.decoder(netlist)
net "pc_gen_ctl_2_i_0_a[2]" in work.decoder(netlist)
net "fsm_dly_2_0_0_a2_x[2]" in work.decoder(netlist)
net "pc_gen_ctl_2_i_0_5[2]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net muxa_ctl_2_0_0_x_0</font>
28) instance work.decoder(netlist)-muxa_ctl_2_0_0_x[1], output net "muxa_ctl_2_0_0_x_0" in work.decoder(netlist)
input nets to instance:
net "zz_ins_i_c_29" in work.decoder(netlist)
net "muxa_ctl_2_0_0_2[1]" in work.decoder(netlist)
End of loops
Writing Verilog Netlist and constraint files
Warning: Found 28 combinational loops!
Each loop is reported with an instance in the loop
and nets connected to that instance.
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net wb_mux_1_0_0_0</font>
1) instance work.decoder(netlist)-wb_mux_1_0_0[0], output net "wb_mux_1_0_0_0" in work.decoder(netlist)
input nets to instance:
net "alu_func_2_0_0_a2_0[1]" in work.decoder(netlist)
net "BUS2118_0" in work.decoder(netlist)
net "wb_mux_1_0_0_a3[0]" in work.decoder(netlist)
net "fsm_dly_2_0_0_o2_x[2]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net wb_we_1_0_0_0</font>
2) instance work.decoder(netlist)-wb_we_1_0_0[0], output net "wb_we_1_0_0_0" in work.decoder(netlist)
input nets to instance:
net "BUS2126_0" in work.decoder(netlist)
net "alu_func_2_0_0_a2_0[1]" in work.decoder(netlist)
net "fsm_dly_2_0_0_o2_x[2]" in work.decoder(netlist)
net "wb_we_1_0_0_a[0]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net muxa_ctl_2_0_0_0</font>
3) instance work.decoder(netlist)-muxa_ctl_2_0_0[0], output net "muxa_ctl_2_0_0_0" in work.decoder(netlist)
input nets to instance:
net "alu_func_2_0_0_a2_0[1]" in work.decoder(netlist)
net "alu_func_2_0_0_o2_x[3]" in work.decoder(netlist)
net "ext_ctl_2_0_0_a2_2_x[2]" in work.decoder(netlist)
net "muxa_ctl_2_0_0_a[0]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net rd_sel_2_0_0_1</font>
4) instance work.decoder(netlist)-rd_sel_2_0_0[1], output net "rd_sel_2_0_0_1" in work.decoder(netlist)
input nets to instance:
net "BUS2110_1" in work.decoder(netlist)
net "zz_ins_i_c_31" in work.decoder(netlist)
net "rd_sel_2_0_0_0[1]" in work.decoder(netlist)
net "rd_sel_2_0_0_a[1]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net rd_sel_2_0_0_0</font>
5) instance work.decoder(netlist)-rd_sel_2_0_0[0], output net "rd_sel_2_0_0_0" in work.decoder(netlist)
input nets to instance:
net "BUS2110_0" in work.decoder(netlist)
net "alu_func_2_0_0_a2_3[1]" in work.decoder(netlist)
net "rd_sel_2_0_0_a[0]" in work.decoder(netlist)
net "alu_func_2_0_0_a3_1[1]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net dmem_ctl_2_0_0_3</font>
6) instance work.decoder(netlist)-dmem_ctl_2_0_0[3], output net "dmem_ctl_2_0_0_3" in work.decoder(netlist)
input nets to instance:
net "BUS2064_3" in work.decoder(netlist)
net "alu_func_2_0_0_a2_0[1]" in work.decoder(netlist)
net "fsm_dly_2_0_0_o2_x[2]" in work.decoder(netlist)
net "dmem_ctl_2_0_0_a[3]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net dmem_ctl_2_0_0_2</font>
7) instance work.decoder(netlist)-dmem_ctl_2_0_0[2], output net "dmem_ctl_2_0_0_2" in work.decoder(netlist)
input nets to instance:
net "zz_ins_i_c_29" in work.decoder(netlist)
net "zz_ins_i_c_30" in work.decoder(netlist)
net "dmem_ctl_2_0_0_a3[2]" in work.decoder(netlist)
net "dmem_ctl_2_0_0_a[2]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net dmem_ctl_2_0_0_0</font>
8) instance work.decoder(netlist)-dmem_ctl_2_0_0[0], output net "dmem_ctl_2_0_0_0" in work.decoder(netlist)
input nets to instance:
net "alu_func_2_0_0_a2_0[1]" in work.decoder(netlist)
net "BUS2064_0" in work.decoder(netlist)
net "fsm_dly_2_0_0_o2_x[2]" in work.decoder(netlist)
net "alu_func_2_0_0_a3_1_x[4]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net dmem_ctl_2_0_0_1</font>
9) instance work.decoder(netlist)-dmem_ctl_2_0_0[1], output net "dmem_ctl_2_0_0_1" in work.decoder(netlist)
input nets to instance:
net "BUS2064_1" in work.decoder(netlist)
net "alu_func_2_0_0_a2_0[1]" in work.decoder(netlist)
net "dmem_ctl_2_0_0_a_x[1]" in work.decoder(netlist)
net "dmem_ctl_2_0_0_1[1]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net pc_gen_ctl_2_0_0_0</font>
10) instance work.decoder(netlist)-pc_gen_ctl_2_0_0[1], output net "pc_gen_ctl_2_0_0_0" in work.decoder(netlist)
input nets to instance:
net "pc_gen_ctl_2_0_0_a2_x[1]" in work.decoder(netlist)
net "alu_func_2_0_0_a2_3_x[0]" in work.decoder(netlist)
net "pc_gen_ctl_2_0_0_a[1]" in work.decoder(netlist)
net "alu_func_2_0_0_a2_2_x[0]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net muxb_ctl_2_0_0_1</font>
11) instance work.decoder(netlist)-muxb_ctl_2_0_0[1], output net "muxb_ctl_2_0_0_1" in work.decoder(netlist)
input nets to instance:
net "zz_ins_i_c_29" in work.decoder(netlist)
net "zz_ins_i_c_30" in work.decoder(netlist)
net "muxb_ctl_2_0_0_0[1]" in work.decoder(netlist)
net "muxb_ctl_2_0_0_a[1]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net muxb_ctl_2_0_0_0</font>
12) instance work.decoder(netlist)-muxb_ctl_2_0_0[0], output net "muxb_ctl_2_0_0_0" in work.decoder(netlist)
input nets to instance:
net "zz_ins_i_c_4" in work.decoder(netlist)
net "muxa_ctl_2_0_0_a3_1[0]" in work.decoder(netlist)
net "muxb_ctl_2_0_0_a3_0_0_x[0]" in work.decoder(netlist)
net "muxb_ctl_2_0_0_a[0]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net fsm_dly_2_0_0_0</font>
13) instance work.decoder(netlist)-fsm_dly_2_0_0[0], output net "fsm_dly_2_0_0_0" in work.decoder(netlist)
input nets to instance:
net "BUS197_0" in work.decoder(netlist)
net "ext_ctl_2_0_0_a3_1_0[2]" in work.decoder(netlist)
net "ext_ctl_2_0_0_o3[2]" in work.decoder(netlist)
net "fsm_dly_2_0_0_a[0]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net ext_ctl_2_0_0_0</font>
14) instance work.decoder(netlist)-ext_ctl_2_0_0[2], output net "ext_ctl_2_0_0_0" in work.decoder(netlist)
input nets to instance:
net "BUS2072_2" in work.decoder(netlist)
net "ext_ctl_2_0_0_a3_1_0[2]" in work.decoder(netlist)
net "ext_ctl_2_0_0_a[2]" in work.decoder(netlist)
net "ext_ctl_2_0_0_o3[2]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net alu_func_2_i_m3_0_0</font>
15) instance work.decoder(netlist)-alu_func_2_i_m3_0[2], output net "alu_func_2_i_m3_0_0" in work.decoder(netlist)
input nets to instance:
net "zz_ins_i_c_3" in work.decoder(netlist)
net "zz_ins_i_c_28" in work.decoder(netlist)
net "alu_func_2_i_m3_0_a[2]" in work.decoder(netlist)
net "alu_func_2_i_m3_0_5[2]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net cmp_ctl_2_0_0_0</font>
16) instance work.decoder(netlist)-cmp_ctl_2_0_0[0], output net "cmp_ctl_2_0_0_0" in work.decoder(netlist)
input nets to instance:
net "alu_func_2_0_0_a2_0[1]" in work.decoder(netlist)
net "cmp_ctl_2_0_0_a2_1[0]" in work.decoder(netlist)
net "BUS2056_0" in work.decoder(netlist)
net "cmp_ctl_2_0_0_1[0]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net cmp_ctl_2_0_0_2</font>
17) instance work.decoder(netlist)-cmp_ctl_2_0_0[2], output net "cmp_ctl_2_0_0_2" in work.decoder(netlist)
input nets to instance:
net "alu_func_2_0_0_a2_0[1]" in work.decoder(netlist)
net "cmp_ctl_2_0_0_a2_x[0]" in work.decoder(netlist)
net "alu_func_2_0_0_a2_0_x[0]" in work.decoder(netlist)
net "cmp_ctl_2_0_0_a[2]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net cmp_ctl_2_0_0_1</font>
18) instance work.decoder(netlist)-cmp_ctl_2_0_0[1], output net "cmp_ctl_2_0_0_1" in work.decoder(netlist)
input nets to instance:
net "BUS2056_1" in work.decoder(netlist)
net "cmp_ctl_2_0_0_a2_0[0]" in work.decoder(netlist)
net "alu_func_2_0_0_a2_0[1]" in work.decoder(netlist)
net "cmp_ctl_2_0_0_a[1]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net alu_we_1_0_0_0</font>
19) instance work.decoder(netlist)-alu_we_1_0_0[0], output net "alu_we_1_0_0_0" in work.decoder(netlist)
input nets to instance:
net "zz_ins_i_c_29" in work.decoder(netlist)
net "alu_we_1_0_0_0[0]" in work.decoder(netlist)
net "alu_we_1_0_0_a3[0]" in work.decoder(netlist)
net "alu_func_2_0_0_a3_1[1]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net alu_func_2_0_0_3</font>
20) instance work.decoder(netlist)-alu_func_2_0_0[3], output net "alu_func_2_0_0_3" in work.decoder(netlist)
input nets to instance:
net "alu_func_2_0_0_a3_0[3]" in work.decoder(netlist)
net "alu_func_2_0_0_a3_1[3]" in work.decoder(netlist)
net "alu_func_2_0_0_o3[3]" in work.decoder(netlist)
net "alu_func_2_0_0_a[3]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net alu_func_2_0_0_4</font>
21) instance work.decoder(netlist)-alu_func_2_0_0[4], output net "alu_func_2_0_0_4" in work.decoder(netlist)
input nets to instance:
net "BUS2040_4" in work.decoder(netlist)
net "alu_func_2_0_0_a2_3[1]" in work.decoder(netlist)
net "alu_func_2_0_0_a[4]" in work.decoder(netlist)
net "alu_func_2_0_0_2[4]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net alu_func_2_0_0_1</font>
22) instance work.decoder(netlist)-alu_func_2_0_0[1], output net "alu_func_2_0_0_1" in work.decoder(netlist)
input nets to instance:
net "BUS2040_1" in work.decoder(netlist)
net "alu_func_2_0_0_a2_3[1]" in work.decoder(netlist)
net "alu_func_2_0_0_3[1]" in work.decoder(netlist)
net "alu_func_2_0_0_a3_1[1]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net alu_func_2_0_0_0</font>
23) instance work.decoder(netlist)-alu_func_2_0_0[0], output net "alu_func_2_0_0_0" in work.decoder(netlist)
input nets to instance:
net "alu_func_2_0_0_a[0]" in work.decoder(netlist)
net "alu_func_2_0_0_a3[0]" in work.decoder(netlist)
net "alu_func_2_0_0_2_x[0]" in work.decoder(netlist)
net "alu_func_2_0_0_a3_0[0]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net pc_gen_ctl_2_i_m3_0_0</font>
24) instance work.decoder(netlist)-pc_gen_ctl_2_i_m3_0[0], output net "pc_gen_ctl_2_i_m3_0_0" in work.decoder(netlist)
input nets to instance:
net "zz_ins_i_c_4" in work.decoder(netlist)
net "pc_gen_ctl_2_i_m3_0_a_x[0]" in work.decoder(netlist)
net "muxa_ctl_2_0_0_o2_0[1]" in work.decoder(netlist)
net "pc_gen_ctl_2_i_m3_0_5[0]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net ext_ctl_2_i_m3_0_1</font>
25) instance work.decoder(netlist)-ext_ctl_2_i_m3_0[1], output net "ext_ctl_2_i_m3_0_1" in work.decoder(netlist)
input nets to instance:
net "zz_ins_i_c_29" in work.decoder(netlist)
net "zz_ins_i_c_28" in work.decoder(netlist)
net "alu_func_2_0_0_a2_0_x[0]" in work.decoder(netlist)
net "ext_ctl_2_i_m3_0_a[1]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net ext_ctl_2_i_m3_0_0</font>
26) instance work.decoder(netlist)-ext_ctl_2_i_m3_0[0], output net "ext_ctl_2_i_m3_0_0" in work.decoder(netlist)
input nets to instance:
net "ext_ctl_2_i_m3_0_a_x[0]" in work.decoder(netlist)
net "alu_func_2_0_0_o3[3]" in work.decoder(netlist)
net "ext_ctl_2_i_m3_0_2[0]" in work.decoder(netlist)
net "fsm_dly_2_0_0_a2_x[2]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net pc_gen_ctl_2_i_0_0</font>
27) instance work.decoder(netlist)-pc_gen_ctl_2_i_0[2], output net "pc_gen_ctl_2_i_0_0" in work.decoder(netlist)
input nets to instance:
net "zz_ins_i_c_27" in work.decoder(netlist)
net "pc_gen_ctl_2_i_0_a[2]" in work.decoder(netlist)
net "fsm_dly_2_0_0_a2_x[2]" in work.decoder(netlist)
net "pc_gen_ctl_2_i_0_5[2]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827012> | Found combinational loop during mapping at net muxa_ctl_2_0_0_x_0</font>
28) instance work.decoder(netlist)-muxa_ctl_2_0_0_x[1], output net "muxa_ctl_2_0_0_x_0" in work.decoder(netlist)
input nets to instance:
net "zz_ins_i_c_29" in work.decoder(netlist)
net "muxa_ctl_2_0_0_2[1]" in work.decoder(netlist)
End of loops
Writing .vqm output for Quartus
Writing Cross reference file for Quartus to E:\mips789\mips789\synplify_prj\rev_1\mips_sys.xrf
Warning: Found 28 combinational loops!
Each loop is reported with an instance in the loop
and nets connected to that instance.
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827112> | Found combinational loop during mapping at net wb_mux_1_0_0_0</font>
1) instance work.decoder(netlist)-wb_mux_1_0_0[0], output net "wb_mux_1_0_0_0" in work.decoder(netlist)
input nets to instance:
net "alu_func_2_0_0_a2_0[1]" in work.decoder(netlist)
net "BUS2118_0" in work.decoder(netlist)
net "wb_mux_1_0_0_a3[0]" in work.decoder(netlist)
net "fsm_dly_2_0_0_o2_x[2]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827112> | Found combinational loop during mapping at net wb_we_1_0_0_0</font>
2) instance work.decoder(netlist)-wb_we_1_0_0[0], output net "wb_we_1_0_0_0" in work.decoder(netlist)
input nets to instance:
net "BUS2126_0" in work.decoder(netlist)
net "alu_func_2_0_0_a2_0[1]" in work.decoder(netlist)
net "fsm_dly_2_0_0_o2_x[2]" in work.decoder(netlist)
net "wb_we_1_0_0_a[0]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827112> | Found combinational loop during mapping at net muxa_ctl_2_0_0_0</font>
3) instance work.decoder(netlist)-muxa_ctl_2_0_0[0], output net "muxa_ctl_2_0_0_0" in work.decoder(netlist)
input nets to instance:
net "alu_func_2_0_0_a2_0[1]" in work.decoder(netlist)
net "alu_func_2_0_0_o2_x[3]" in work.decoder(netlist)
net "ext_ctl_2_0_0_a2_2_x[2]" in work.decoder(netlist)
net "muxa_ctl_2_0_0_a[0]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827112> | Found combinational loop during mapping at net rd_sel_2_0_0_1</font>
4) instance work.decoder(netlist)-rd_sel_2_0_0[1], output net "rd_sel_2_0_0_1" in work.decoder(netlist)
input nets to instance:
net "BUS2110_1" in work.decoder(netlist)
net "zz_ins_i_c_31" in work.decoder(netlist)
net "rd_sel_2_0_0_0[1]" in work.decoder(netlist)
net "rd_sel_2_0_0_a[1]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827112> | Found combinational loop during mapping at net rd_sel_2_0_0_0</font>
5) instance work.decoder(netlist)-rd_sel_2_0_0[0], output net "rd_sel_2_0_0_0" in work.decoder(netlist)
input nets to instance:
net "BUS2110_0" in work.decoder(netlist)
net "alu_func_2_0_0_a2_3[1]" in work.decoder(netlist)
net "rd_sel_2_0_0_a[0]" in work.decoder(netlist)
net "alu_func_2_0_0_a3_1[1]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827112> | Found combinational loop during mapping at net dmem_ctl_2_0_0_3</font>
6) instance work.decoder(netlist)-dmem_ctl_2_0_0[3], output net "dmem_ctl_2_0_0_3" in work.decoder(netlist)
input nets to instance:
net "BUS2064_3" in work.decoder(netlist)
net "alu_func_2_0_0_a2_0[1]" in work.decoder(netlist)
net "fsm_dly_2_0_0_o2_x[2]" in work.decoder(netlist)
net "dmem_ctl_2_0_0_a[3]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827112> | Found combinational loop during mapping at net dmem_ctl_2_0_0_2</font>
7) instance work.decoder(netlist)-dmem_ctl_2_0_0[2], output net "dmem_ctl_2_0_0_2" in work.decoder(netlist)
input nets to instance:
net "zz_ins_i_c_29" in work.decoder(netlist)
net "zz_ins_i_c_30" in work.decoder(netlist)
net "dmem_ctl_2_0_0_a3[2]" in work.decoder(netlist)
net "dmem_ctl_2_0_0_a[2]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827112> | Found combinational loop during mapping at net dmem_ctl_2_0_0_0</font>
8) instance work.decoder(netlist)-dmem_ctl_2_0_0[0], output net "dmem_ctl_2_0_0_0" in work.decoder(netlist)
input nets to instance:
net "alu_func_2_0_0_a2_0[1]" in work.decoder(netlist)
net "BUS2064_0" in work.decoder(netlist)
net "fsm_dly_2_0_0_o2_x[2]" in work.decoder(netlist)
net "alu_func_2_0_0_a3_1_x[4]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827112> | Found combinational loop during mapping at net dmem_ctl_2_0_0_1</font>
9) instance work.decoder(netlist)-dmem_ctl_2_0_0[1], output net "dmem_ctl_2_0_0_1" in work.decoder(netlist)
input nets to instance:
net "BUS2064_1" in work.decoder(netlist)
net "alu_func_2_0_0_a2_0[1]" in work.decoder(netlist)
net "dmem_ctl_2_0_0_a_x[1]" in work.decoder(netlist)
net "dmem_ctl_2_0_0_1[1]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827112> | Found combinational loop during mapping at net pc_gen_ctl_2_0_0_0</font>
10) instance work.decoder(netlist)-pc_gen_ctl_2_0_0[1], output net "pc_gen_ctl_2_0_0_0" in work.decoder(netlist)
input nets to instance:
net "pc_gen_ctl_2_0_0_a2_x[1]" in work.decoder(netlist)
net "alu_func_2_0_0_a2_3_x[0]" in work.decoder(netlist)
net "pc_gen_ctl_2_0_0_a[1]" in work.decoder(netlist)
net "alu_func_2_0_0_a2_2_x[0]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827112> | Found combinational loop during mapping at net muxb_ctl_2_0_0_1</font>
11) instance work.decoder(netlist)-muxb_ctl_2_0_0[1], output net "muxb_ctl_2_0_0_1" in work.decoder(netlist)
input nets to instance:
net "zz_ins_i_c_29" in work.decoder(netlist)
net "zz_ins_i_c_30" in work.decoder(netlist)
net "muxb_ctl_2_0_0_0[1]" in work.decoder(netlist)
net "muxb_ctl_2_0_0_a[1]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827112> | Found combinational loop during mapping at net muxb_ctl_2_0_0_0</font>
12) instance work.decoder(netlist)-muxb_ctl_2_0_0[0], output net "muxb_ctl_2_0_0_0" in work.decoder(netlist)
input nets to instance:
net "zz_ins_i_c_4" in work.decoder(netlist)
net "muxa_ctl_2_0_0_a3_1[0]" in work.decoder(netlist)
net "muxb_ctl_2_0_0_a3_0_0_x[0]" in work.decoder(netlist)
net "muxb_ctl_2_0_0_a[0]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827112> | Found combinational loop during mapping at net fsm_dly_2_0_0_0</font>
13) instance work.decoder(netlist)-fsm_dly_2_0_0[0], output net "fsm_dly_2_0_0_0" in work.decoder(netlist)
input nets to instance:
net "BUS197_0" in work.decoder(netlist)
net "ext_ctl_2_0_0_a3_1_0[2]" in work.decoder(netlist)
net "ext_ctl_2_0_0_o3[2]" in work.decoder(netlist)
net "fsm_dly_2_0_0_a[0]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827112> | Found combinational loop during mapping at net ext_ctl_2_0_0_0</font>
14) instance work.decoder(netlist)-ext_ctl_2_0_0[2], output net "ext_ctl_2_0_0_0" in work.decoder(netlist)
input nets to instance:
net "BUS2072_2" in work.decoder(netlist)
net "ext_ctl_2_0_0_a3_1_0[2]" in work.decoder(netlist)
net "ext_ctl_2_0_0_a[2]" in work.decoder(netlist)
net "ext_ctl_2_0_0_o3[2]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827112> | Found combinational loop during mapping at net alu_func_2_i_m3_0_0</font>
15) instance work.decoder(netlist)-alu_func_2_i_m3_0[2], output net "alu_func_2_i_m3_0_0" in work.decoder(netlist)
input nets to instance:
net "zz_ins_i_c_3" in work.decoder(netlist)
net "zz_ins_i_c_28" in work.decoder(netlist)
net "alu_func_2_i_m3_0_a[2]" in work.decoder(netlist)
net "alu_func_2_i_m3_0_5[2]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827112> | Found combinational loop during mapping at net cmp_ctl_2_0_0_0</font>
16) instance work.decoder(netlist)-cmp_ctl_2_0_0[0], output net "cmp_ctl_2_0_0_0" in work.decoder(netlist)
input nets to instance:
net "alu_func_2_0_0_a2_0[1]" in work.decoder(netlist)
net "cmp_ctl_2_0_0_a2_1[0]" in work.decoder(netlist)
net "BUS2056_0" in work.decoder(netlist)
net "cmp_ctl_2_0_0_1[0]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827112> | Found combinational loop during mapping at net cmp_ctl_2_0_0_2</font>
17) instance work.decoder(netlist)-cmp_ctl_2_0_0[2], output net "cmp_ctl_2_0_0_2" in work.decoder(netlist)
input nets to instance:
net "alu_func_2_0_0_a2_0[1]" in work.decoder(netlist)
net "cmp_ctl_2_0_0_a2_x[0]" in work.decoder(netlist)
net "alu_func_2_0_0_a2_0_x[0]" in work.decoder(netlist)
net "cmp_ctl_2_0_0_a[2]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827112> | Found combinational loop during mapping at net cmp_ctl_2_0_0_1</font>
18) instance work.decoder(netlist)-cmp_ctl_2_0_0[1], output net "cmp_ctl_2_0_0_1" in work.decoder(netlist)
input nets to instance:
net "BUS2056_1" in work.decoder(netlist)
net "cmp_ctl_2_0_0_a2_0[0]" in work.decoder(netlist)
net "alu_func_2_0_0_a2_0[1]" in work.decoder(netlist)
net "cmp_ctl_2_0_0_a[1]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827112> | Found combinational loop during mapping at net alu_we_1_0_0_0</font>
19) instance work.decoder(netlist)-alu_we_1_0_0[0], output net "alu_we_1_0_0_0" in work.decoder(netlist)
input nets to instance:
net "zz_ins_i_c_29" in work.decoder(netlist)
net "alu_we_1_0_0_0[0]" in work.decoder(netlist)
net "alu_we_1_0_0_a3[0]" in work.decoder(netlist)
net "alu_func_2_0_0_a3_1[1]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827112> | Found combinational loop during mapping at net alu_func_2_0_0_3</font>
20) instance work.decoder(netlist)-alu_func_2_0_0[3], output net "alu_func_2_0_0_3" in work.decoder(netlist)
input nets to instance:
net "alu_func_2_0_0_a3_0[3]" in work.decoder(netlist)
net "alu_func_2_0_0_a3_1[3]" in work.decoder(netlist)
net "alu_func_2_0_0_o3[3]" in work.decoder(netlist)
net "alu_func_2_0_0_a[3]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827112> | Found combinational loop during mapping at net alu_func_2_0_0_4</font>
21) instance work.decoder(netlist)-alu_func_2_0_0[4], output net "alu_func_2_0_0_4" in work.decoder(netlist)
input nets to instance:
net "BUS2040_4" in work.decoder(netlist)
net "alu_func_2_0_0_a2_3[1]" in work.decoder(netlist)
net "alu_func_2_0_0_a[4]" in work.decoder(netlist)
net "alu_func_2_0_0_2[4]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827112> | Found combinational loop during mapping at net alu_func_2_0_0_1</font>
22) instance work.decoder(netlist)-alu_func_2_0_0[1], output net "alu_func_2_0_0_1" in work.decoder(netlist)
input nets to instance:
net "BUS2040_1" in work.decoder(netlist)
net "alu_func_2_0_0_a2_3[1]" in work.decoder(netlist)
net "alu_func_2_0_0_3[1]" in work.decoder(netlist)
net "alu_func_2_0_0_a3_1[1]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827112> | Found combinational loop during mapping at net alu_func_2_0_0_0</font>
23) instance work.decoder(netlist)-alu_func_2_0_0[0], output net "alu_func_2_0_0_0" in work.decoder(netlist)
input nets to instance:
net "alu_func_2_0_0_a[0]" in work.decoder(netlist)
net "alu_func_2_0_0_a3[0]" in work.decoder(netlist)
net "alu_func_2_0_0_2_x[0]" in work.decoder(netlist)
net "alu_func_2_0_0_a3_0[0]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827112> | Found combinational loop during mapping at net pc_gen_ctl_2_i_m3_0_0</font>
24) instance work.decoder(netlist)-pc_gen_ctl_2_i_m3_0[0], output net "pc_gen_ctl_2_i_m3_0_0" in work.decoder(netlist)
input nets to instance:
net "zz_ins_i_c_4" in work.decoder(netlist)
net "pc_gen_ctl_2_i_m3_0_a_x[0]" in work.decoder(netlist)
net "muxa_ctl_2_0_0_o2_0[1]" in work.decoder(netlist)
net "pc_gen_ctl_2_i_m3_0_5[0]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827112> | Found combinational loop during mapping at net ext_ctl_2_i_m3_0_1</font>
25) instance work.decoder(netlist)-ext_ctl_2_i_m3_0[1], output net "ext_ctl_2_i_m3_0_1" in work.decoder(netlist)
input nets to instance:
net "zz_ins_i_c_29" in work.decoder(netlist)
net "zz_ins_i_c_28" in work.decoder(netlist)
net "alu_func_2_0_0_a2_0_x[0]" in work.decoder(netlist)
net "ext_ctl_2_i_m3_0_a[1]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827112> | Found combinational loop during mapping at net ext_ctl_2_i_m3_0_0</font>
26) instance work.decoder(netlist)-ext_ctl_2_i_m3_0[0], output net "ext_ctl_2_i_m3_0_0" in work.decoder(netlist)
input nets to instance:
net "ext_ctl_2_i_m3_0_a_x[0]" in work.decoder(netlist)
net "alu_func_2_0_0_o3[3]" in work.decoder(netlist)
net "ext_ctl_2_i_m3_0_2[0]" in work.decoder(netlist)
net "fsm_dly_2_0_0_a2_x[2]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827112> | Found combinational loop during mapping at net pc_gen_ctl_2_i_0_0</font>
27) instance work.decoder(netlist)-pc_gen_ctl_2_i_0[2], output net "pc_gen_ctl_2_i_0_0" in work.decoder(netlist)
input nets to instance:
net "zz_ins_i_c_27" in work.decoder(netlist)
net "pc_gen_ctl_2_i_0_a[2]" in work.decoder(netlist)
net "fsm_dly_2_0_0_a2_x[2]" in work.decoder(netlist)
net "pc_gen_ctl_2_i_0_5[2]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223827112> | Found combinational loop during mapping at net muxa_ctl_2_0_0_x_0</font>
28) instance work.decoder(netlist)-muxa_ctl_2_0_0_x[1], output net "muxa_ctl_2_0_0_x_0" in work.decoder(netlist)
input nets to instance:
net "zz_ins_i_c_29" in work.decoder(netlist)
net "muxa_ctl_2_0_0_2[1]" in work.decoder(netlist)
End of loops
Found clock mips_sys|clk with period 20.00ns
<font color=#A52A2A>@W:<a href="@W:MT253:@XP_HELP">MT253</a> : <a href="e:\mips789\mips789\rtl\verilog\altera\fifo512_cyclone.v:66:8:66:24:@W:MT253:@XP_MSG">fifo512_cyclone.v(66)</a><!@TM:1223827112> | Blackbox scfifo_Z1 is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) </font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:161:4:161:8:@W::@XP_MSG">mem_module.v(161)</a><!@TM:1223827112> | Net un1_byte_addr_2 appears to be a clock source which was not identified. Assuming default frequency. </font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\ctl_fsm.v:58:8:58:12:@W::@XP_MSG">ctl_fsm.v(58)</a><!@TM:1223827112> | Net un1_rst_2 appears to be a clock source which was not identified. Assuming default frequency. </font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:1:1:961:16:@W::@XP_MSG">decode_pipe.v(1)</a><!@TM:1223827112> | Net un1_muxa_ctl370_x appears to be a clock source which was not identified. Assuming default frequency. </font>
<a name=timingReport18>##### START OF TIMING REPORT #####[
# Timing Report written on Sun Oct 12 23:58:31 2008
#
Top view: mips_sys
Requested Frequency: 50.0 MHz
Wire load mode: top
Paths requested: 5
Constraint File(s): E:\mips789\mips789\synplify_prj\rev_1\mips_sys_fsm.sdc
@N:<a href="@N:MT195:@XP_HELP">MT195</a> : <!@TM:1223827112> | This timing report estimates place and route data. Please look at the place and route timing report for final timing..
@N:<a href="@N:MT197:@XP_HELP">MT197</a> : <!@TM:1223827112> | Clock constraints cover only FF-to-FF paths associated with the clock..
<a name=performanceSummary19>Performance Summary
*******************
Worst slack in design: 6.086
Requested Estimated Requested Estimated Clock Clock
Starting Clock Frequency Frequency Period Period Slack Type Group
----------------------------------------------------------------------------------------------------------------------
mips_sys|clk 50.0 MHz 71.9 MHz 20.000 13.914 6.086 inferred Inferred_clkgroup_0
System 50.0 MHz 481.8 MHz 20.000 2.075 17.925 system default_clkgroup
======================================================================================================================
<a name=clockRelationships20>Clock Relationships
*******************
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
------------------------------------------------------------------------------------------------------------------
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
------------------------------------------------------------------------------------------------------------------
mips_sys|clk mips_sys|clk | 20.000 6.086 | No paths - | No paths - | No paths -
==================================================================================================================
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
<a name=interfaceInfo21>Interface Information
*********************
No IO constraint found
====================================
<a name=clockReport22>Detailed Report for Clock: mips_sys|clk
====================================
<a name=startingSlack23>Starting Points with Worst Slack
********************************
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
----------------------------------------------------------------------------------------------------------------------------------
mips_core.rnd_pass1.r5_o[1] mips_sys|clk cyclone_lcell_ff regout r5_o_1 0.173 6.086
mips_core.rnd_pass1.r5_o[4] mips_sys|clk cyclone_lcell_ff regout r5_o_4 0.173 6.200
mips_core.iRF_stage.ins_reg.r32_o[20] mips_sys|clk cyclone_lcell_ff regout r32_o_20 0.173 6.353
mips_core.rnd_pass1.r5_o[3] mips_sys|clk cyclone_lcell_ff regout r5_o_3 0.173 6.419
mips_core.iRF_stage.ins_reg.r32_o[22] mips_sys|clk cyclone_lcell_ff regout r32_o_22 0.173 6.458
mips_core.iRF_stage.ins_reg.r32_o[19] mips_sys|clk cyclone_lcell_ff regout r32_o_19 0.173 6.467
mips_core.rnd_pass1.r5_o[0] mips_sys|clk cyclone_lcell_ff regout r5_o_0 0.173 6.533
mips_core.iRF_stage.ins_reg.r32_o[17] mips_sys|clk cyclone_lcell_ff regout r32_o_17 0.173 6.582
mips_core.decoder_pipe.pipereg.U22.wb_we_o[0] mips_sys|clk cyclone_lcell_ff regout wb_we_o_0 0.173 6.582
mips_core.iRF_stage.ins_reg.r32_o[23] mips_sys|clk cyclone_lcell_ff regout r32_o_23 0.173 6.595
==================================================================================================================================
<a name=endingSlack24>Ending Points with Worst Slack
******************************
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
------------------------------------------------------------------------------------------------------------------
mips_core.rt_reg.r32_o[13] mips_sys|clk cyclone_lcell_ff datab dout_iv_1_13 12.155 6.086
mips_core.pc.r32_o[31] mips_sys|clk cyclone_lcell_ff datad un1_pc_add31 19.971 6.086
mips_core.pc.r32_o[30] mips_sys|clk cyclone_lcell_ff datac un1_pc_add30 19.971 6.113
mips_core.pc.r32_o[29] mips_sys|clk cyclone_lcell_ff datac un1_pc_add29 19.971 6.140
mips_core.pc.r32_o[28] mips_sys|clk cyclone_lcell_ff datac un1_pc_add28 19.971 6.167
mips_core.rs_reg.r32_o[14] mips_sys|clk cyclone_lcell_ff datab dout_iv_1_14 12.157 6.180
mips_core.rt_reg.r32_o[30] mips_sys|clk cyclone_lcell_ff datab dout_iv_1_30 12.259 6.190
mips_core.pc.r32_o[27] mips_sys|clk cyclone_lcell_ff datac un1_pc_add27 19.971 6.194
mips_core.rt_reg.r32_o[1] mips_sys|clk cyclone_lcell_ff datab dout_iv_1_1 12.269 6.200
mips_core.rt_reg.r32_o[29] mips_sys|clk cyclone_lcell_ff datab dout_iv_1_29 12.269 6.200
==================================================================================================================
<a name=worstPaths25>Worst Path Information
<a href="E:\mips789\mips789\synplify_prj\rev_1\mips_sys.srr:fp:530391:549795:@XP_NAMES">View Worst Path in Analyst</a>
***********************
Path information for path number 1:
Requested Period: 20.000
- Setup time: 0.029
= Required time: 19.971
- Propagation time: 13.885
= Slack (critical) : 6.086
Number of logic level(s): 48
Starting point: mips_core.rnd_pass1.r5_o[1] / regout
Ending point: mips_core.pc.r32_o[31] / datad
The start point is clocked by mips_sys|clk [rising] on pin clk
The end point is clocked by mips_sys|clk [rising] on pin clk
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
----------------------------------------------------------------------------------------------------------------------------------
mips_core.rnd_pass1.r5_o[1] cyclone_lcell_ff regout Out 0.173 0.173 -
r5_o_1 Net - - 0.635 - 6
mips_core.iforward.fw_alu_rs.un14_mux_fw_a cyclone_lcell dataa In - 0.808 -
mips_core.iforward.fw_alu_rs.un14_mux_fw_a cyclone_lcell combout Out 0.454 1.262 -
un14_mux_fw_a Net - - 0.245 - 1
mips_core.iforward.fw_alu_rs.un14_mux_fw cyclone_lcell datad In - 1.508 -
mips_core.iforward.fw_alu_rs.un14_mux_fw cyclone_lcell combout Out 0.088 1.596 -
un14_mux_fw Net - - 0.545 - 5
mips_core.iforward.fw_cmp_rt.mux_fw_1 cyclone_lcell datad In - 2.141 -
mips_core.iforward.fw_cmp_rt.mux_fw_1 cyclone_lcell combout Out 0.088 2.229 -
mux_fw_1 Net - - 1.253 - 34
mips_core.iforward.fw_cmp_rt.un32_mux_fw cyclone_lcell datad In - 3.482 -
mips_core.iforward.fw_cmp_rt.un32_mux_fw cyclone_lcell combout Out 0.088 3.570 -
un32_mux_fw Net - - 0.274 - 2
mips_core.iRF_stage.reg_bank.N_16_i_0_s2 cyclone_lcell datad In - 3.844 -
mips_core.iRF_stage.reg_bank.N_16_i_0_s2 cyclone_lcell combout Out 0.088 3.932 -
N_16_i_0_s2 Net - - 1.218 - 32
mips_core.iRF_stage.rf_fwd_rt.dout_iv_1_a[13] cyclone_lcell datad In - 5.150 -
mips_core.iRF_stage.rf_fwd_rt.dout_iv_1_a[13] cyclone_lcell combout Out 0.088 5.238 -
dout_iv_1_a[13] Net - - 0.245 - 1
mips_core.iRF_stage.rf_fwd_rt.dout_iv_1[13] cyclone_lcell datab In - 5.484 -
mips_core.iRF_stage.rf_fwd_rt.dout_iv_1[13] cyclone_lcell combout Out 0.340 5.824 -
dout_iv_1_13 Net - - 0.245 - 1
mips_core.rt_reg.r32_o[13] cyclone_lcell_ff datab In - 6.069 -
mips_core.rt_reg.r32_o[13] cyclone_lcell_ff combout Out 0.340 6.409 -
dout_iv_13 Net - - 0.245 - 1
mips_core.iRF_stage.i_cmp.res_2_NE_7_0_a cyclone_lcell dataa In - 6.654 -
mips_core.iRF_stage.i_cmp.res_2_NE_7_0_a cyclone_lcell combout Out 0.454 7.108 -
res_2_NE_7_0_a Net - - 0.245 - 1
mips_core.iRF_stage.i_cmp.res_2_NE_7_0 cyclone_lcell datad In - 7.354 -
mips_core.iRF_stage.i_cmp.res_2_NE_7_0 cyclone_lcell combout Out 0.088 7.442 -
res_2_NE_7_0 Net - - 0.245 - 1
mips_core.iRF_stage.i_cmp.res_2_NE_12_0 cyclone_lcell datac In - 7.687 -
mips_core.iRF_stage.i_cmp.res_2_NE_12_0 cyclone_lcell combout Out 0.225 7.912 -
res_2_NE_12_0 Net - - 0.245 - 1
mips_core.iRF_stage.i_cmp.res_2_NE cyclone_lcell dataa In - 8.157 -
mips_core.iRF_stage.i_cmp.res_2_NE cyclone_lcell combout Out 0.454 8.611 -
res_2_NE Net - - 0.274 - 2
mips_core.iRF_stage.i_cmp.res_3_0 cyclone_lcell datad In - 8.885 -
mips_core.iRF_stage.i_cmp.res_3_0 cyclone_lcell combout Out 0.088 8.973 -
res_3_0 Net - - 0.245 - 1
mips_core.iRF_stage.i_cmp.res_7_0 cyclone_lcell datab In - 9.219 -
mips_core.iRF_stage.i_cmp.res_7_0 cyclone_lcell combout Out 0.340 9.559 -
res_7_0 Net - - 0.274 - 2
mips_core.iRF_stage.i_pc_gen.un1_pc_prectl_1_0_a3[0] cyclone_lcell datad In - 9.833 -
mips_core.iRF_stage.i_pc_gen.un1_pc_prectl_1_0_a3[0] cyclone_lcell combout Out 0.088 9.921 -
un1_pc_prectl_1_0_a3[0] Net - - 1.201 - 31
mips_core.iRF_stage.i_pc_gen.un1_pc_prectl_1_0_a4[0] cyclone_lcell datab In - 11.121 -
mips_core.iRF_stage.i_pc_gen.un1_pc_prectl_1_0_a4[0] cyclone_lcell combout Out 0.340 11.461 -
un1_pc_prectl_1_0_a4[0] Net - - 0.245 - 1
mips_core.iRF_stage.i_pc_gen.un1_pc_add0 cyclone_lcell datab In - 11.707 -
mips_core.iRF_stage.i_pc_gen.un1_pc_add0 cyclone_lcell cout Out 0.645 12.352 -
un1_pc_carry_0 Net - - 0.000 - 1
mips_core.iRF_stage.i_pc_gen.un1_pc_add1 cyclone_lcell cin In - 12.352 -
mips_core.iRF_stage.i_pc_gen.un1_pc_add1 cyclone_lcell cout Out 0.027 12.379 -
un1_pc_carry_1 Net - - 0.000 - 1
mips_core.iRF_stage.i_pc_gen.un1_pc_add2 cyclone_lcell cin In - 12.379 -
mips_core.iRF_stage.i_pc_gen.un1_pc_add2 cyclone_lcell cout Out 0.027 12.406 -
un1_pc_carry_2 Net - - 0.000 - 1
mips_core.iRF_stage.i_pc_gen.un1_pc_add3 cyclone_lcell cin In - 12.406 -
mips_core.iRF_stage.i_pc_gen.un1_pc_add3 cyclone_lcell cout Out 0.027 12.433 -
un1_pc_carry_3 Net - - 0.000 - 1
mips_core.iRF_stage.i_pc_gen.un1_pc_add4 cyclone_lcell cin In - 12.433 -
mips_core.iRF_stage.i_pc_gen.un1_pc_add4 cyclone_lcell cout Out 0.027 12.460 -
un1_pc_carry_4 Net - - 0.000 - 1
mips_core.iRF_stage.i_pc_gen.un1_pc_add5 cyclone_lcell cin In - 12.460 -
mips_core.iRF_stage.i_pc_gen.un1_pc_add5 cyclone_lcell cout Out 0.027 12.487 -
un1_pc_carry_5 Net - - 0.000 - 1
mips_core.iRF_stage.i_pc_gen.un1_pc_add6 cyclone_lcell cin In - 12.487 -
mips_core.iRF_stage.i_pc_gen.un1_pc_add6 cyclone_lcell cout Out 0.027 12.514 -
un1_pc_carry_6 Net - - 0.000 - 1
mips_core.iRF_stage.i_pc_gen.un1_pc_add7 cyclone_lcell cin In - 12.514 -
mips_core.iRF_stage.i_pc_gen.un1_pc_add7 cyclone_lcell cout Out 0.027 12.541 -
un1_pc_carry_7 Net - - 0.000 - 1
mips_core.iRF_stage.i_pc_gen.un1_pc_add8 cyclone_lcell cin In - 12.541 -
mips_core.iRF_stage.i_pc_gen.un1_pc_add8 cyclone_lcell cout Out 0.027 12.568 -
un1_pc_carry_8 Net - - 0.000 - 1
mips_core.iRF_stage.i_pc_gen.un1_pc_add9 cyclone_lcell cin In - 12.568 -
mips_core.iRF_stage.i_pc_gen.un1_pc_add9 cyclone_lcell cout Out 0.027 12.595 -
un1_pc_carry_9 Net - - 0.000 - 1
mips_core.iRF_stage.i_pc_gen.un1_pc_add10 cyclone_lcell cin In - 12.595 -
mips_core.iRF_stage.i_pc_gen.un1_pc_add10 cyclone_lcell cout Out 0.027 12.622 -
un1_pc_carry_10 Net - - 0.000 - 1
mips_core.iRF_stage.i_pc_gen.un1_pc_add11 cyclone_lcell cin In - 12.622 -
mips_core.iRF_stage.i_pc_gen.un1_pc_add11 cyclone_lcell cout Out 0.027 12.649 -
un1_pc_carry_11 Net - - 0.000 - 1
mips_core.iRF_stage.i_pc_gen.un1_pc_add12 cyclone_lcell cin In - 12.649 -
mips_core.iRF_stage.i_pc_gen.un1_pc_add12 cyclone_lcell cout Out 0.027 12.676 -
un1_pc_carry_12 Net - - 0.000 - 1
mips_core.iRF_stage.i_pc_gen.un1_pc_add13 cyclone_lcell cin In - 12.676 -
mips_core.iRF_stage.i_pc_gen.un1_pc_add13 cyclone_lcell cout Out 0.027 12.703 -
un1_pc_carry_13 Net - - 0.000 - 1
mips_core.iRF_stage.i_pc_gen.un1_pc_add14 cyclone_lcell cin In - 12.703 -
mips_core.iRF_stage.i_pc_gen.un1_pc_add14 cyclone_lcell cout Out 0.027 12.730 -
un1_pc_carry_14 Net - - 0.000 - 1
mips_core.iRF_stage.i_pc_gen.un1_pc_add15 cyclone_lcell cin In - 12.730 -
mips_core.iRF_stage.i_pc_gen.un1_pc_add15 cyclone_lcell cout Out 0.027 12.757 -
un1_pc_carry_15 Net - - 0.000 - 1
mips_core.iRF_stage.i_pc_gen.un1_pc_add16 cyclone_lcell cin In - 12.757 -
mips_core.iRF_stage.i_pc_gen.un1_pc_add16 cyclone_lcell cout Out 0.027 12.784 -
un1_pc_carry_16 Net - - 0.000 - 1
mips_core.iRF_stage.i_pc_gen.un1_pc_add17 cyclone_lcell cin In - 12.784 -
mips_core.iRF_stage.i_pc_gen.un1_pc_add17 cyclone_lcell cout Out 0.027 12.811 -
un1_pc_carry_17 Net - - 0.000 - 1
mips_core.iRF_stage.i_pc_gen.un1_pc_add18 cyclone_lcell cin In - 12.811 -
mips_core.iRF_stage.i_pc_gen.un1_pc_add18 cyclone_lcell cout Out 0.027 12.838 -
un1_pc_carry_18 Net - - 0.000 - 1
mips_core.iRF_stage.i_pc_gen.un1_pc_add19 cyclone_lcell cin In - 12.838 -
mips_core.iRF_stage.i_pc_gen.un1_pc_add19 cyclone_lcell cout Out 0.027 12.865 -
un1_pc_carry_19 Net - - 0.000 - 1
mips_core.iRF_stage.i_pc_gen.un1_pc_add20 cyclone_lcell cin In - 12.865 -
mips_core.iRF_stage.i_pc_gen.un1_pc_add20 cyclone_lcell cout Out 0.027 12.892 -
un1_pc_carry_20 Net - - 0.000 - 1
mips_core.iRF_stage.i_pc_gen.un1_pc_add21 cyclone_lcell cin In - 12.892 -
mips_core.iRF_stage.i_pc_gen.un1_pc_add21 cyclone_lcell cout Out 0.027 12.919 -
un1_pc_carry_21 Net - - 0.000 - 1
mips_core.iRF_stage.i_pc_gen.un1_pc_add22 cyclone_lcell cin In - 12.919 -
mips_core.iRF_stage.i_pc_gen.un1_pc_add22 cyclone_lcell cout Out 0.027 12.946 -
un1_pc_carry_22 Net - - 0.000 - 1
mips_core.iRF_stage.i_pc_gen.un1_pc_add23 cyclone_lcell cin In - 12.946 -
mips_core.iRF_stage.i_pc_gen.un1_pc_add23 cyclone_lcell cout Out 0.027 12.973 -
un1_pc_carry_23 Net - - 0.000 - 1
mips_core.iRF_stage.i_pc_gen.un1_pc_add24 cyclone_lcell cin In - 12.973 -
mips_core.iRF_stage.i_pc_gen.un1_pc_add24 cyclone_lcell cout Out 0.027 13.000 -
un1_pc_carry_24 Net - - 0.000 - 1
mips_core.iRF_stage.i_pc_gen.un1_pc_add25 cyclone_lcell cin In - 13.000 -
mips_core.iRF_stage.i_pc_gen.un1_pc_add25 cyclone_lcell cout Out 0.027 13.027 -
un1_pc_carry_25 Net - - 0.000 - 1
mips_core.iRF_stage.i_pc_gen.un1_pc_add26 cyclone_lcell cin In - 13.027 -
mips_core.iRF_stage.i_pc_gen.un1_pc_add26 cyclone_lcell cout Out 0.027 13.054 -
un1_pc_carry_26 Net - - 0.000 - 1
mips_core.iRF_stage.i_pc_gen.un1_pc_add27 cyclone_lcell cin In - 13.054 -
mips_core.iRF_stage.i_pc_gen.un1_pc_add27 cyclone_lcell cout Out 0.027 13.081 -
un1_pc_carry_27 Net - - 0.000 - 1
mips_core.iRF_stage.i_pc_gen.un1_pc_add28 cyclone_lcell cin In - 13.081 -
mips_core.iRF_stage.i_pc_gen.un1_pc_add28 cyclone_lcell cout Out 0.027 13.108 -
un1_pc_carry_28 Net - - 0.000 - 1
mips_core.iRF_stage.i_pc_gen.un1_pc_add29 cyclone_lcell cin In - 13.108 -
mips_core.iRF_stage.i_pc_gen.un1_pc_add29 cyclone_lcell cout Out 0.027 13.135 -
un1_pc_carry_29 Net - - 0.000 - 1
mips_core.iRF_stage.i_pc_gen.un1_pc_add30 cyclone_lcell cin In - 13.135 -
mips_core.iRF_stage.i_pc_gen.un1_pc_add30 cyclone_lcell cout Out 0.027 13.162 -
un1_pc_carry_30 Net - - 0.000 - 1
mips_core.iRF_stage.i_pc_gen.un1_pc_add31 cyclone_lcell cin In - 13.162 -
mips_core.iRF_stage.i_pc_gen.un1_pc_add31 cyclone_lcell combout Out 0.478 13.640 -
un1_pc_add31 Net - - 0.245 - 1
mips_core.pc.r32_o[31] cyclone_lcell_ff datad In - 13.885 -
==================================================================================================================================
Total path delay (propagation time + setup) of 13.914 is 5.786(41.6%) logic and 8.128(58.4%) route.
====================================
<a name=clockReport26>Detailed Report for Clock: System
====================================
<a name=startingSlack27>Starting Points with Worst Slack
********************************
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
------------------------------------------------------------------------------------------------------------------------------
imips_dvc.iuart0.uart_txd.fifo.scfifo_component System scfifo_Z1 empty empty 0.461 17.925
mips_core.decoder_pipe.idecoder.fsm_dly_1[1] System SYNLPM_LATR1 Q[0] BUS197_1 0.173 18.473
mips_core.decoder_pipe.idecoder.fsm_dly_1[2] System SYNLPM_LATR1 Q[0] BUS197_2 0.173 18.473
mips_core.MEM_CTL.i_mem_dout_ctl.dout_1[0] System SYNLPM_LATR1 Q[0] BUS22401_0 0.173 19.553
mips_core.MEM_CTL.i_mem_dout_ctl.dout_1[1] System SYNLPM_LATR1 Q[0] BUS22401_1 0.173 19.553
mips_core.MEM_CTL.i_mem_dout_ctl.dout_1[2] System SYNLPM_LATR1 Q[0] BUS22401_2 0.173 19.553
mips_core.MEM_CTL.i_mem_dout_ctl.dout_1[3] System SYNLPM_LATR1 Q[0] BUS22401_3 0.173 19.553
mips_core.MEM_CTL.i_mem_dout_ctl.dout_1[4] System SYNLPM_LATR1 Q[0] BUS22401_4 0.173 19.553
mips_core.MEM_CTL.i_mem_dout_ctl.dout_1[5] System SYNLPM_LATR1 Q[0] BUS22401_5 0.173 19.553
mips_core.MEM_CTL.i_mem_dout_ctl.dout_1[6] System SYNLPM_LATR1 Q[0] BUS22401_6 0.173 19.553
==============================================================================================================================
<a name=endingSlack28>Ending Points with Worst Slack
******************************
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
----------------------------------------------------------------------------------------------------------------------------------------------------------
imips_dvc.iuart0.uart_txd.fifo.scfifo_component System scfifo_Z1 rdreq ua_state_ns_0_a2_0_0 19.539 17.925
mips_core.decoder_pipe.idecoder.fsm_dly_1[1] System SYNLPM_LATR1 DATA[0] fsm_dly_2_i_m3_0[1] 19.971 18.473
mips_core.decoder_pipe.idecoder.fsm_dly_1[2] System SYNLPM_LATR1 DATA[0] fsm_dly_2_0_0[2] 19.971 18.473
mips_core.iRF_stage.MIAN_FSM.CurrState_Sreg0[1] System cyclone_lcell_ff dataa CurrState_Sreg0_ns_0_0_a[1] 19.971 18.554
mips_core.iRF_stage.MIAN_FSM.CurrState_Sreg0[8] System cyclone_lcell_ff datab CurrState_Sreg0_ns_0_0_0_a_x[8] 19.971 18.554
imips_dvc.iuart0.uart_txd.read_request_ff System cyclone_lcell_ff dataa empty 19.971 19.056
imips_dvc.iuart0.uart_txd.ua_state[1] System cyclone_lcell_ff dataa empty 19.971 19.056
imips_dvc.iuart0.uart_txd.ua_state_i[0] System cyclone_lcell_ff dataa empty 19.971 19.056
mips_core.iRF_stage.MIAN_FSM.CurrState_Sreg0[2] System cyclone_lcell_ff datab BUS197_1 19.971 19.140
mips_core.iRF_stage.MIAN_FSM.CurrState_Sreg0[2] System cyclone_lcell_ff datac BUS197_2 19.971 19.140
==========================================================================================================================================================
<a name=worstPaths29>Worst Path Information
<a href="E:\mips789\mips789\synplify_prj\rev_1\mips_sys.srr:fp:555667:556411:@XP_NAMES">View Worst Path in Analyst</a>
***********************
Path information for path number 1:
Requested Period: 20.000
- Setup time: 0.461
= Required time: 19.539
- Propagation time: 1.615
= Slack (non-critical) : 17.925
Number of logic level(s): 1
Starting point: imips_dvc.iuart0.uart_txd.fifo.scfifo_component / empty
Ending point: imips_dvc.iuart0.uart_txd.fifo.scfifo_component / rdreq
The start point is clocked by System [rising]
The end point is clocked by System [rising]
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
--------------------------------------------------------------------------------------------------------------------------
imips_dvc.iuart0.uart_txd.fifo.scfifo_component scfifo_Z1 empty Out 0.000 0.461 -
empty Net - - 0.455 - 4
imips_dvc.iuart0.uart_txd.ua_state_ns_0_a2_0[1] cyclone_lcell dataa In - 0.915 -
imips_dvc.iuart0.uart_txd.ua_state_ns_0_a2_0[1] cyclone_lcell combout Out 0.454 1.369 -
ua_state_ns_0_a2_0[1] Net - - 0.245 - 1
imips_dvc.iuart0.uart_txd.fifo.scfifo_component scfifo_Z1 rdreq In - 1.615 -
==========================================================================================================================
Total path delay (propagation time + setup) of 2.075 is 0.915(44.1%) logic and 0.700(33.7%) route.
##### END OF TIMING REPORT #####]
<a name=areaReport30>##### START OF AREA REPORT #####[
Design view:work.mips_sys(verilog)
Selecting part EP1C6Q240C6
@N:<a href="@N:FA174:@XP_HELP">FA174</a> : <!@TM:1223827112> | The following device usage report estimates place and route data. Please look at the place and route report for final resource usage..
I/O ATOMs: 197
Total LUTs: 3388 of 5980 (56%)
Logic resources: 3521 ATOMs of 5980 (58%)
ATOM count by mode:
normal: 3108
arithmetic: 413
ShiftTap: 0 (0 registers)
Total ESB: 2048 bits (2% of 81920)
LPM latches: 72
ATOMs using regout pin: 794
also using enable pin: 310
also using combout pin: 255
ATOMs using combout pin: 2883
Number of Inputs on ATOMs: 12752
Number of Nets: 10675
##### END OF AREA REPORT #####]
Mapper successful!
Process took 0h:1m:39s realtime, 0h:1m:39s cputime
###########################################################]
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