Subversion Repositories mips789

SCHM0103

HEADER
{
 FREEID 726
 VARIABLES
 {
  #BLOCKTABLE_FILE="#table.bde"
  #BLOCKTABLE_INCLUDED="1"
  #LANGUAGE="VERILOG"
  #MODULE="MIPSUART"
  AUTHOR="Unknown"
  COMPANY="Unknown"
  CREATIONDATE="8/16/2008"
  TITLE="MIPS_UART"
 }
 SYMBOL "#default" "mem_array" "mem_array"
 {
  HEADER
  {
   VARIABLES
   {
    #DESCRIPTION=""
    #LANGUAGE="VERILOG"
    #MODIFIED="1218631627"
   }
  }
  PAGE "" 
  {
   PAGEHEADER
   {
    RECT (0,0,300,280)
    FREEID 19
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   BODY
   {
    RECT  1, -1, 0
    {
     VARIABLES
     {
      #OUTLINE_FILLING="1"
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     AREA (20,0,280,280)
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    TEXT  3, 0, 0
    {
     TEXT "$#NAME"
     RECT (25,30,60,54)
     ALIGN 4
     MARGINS (1,1)
     PARENT 2
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    TEXT  5, 0, 0
    {
     TEXT "$#NAME"
     RECT (163,30,275,54)
     ALIGN 6
     MARGINS (1,1)
     PARENT 4
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    TEXT  7, 0, 0
    {
     TEXT "$#NAME"
     RECT (25,70,126,94)
     ALIGN 4
     MARGINS (1,1)
     PARENT 6
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    TEXT  9, 0, 0
    {
     TEXT "$#NAME"
     RECT (152,70,275,94)
     ALIGN 6
     MARGINS (1,1)
     PARENT 8
    }
    TEXT  11, 0, 0
    {
     TEXT "$#NAME"
     RECT (25,110,137,134)
     ALIGN 4
     MARGINS (1,1)
     PARENT 10
    }
    TEXT  13, 0, 0
    {
     TEXT "$#NAME"
     RECT (25,150,192,174)
     ALIGN 4
     MARGINS (1,1)
     PARENT 12
    }
    TEXT  15, 0, 0
    {
     TEXT "$#NAME"
     RECT (25,190,192,214)
     ALIGN 4
     MARGINS (1,1)
     PARENT 14
    }
    TEXT  17, 0, 0
    {
     TEXT "$#NAME"
     RECT (25,230,126,254)
     ALIGN 4
     MARGINS (1,1)
     PARENT 16
    }
    PIN  2, 0, 0
    {
     COORD (0,40)
     VARIABLES
     {
      #DIRECTION="IN"
      #LENGTH="20"
      #MDA_RECORD_TOKEN="OTHER"
      #NAME="clk"
      #NUMBER="0"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (0,0), (20,0) )
     }
    }
    PIN  4, 0, 0
    {
     COORD (300,40)
     VARIABLES
     {
      #DIRECTION="OUT"
      #DOWNTO="1"
      #LENGTH="20"
      #MDA_RECORD_TOKEN="OTHER"
      #NAME="dout(31:0)"
      #NUMBER="0"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (-20,0), (0,0) )
     }
    }
    PIN  6, 0, 0
    {
     COORD (0,80)
     VARIABLES
     {
      #DIRECTION="IN"
      #DOWNTO="1"
      #LENGTH="20"
      #MDA_RECORD_TOKEN="OTHER"
      #NAME="din(31:0)"
      #NUMBER="0"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (0,0), (20,0) )
     }
    }
    PIN  8, 0, 0
    {
     COORD (300,80)
     VARIABLES
     {
      #DIRECTION="OUT"
      #DOWNTO="1"
      #LENGTH="20"
      #MDA_RECORD_TOKEN="OTHER"
      #NAME="ins_o(31:0)"
      #NUMBER="0"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (-20,0), (0,0) )
     }
    }
    PIN  10, 0, 0
    {
     COORD (0,120)
     VARIABLES
     {
      #DIRECTION="IN"
      #DOWNTO="1"
      #LENGTH="20"
      #MDA_RECORD_TOKEN="OTHER"
      #NAME="pc_i(31:0)"
      #NUMBER="0"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (0,0), (20,0) )
     }
    }
    PIN  12, 0, 0
    {
     COORD (0,160)
     VARIABLES
     {
      #DIRECTION="IN"
      #DOWNTO="1"
      #LENGTH="20"
      #MDA_RECORD_TOKEN="OTHER"
      #NAME="rd_addr_i(31:0)"
      #NUMBER="0"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (0,0), (20,0) )
     }
    }
    PIN  14, 0, 0
    {
     COORD (0,200)
     VARIABLES
     {
      #DIRECTION="IN"
      #DOWNTO="1"
      #LENGTH="20"
      #MDA_RECORD_TOKEN="OTHER"
      #NAME="wr_addr_i(31:0)"
      #NUMBER="0"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (0,0), (20,0) )
     }
    }
    PIN  16, 0, 0
    {
     COORD (0,240)
     VARIABLES
     {
      #DIRECTION="IN"
      #DOWNTO="1"
      #LENGTH="20"
      #MDA_RECORD_TOKEN="OTHER"
      #NAME="wren(3:0)"
      #NUMBER="0"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (0,0), (20,0) )
     }
    }
   }
  }
 }
 SYMBOL "#default" "mips_core1" "mips_core1"
 {
  HEADER
  {
   VARIABLES
   {
    #DESCRIPTION=""
    #LANGUAGE="VERILOG"
    #MODIFIED="1218631794"
   }
  }
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    FREEID 33
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    RECT  1, -1, 0
    {
     VARIABLES
     {
      #OUTLINE_FILLING="1"
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     AREA (20,0,420,360)
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    TEXT  3, 0, 0
    {
     TEXT "$#NAME"
     RECT (25,30,60,54)
     ALIGN 4
     MARGINS (1,1)
     PARENT 2
    }
    TEXT  5, 0, 0
    {
     TEXT "$#NAME"
     RECT (237,30,415,54)
     ALIGN 6
     MARGINS (1,1)
     PARENT 4
    }
    TEXT  7, 0, 0
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     TEXT "$#NAME"
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     ALIGN 4
     MARGINS (1,1)
     PARENT 6
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    TEXT  9, 0, 0
    {
     TEXT "$#NAME"
     RECT (237,70,415,94)
     ALIGN 6
     MARGINS (1,1)
     PARENT 8
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    TEXT  11, 0, 0
    {
     TEXT "$#NAME"
     RECT (25,110,181,134)
     ALIGN 4
     MARGINS (1,1)
     PARENT 10
    }
    TEXT  13, 0, 0
    {
     TEXT "$#NAME"
     RECT (215,110,415,134)
     ALIGN 6
     MARGINS (1,1)
     PARENT 12
    }
    TEXT  15, 0, 0
    {
     TEXT "$#NAME"
     RECT (25,150,82,174)
     ALIGN 4
     MARGINS (1,1)
     PARENT 14
    }
    TEXT  17, 0, 0
    {
     TEXT "$#NAME"
     RECT (347,150,415,174)
     ALIGN 6
     MARGINS (1,1)
     PARENT 16
    }
    TEXT  19, 0, 0
    {
     TEXT "$#NAME"
     RECT (25,190,60,214)
     ALIGN 4
     MARGINS (1,1)
     PARENT 18
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    TEXT  21, 0, 0
    {
     TEXT "$#NAME"
     RECT (248,190,415,214)
     ALIGN 6
     MARGINS (1,1)
     PARENT 20
    }
    TEXT  23, 0, 0
    {
     TEXT "$#NAME"
     RECT (25,230,159,254)
     ALIGN 4
     MARGINS (1,1)
     PARENT 22
    }
    TEXT  25, 0, 0
    {
     TEXT "$#NAME"
     RECT (270,230,415,254)
     ALIGN 6
     MARGINS (1,1)
     PARENT 24
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    TEXT  27, 0, 0
    {
     TEXT "$#NAME"
     RECT (25,270,181,294)
     ALIGN 4
     MARGINS (1,1)
     PARENT 26
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    TEXT  29, 0, 0
    {
     TEXT "$#NAME"
     RECT (270,270,415,294)
     ALIGN 6
     MARGINS (1,1)
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    }
    TEXT  31, 0, 0
    {
     TEXT "$#NAME"
     RECT (248,310,415,334)
     ALIGN 6
     MARGINS (1,1)
     PARENT 30
    }
    PIN  2, 0, 0
    {
     COORD (0,40)
     VARIABLES
     {
      #DIRECTION="IN"
      #LENGTH="20"
      #MDA_RECORD_TOKEN="OTHER"
      #NAME="clk"
      #NUMBER="0"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (0,0), (20,0) )
     }
    }
    PIN  4, 0, 0
    {
     COORD (440,40)
     VARIABLES
     {
      #DIRECTION="OUT"
      #DOWNTO="1"
      #LENGTH="20"
      #MDA_RECORD_TOKEN="OTHER"
      #NAME="cop_addr_o(31:0)"
      #NUMBER="0"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (-20,0), (0,0) )
     }
    }
    PIN  6, 0, 0
    {
     COORD (0,80)
     VARIABLES
     {
      #DIRECTION="IN"
      #DOWNTO="1"
      #LENGTH="20"
      #MDA_RECORD_TOKEN="OTHER"
      #NAME="cop_dout(31:0)"
      #NUMBER="0"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (0,0), (20,0) )
     }
    }
    PIN  8, 0, 0
    {
     COORD (440,80)
     VARIABLES
     {
      #DIRECTION="OUT"
      #DOWNTO="1"
      #LENGTH="20"
      #MDA_RECORD_TOKEN="OTHER"
      #NAME="cop_data_o(31:0)"
      #NUMBER="0"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (-20,0), (0,0) )
     }
    }
    PIN  10, 0, 0
    {
     COORD (0,120)
     VARIABLES
     {
      #DIRECTION="IN"
      #DOWNTO="1"
      #LENGTH="20"
      #MDA_RECORD_TOKEN="OTHER"
      #NAME="irq_addr(31:0)"
      #NUMBER="0"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (0,0), (20,0) )
     }
    }
    PIN  12, 0, 0
    {
     COORD (440,120)
     VARIABLES
     {
      #DIRECTION="OUT"
      #DOWNTO="1"
      #LENGTH="20"
      #MDA_RECORD_TOKEN="OTHER"
      #NAME="cop_mem_ctl_o(3:0)"
      #NUMBER="0"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (-20,0), (0,0) )
     }
    }
    PIN  14, 0, 0
    {
     COORD (0,160)
     VARIABLES
     {
      #DIRECTION="IN"
      #LENGTH="20"
      #MDA_RECORD_TOKEN="OTHER"
      #NAME="irq_i"
      #NUMBER="0"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (0,0), (20,0) )
     }
    }
    PIN  16, 0, 0
    {
     COORD (440,160)
     VARIABLES
     {
      #DIRECTION="OUT"
      #LENGTH="20"
      #MDA_RECORD_TOKEN="OTHER"
      #NAME="iack_o"
      #NUMBER="0"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (-20,0), (0,0) )
     }
    }
    PIN  18, 0, 0
    {
     COORD (0,200)
     VARIABLES
     {
      #DIRECTION="IN"
      #LENGTH="20"
      #MDA_RECORD_TOKEN="OTHER"
      #NAME="rst"
      #NUMBER="0"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (0,0), (20,0) )
     }
    }
    PIN  20, 0, 0
    {
     COORD (440,200)
     VARIABLES
     {
      #DIRECTION="OUT"
      #DOWNTO="1"
      #LENGTH="20"
      #MDA_RECORD_TOKEN="OTHER"
      #NAME="zz_addr_o(31:0)"
      #NUMBER="0"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (-20,0), (0,0) )
     }
    }
    PIN  22, 0, 0
    {
     COORD (0,240)
     VARIABLES
     {
      #DIRECTION="IN"
      #DOWNTO="1"
      #LENGTH="20"
      #MDA_RECORD_TOKEN="OTHER"
      #NAME="zz_din(31:0)"
      #NUMBER="0"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (0,0), (20,0) )
     }
    }
    PIN  24, 0, 0
    {
     COORD (440,240)
     VARIABLES
     {
      #DIRECTION="OUT"
      #DOWNTO="1"
      #LENGTH="20"
      #MDA_RECORD_TOKEN="OTHER"
      #NAME="zz_dout(31:0)"
      #NUMBER="0"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (-20,0), (0,0) )
     }
    }
    PIN  26, 0, 0
    {
     COORD (0,280)
     VARIABLES
     {
      #DIRECTION="IN"
      #DOWNTO="1"
      #LENGTH="20"
      #MDA_RECORD_TOKEN="OTHER"
      #NAME="zz_ins_i(31:0)"
      #NUMBER="0"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (0,0), (20,0) )
     }
    }
    PIN  28, 0, 0
    {
     COORD (440,280)
     VARIABLES
     {
      #DIRECTION="OUT"
      #DOWNTO="1"
      #LENGTH="20"
      #MDA_RECORD_TOKEN="OTHER"
      #NAME="zz_pc_o(31:0)"
      #NUMBER="0"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (-20,0), (0,0) )
     }
    }
    PIN  30, 0, 0
    {
     COORD (440,320)
     VARIABLES
     {
      #DIRECTION="OUT"
      #DOWNTO="1"
      #LENGTH="20"
      #MDA_RECORD_TOKEN="OTHER"
      #NAME="zz_wr_en_o(3:0)"
      #NUMBER="0"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (-20,0), (0,0) )
     }
    }
   }
  }
 }
 SYMBOL "#default" "mips_uart" "mips_uart"
 {
  HEADER
  {
   VARIABLES
   {
    #DESCRIPTION=""
    #GENERIC0="FREQUENCE:integer:=25000000"
    #GENERIC1="BANDRATE:integer:=9600"
    #LANGUAGE="VERILOG"
    #MODIFIED="1218827070"
   }
  }
  PAGE "" 
  {
   PAGEHEADER
   {
    RECT (0,0,320,280)
    FREEID 19
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   BODY
   {
    RECT  1, -1, 0
    {
     VARIABLES
     {
      #OUTLINE_FILLING="1"
     }
     AREA (20,0,300,280)
    }
    TEXT  3, 0, 0
    {
     TEXT "$#NAME"
     RECT (25,30,159,54)
     ALIGN 4
     MARGINS (1,1)
     PARENT 2
    }
    TEXT  5, 0, 0
    {
     TEXT "$#NAME"
     RECT (183,30,295,54)
     ALIGN 6
     MARGINS (1,1)
     PARENT 4
    }
    TEXT  7, 0, 0
    {
     TEXT "$#NAME"
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     ALIGN 4
     MARGINS (1,1)
     PARENT 6
    }
    TEXT  9, 0, 0
    {
     TEXT "$#NAME"
     RECT (238,70,295,94)
     ALIGN 6
     MARGINS (1,1)
     PARENT 8
    }
    TEXT  11, 0, 0
    {
     TEXT "$#NAME"
     RECT (25,110,126,134)
     ALIGN 4
     MARGINS (1,1)
     PARENT 10
    }
    TEXT  13, 0, 0
    {
     TEXT "$#NAME"
     RECT (25,150,192,174)
     ALIGN 4
     MARGINS (1,1)
     PARENT 12
    }
    TEXT  15, 0, 0
    {
     TEXT "$#NAME"
     RECT (25,190,60,214)
     ALIGN 4
     MARGINS (1,1)
     PARENT 14
    }
    TEXT  17, 0, 0
    {
     TEXT "$#NAME"
     RECT (25,230,82,254)
     ALIGN 4
     MARGINS (1,1)
     PARENT 16
    }
    PIN  2, 0, 0
    {
     COORD (0,40)
     VARIABLES
     {
      #DIRECTION="IN"
      #DOWNTO="1"
      #LENGTH="20"
      #MDA_RECORD_TOKEN="OTHER"
      #NAME="addr_i(31:0)"
      #NUMBER="0"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (0,0), (20,0) )
     }
    }
    PIN  4, 0, 0
    {
     COORD (320,40)
     VARIABLES
     {
      #DIRECTION="OUT"
      #DOWNTO="1"
      #LENGTH="20"
      #MDA_RECORD_TOKEN="OTHER"
      #NAME="dout(31:0)"
      #NUMBER="0"
      #VERILOG_TYPE="reg"
     }
     LINE  2, 0, 0
     {
      POINTS ( (-20,0), (0,0) )
     }
    }
    PIN  6, 0, 0
    {
     COORD (0,80)
     VARIABLES
     {
      #DIRECTION="IN"
      #LENGTH="20"
      #MDA_RECORD_TOKEN="OTHER"
      #NAME="clk"
      #NUMBER="0"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (0,0), (20,0) )
     }
    }
    PIN  8, 0, 0
    {
     COORD (320,80)
     VARIABLES
     {
      #DIRECTION="OUT"
      #LENGTH="20"
      #MDA_RECORD_TOKEN="OTHER"
      #NAME="ser_o"
      #NUMBER="0"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (-20,0), (0,0) )
     }
    }
    PIN  10, 0, 0
    {
     COORD (0,120)
     VARIABLES
     {
      #DIRECTION="IN"
      #DOWNTO="1"
      #LENGTH="20"
      #MDA_RECORD_TOKEN="OTHER"
      #NAME="din(31:0)"
      #NUMBER="0"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (0,0), (20,0) )
     }
    }
    PIN  12, 0, 0
    {
     COORD (0,160)
     VARIABLES
     {
      #DIRECTION="IN"
      #DOWNTO="1"
      #LENGTH="20"
      #MDA_RECORD_TOKEN="OTHER"
      #NAME="dmem_ctl_i(3:0)"
      #NUMBER="0"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (0,0), (20,0) )
     }
    }
    PIN  14, 0, 0
    {
     COORD (0,200)
     VARIABLES
     {
      #DIRECTION="IN"
      #LENGTH="20"
      #MDA_RECORD_TOKEN="OTHER"
      #NAME="rst"
      #NUMBER="0"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (0,0), (20,0) )
     }
    }
    PIN  16, 0, 0
    {
     COORD (0,240)
     VARIABLES
     {
      #DIRECTION="IN"
      #LENGTH="20"
      #MDA_RECORD_TOKEN="OTHER"
      #NAME="ser_i"
      #NUMBER="0"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (0,0), (20,0) )
     }
    }
   }
  }
 }
}

PAGE ""
{
 PAGEHEADER
 {
  PAGESIZE (2200,1700)
  MARGINS (200,200,200,200)
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 BODY
 {
  INSTANCE  1, 0, 0
  {
   VARIABLES
   {
    #COMPONENT="mem_array"
    #LIBRARY="#default"
    #REFERENCE="ram_4k"
    #SYMBOL="mem_array"
   }
   COORD (1380,780)
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  {
   TEXT "$#REFERENCE"
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   ALIGN 8
   MARGINS (1,1)
   PARENT 1
  }
  TEXT  11, 0, 0
  {
   TEXT "$#COMPONENT"
   RECT (1380,1060,1535,1095)
   MARGINS (1,1)
   PARENT 1
  }
  INSTANCE  12, 0, 0
  {
   VARIABLES
   {
    #COMPONENT="Input"
    #LIBRARY="#terminals"
    #REFERENCE="clk"
    #SYMBOL="Input"
   }
   COORD (520,660)
   VERTEXES ( (2,245) )
  }
  TEXT  14, 0, 0
  {
   TEXT "$#REFERENCE"
   RECT (416,643,469,678)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
  }
  INSTANCE  15, 0, 0
  {
   VARIABLES
   {
    #COMPONENT="Input"
    #LIBRARY="#terminals"
    #REFERENCE="rst"
    #SYMBOL="Input"
   }
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   VERTEXES ( (2,239) )
  }
  TEXT  17, 0, 0
  {
   TEXT "$#REFERENCE"
   RECT (416,883,469,918)
   ALIGN 6
   MARGINS (1,1)
   PARENT 15
  }
  INSTANCE  18, 0, 0
  {
   VARIABLES
   {
    #COMPONENT="Input"
    #LIBRARY="#terminals"
    #REFERENCE="key2"
    #SYMBOL="Input"
   }
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  NET WIRE  21, 0, 0
  NET WIRE  43, 0, 0
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  INSTANCE  57, 0, 0
  {
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   {
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    #REFERENCE="mips_core_"
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   COORD (620,700)
   VERTEXES ( (2,244), (10,249), (14,231), (18,237), (22,263), (26,255), (4,266), (8,268), (12,270), (30,258), (6,599), (28,679), (20,685), (24,692) )
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  TEXT  72, 0, 0
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  TEXT  73, 0, 0
  {
   TEXT "$#COMPONENT"
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  NET BUS  74, 0, 0
  NET BUS  76, 0, 0
  INSTANCE  81, 0, 0
  {
   VARIABLES
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  TEXT  83, 0, 0
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  {
   VARIABLES
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  NET BUS  92, 0, 0
  {
   VARIABLES
   {
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   }
  }
  NET BUS  98, 0, 0
  {
   VARIABLES
   {
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   }
  }
  NET BUS  100, 0, 0
  {
   VARIABLES
   {
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  }
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  {
   VARIABLES
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  TEXT  119, 0, 0
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  TEXT  122, 0, 0
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   PARENT 694
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  TEXT  127, 0, 0
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   PARENT 684
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  TEXT  131, 0, 0
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  NET BUS  133, 0, 0
  {
   VARIABLES
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    #NAME="data2core(31:0)"
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  }
  TEXT  141, 0, 0
  {
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   PARENT 326
  }
  NET BUS  143, 0, 0
  {
   VARIABLES
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    #VERILOG_TYPE="wire"
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  }
  TEXT  147, 0, 0
  {
   TEXT "$#NAME"
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   ALIGN 4
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   PARENT 333
  }
  NET BUS  148, 0, 0
  {
   VARIABLES
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    #NAME="data2cop(31:0)"
    #VERILOG_TYPE="wire"
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  }
  TEXT  152, 0, 0
  {
   TEXT "$#NAME"
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   ALIGN 4
   MARGINS (1,1)
   PARENT 338
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  NET BUS  153, 0, 0
  {
   VARIABLES
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    #NAME="cop_mem_ctl(3:0)"
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  TEXT  157, 0, 0
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    #NAMED="1"
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    #NAMED="1"
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    #NAMED="1"
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  }
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   NET 153
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   NET 153
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   VARIABLES
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    #NAMED="1"
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  INSTANCE  345, 0, 0
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   VARIABLES
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    #COMPONENT="mips_uart"
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    #REFERENCE="uart"
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