URL
https://opencores.org/ocsvn/mips789/mips789/trunk
Subversion Repositories mips789
[/] [mips789/] [branches/] [mcupro/] [dbe/] [decode_pipe.BDE] - Rev 61
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SCHM0103
HEADER
{
FREEID 6022
VARIABLES
{
#BLOCKTABLE_FILE="#table.bde"
#BLOCKTABLE_INCLUDED="1"
#LANGUAGE="VERILOG"
#MODULE="decode_pipe3"
AUTHOR="liwei"
COMPANY="PKU"
CREATIONDATE="2007-8-4"
TITLE="No Title"
}
SYMBOL "#default" "pipelinedregs" "pipelinedregs"
{
HEADER
{
VARIABLES
{
#DESCRIPTION=""
#GENERIC0="DANGLING_INPUT_CONSTANT:integer:=1'bZ"
#LANGUAGE="VERILOG"
#MODIFIED="1194442907"
}
}
PAGE ""
{
PAGEHEADER
{
RECT (0,0,400,640)
FREEID 57
}
BODY
{
RECT 1, -1, 0
{
VARIABLES
{
#OUTLINE_FILLING="1"
}
AREA (20,0,380,640)
}
TEXT 3, 0, 0
{
TEXT "$#NAME"
RECT (25,30,192,54)
ALIGN 4
MARGINS (1,1)
PARENT 2
}
TEXT 5, 0, 0
{
TEXT "$#NAME"
RECT (208,30,375,54)
ALIGN 6
MARGINS (1,1)
PARENT 4
}
TEXT 7, 0, 0
{
TEXT "$#NAME"
RECT (25,70,170,94)
ALIGN 4
MARGINS (1,1)
PARENT 6
}
TEXT 9, 0, 0
{
TEXT "$#NAME"
RECT (230,70,375,94)
ALIGN 6
MARGINS (1,1)
PARENT 8
}
TEXT 11, 0, 0
{
TEXT "$#NAME"
RECT (25,110,60,134)
ALIGN 4
MARGINS (1,1)
PARENT 10
}
TEXT 13, 0, 0
{
TEXT "$#NAME"
RECT (219,110,375,134)
ALIGN 6
MARGINS (1,1)
PARENT 12
}
TEXT 15, 0, 0
{
TEXT "$#NAME"
RECT (25,150,181,174)
ALIGN 4
MARGINS (1,1)
PARENT 14
}
TEXT 17, 0, 0
{
TEXT "$#NAME"
RECT (208,150,375,174)
ALIGN 6
MARGINS (1,1)
PARENT 16
}
TEXT 19, 0, 0
{
TEXT "$#NAME"
RECT (25,190,192,214)
ALIGN 4
MARGINS (1,1)
PARENT 18
}
TEXT 21, 0, 0
{
TEXT "$#NAME"
RECT (175,190,375,214)
ALIGN 6
MARGINS (1,1)
PARENT 20
}
TEXT 23, 0, 0
{
TEXT "$#NAME"
RECT (25,230,181,254)
ALIGN 4
MARGINS (1,1)
PARENT 22
}
TEXT 25, 0, 0
{
TEXT "$#NAME"
RECT (241,230,375,254)
ALIGN 6
MARGINS (1,1)
PARENT 24
}
TEXT 27, 0, 0
{
TEXT "$#NAME"
RECT (25,270,170,294)
ALIGN 4
MARGINS (1,1)
PARENT 26
}
TEXT 29, 0, 0
{
TEXT "$#NAME"
RECT (208,270,375,294)
ALIGN 6
MARGINS (1,1)
PARENT 28
}
TEXT 31, 0, 0
{
TEXT "$#NAME"
RECT (25,310,170,334)
ALIGN 4
MARGINS (1,1)
PARENT 30
}
TEXT 33, 0, 0
{
TEXT "$#NAME"
RECT (208,310,375,334)
ALIGN 6
MARGINS (1,1)
PARENT 32
}
TEXT 35, 0, 0
{
TEXT "$#NAME"
RECT (25,350,192,374)
ALIGN 4
MARGINS (1,1)
PARENT 34
}
TEXT 37, 0, 0
{
TEXT "$#NAME"
RECT (186,350,375,374)
ALIGN 6
MARGINS (1,1)
PARENT 36
}
TEXT 39, 0, 0
{
TEXT "$#NAME"
RECT (25,390,192,414)
ALIGN 4
MARGINS (1,1)
PARENT 38
}
TEXT 41, 0, 0
{
TEXT "$#NAME"
RECT (230,390,375,414)
ALIGN 6
MARGINS (1,1)
PARENT 40
}
TEXT 43, 0, 0
{
TEXT "$#NAME"
RECT (25,430,214,454)
ALIGN 4
MARGINS (1,1)
PARENT 42
}
TEXT 45, 0, 0
{
TEXT "$#NAME"
RECT (186,430,375,454)
ALIGN 6
MARGINS (1,1)
PARENT 44
}
TEXT 47, 0, 0
{
TEXT "$#NAME"
RECT (25,470,170,494)
ALIGN 4
MARGINS (1,1)
PARENT 46
}
TEXT 49, 0, 0
{
TEXT "$#NAME"
RECT (241,470,375,494)
ALIGN 6
MARGINS (1,1)
PARENT 48
}
TEXT 51, 0, 0
{
TEXT "$#NAME"
RECT (25,510,170,534)
ALIGN 4
MARGINS (1,1)
PARENT 50
}
TEXT 53, 0, 0
{
TEXT "$#NAME"
RECT (25,550,214,574)
ALIGN 4
MARGINS (1,1)
PARENT 52
}
TEXT 55, 0, 0
{
TEXT "$#NAME"
RECT (25,590,159,614)
ALIGN 4
MARGINS (1,1)
PARENT 54
}
PIN 2, 0, 0
{
COORD (0,40)
VARIABLES
{
#DIRECTION="IN"
#DOWNTO="1"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="alu_func_i(4:0)"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (20,0) )
}
}
PIN 4, 0, 0
{
COORD (400,40)
VARIABLES
{
#DIRECTION="OUT"
#DOWNTO="1"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="alu_func_o(4:0)"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (-20,0), (0,0) )
}
}
PIN 6, 0, 0
{
COORD (0,80)
VARIABLES
{
#DIRECTION="IN"
#DOWNTO="1"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="alu_we_i(0:0)"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (20,0) )
}
}
PIN 8, 0, 0
{
COORD (400,80)
VARIABLES
{
#DIRECTION="OUT"
#DOWNTO="1"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="alu_we_o(0:0)"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (-20,0), (0,0) )
}
}
PIN 10, 0, 0
{
COORD (0,120)
VARIABLES
{
#DIRECTION="IN"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="clk"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (20,0) )
}
}
PIN 12, 0, 0
{
COORD (400,120)
VARIABLES
{
#DIRECTION="OUT"
#DOWNTO="1"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="cmp_ctl_o(2:0)"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (-20,0), (0,0) )
}
}
PIN 14, 0, 0
{
COORD (0,160)
VARIABLES
{
#DIRECTION="IN"
#DOWNTO="1"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="cmp_ctl_i(2:0)"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (20,0) )
}
}
PIN 16, 0, 0
{
COORD (400,160)
VARIABLES
{
#DIRECTION="OUT"
#DOWNTO="1"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="dmem_ctl_o(3:0)"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (-20,0), (0,0) )
}
}
PIN 18, 0, 0
{
COORD (0,200)
VARIABLES
{
#DIRECTION="IN"
#DOWNTO="1"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="dmem_ctl_i(3:0)"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (20,0) )
}
}
PIN 20, 0, 0
{
COORD (400,200)
VARIABLES
{
#DIRECTION="OUT"
#DOWNTO="1"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="dmem_ctl_ur_o(3:0)"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (-20,0), (0,0) )
}
}
PIN 22, 0, 0
{
COORD (0,240)
VARIABLES
{
#DIRECTION="IN"
#DOWNTO="1"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="ext_ctl_i(2:0)"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (20,0) )
}
}
PIN 24, 0, 0
{
COORD (400,240)
VARIABLES
{
#DIRECTION="OUT"
#DOWNTO="1"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="ext_ctl(2:0)"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (-20,0), (0,0) )
}
}
PIN 26, 0, 0
{
COORD (0,280)
VARIABLES
{
#DIRECTION="IN"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="id2ra_ctl_clr"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (20,0) )
}
}
PIN 28, 0, 0
{
COORD (400,280)
VARIABLES
{
#DIRECTION="OUT"
#DOWNTO="1"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="muxa_ctl_o(1:0)"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (-20,0), (0,0) )
}
}
PIN 30, 0, 0
{
COORD (0,320)
VARIABLES
{
#DIRECTION="IN"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="id2ra_ctl_cls"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (20,0) )
}
}
PIN 32, 0, 0
{
COORD (400,320)
VARIABLES
{
#DIRECTION="OUT"
#DOWNTO="1"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="muxb_ctl_o(1:0)"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (-20,0), (0,0) )
}
}
PIN 34, 0, 0
{
COORD (0,360)
VARIABLES
{
#DIRECTION="IN"
#DOWNTO="1"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="muxa_ctl_i(1:0)"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (20,0) )
}
}
PIN 36, 0, 0
{
COORD (400,360)
VARIABLES
{
#DIRECTION="OUT"
#DOWNTO="1"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="pc_gen_ctl_o(2:0)"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (-20,0), (0,0) )
}
}
PIN 38, 0, 0
{
COORD (0,400)
VARIABLES
{
#DIRECTION="IN"
#DOWNTO="1"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="muxb_ctl_i(1:0)"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (20,0) )
}
}
PIN 40, 0, 0
{
COORD (400,400)
VARIABLES
{
#DIRECTION="OUT"
#DOWNTO="1"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="rd_sel_o(1:0)"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (-20,0), (0,0) )
}
}
PIN 42, 0, 0
{
COORD (0,440)
VARIABLES
{
#DIRECTION="IN"
#DOWNTO="1"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="pc_gen_ctl_i(2:0)"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (20,0) )
}
}
PIN 44, 0, 0
{
COORD (400,440)
VARIABLES
{
#DIRECTION="OUT"
#DOWNTO="1"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="wb_mux_ctl_o(0:0)"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (-20,0), (0,0) )
}
}
PIN 46, 0, 0
{
COORD (0,480)
VARIABLES
{
#DIRECTION="IN"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="ra2ex_ctl_clr"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (20,0) )
}
}
PIN 48, 0, 0
{
COORD (400,480)
VARIABLES
{
#DIRECTION="OUT"
#DOWNTO="1"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="wb_we_o(0:0)"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (-20,0), (0,0) )
}
}
PIN 50, 0, 0
{
COORD (0,520)
VARIABLES
{
#DIRECTION="IN"
#DOWNTO="1"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="rd_sel_i(1:0)"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (20,0) )
}
}
PIN 52, 0, 0
{
COORD (0,560)
VARIABLES
{
#DIRECTION="IN"
#DOWNTO="1"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="wb_mux_ctl_i(0:0)"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (20,0) )
}
}
PIN 54, 0, 0
{
COORD (0,600)
VARIABLES
{
#DIRECTION="IN"
#DOWNTO="1"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="wb_we_i(0:0)"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (20,0) )
}
}
}
}
}
SYMBOL "#default" "decoder3" "decoder3"
{
HEADER
{
VARIABLES
{
#DESCRIPTION=""
#LANGUAGE="VERILOG"
#MODIFIED="1218402908"
}
}
PAGE ""
{
PAGEHEADER
{
RECT (0,0,280,520)
FREEID 28
}
BODY
{
RECT 1, -1, 0
{
VARIABLES
{
#OUTLINE_FILLING="1"
}
AREA (20,0,260,520)
}
TEXT 3, 0, 0
{
TEXT "$#NAME"
RECT (25,30,148,54)
ALIGN 4
MARGINS (1,1)
PARENT 2
}
TEXT 5, 0, 0
{
TEXT "$#NAME"
RECT (110,30,255,54)
ALIGN 6
MARGINS (1,1)
PARENT 4
}
TEXT 7, 0, 0
{
TEXT "$#NAME"
RECT (132,70,255,94)
ALIGN 6
MARGINS (1,1)
PARENT 6
}
TEXT 9, 0, 0
{
TEXT "$#NAME"
RECT (121,110,255,134)
ALIGN 6
MARGINS (1,1)
PARENT 8
}
TEXT 11, 0, 0
{
TEXT "$#NAME"
RECT (110,150,255,174)
ALIGN 6
MARGINS (1,1)
PARENT 10
}
TEXT 13, 0, 0
{
TEXT "$#NAME"
RECT (121,190,255,214)
ALIGN 6
MARGINS (1,1)
PARENT 12
}
TEXT 15, 0, 0
{
TEXT "$#NAME"
RECT (121,230,255,254)
ALIGN 6
MARGINS (1,1)
PARENT 14
}
TEXT 17, 0, 0
{
TEXT "$#NAME"
RECT (110,270,255,294)
ALIGN 6
MARGINS (1,1)
PARENT 16
}
TEXT 19, 0, 0
{
TEXT "$#NAME"
RECT (110,310,255,334)
ALIGN 6
MARGINS (1,1)
PARENT 18
}
TEXT 21, 0, 0
{
TEXT "$#NAME"
RECT (88,350,255,374)
ALIGN 6
MARGINS (1,1)
PARENT 20
}
TEXT 23, 0, 0
{
TEXT "$#NAME"
RECT (132,390,255,414)
ALIGN 6
MARGINS (1,1)
PARENT 22
}
TEXT 25, 0, 0
{
TEXT "$#NAME"
RECT (132,430,255,454)
ALIGN 6
MARGINS (1,1)
PARENT 24
}
TEXT 27, 0, 0
{
TEXT "$#NAME"
RECT (143,470,255,494)
ALIGN 6
MARGINS (1,1)
PARENT 26
}
PIN 2, 0, 0
{
COORD (0,40)
VARIABLES
{
#DIRECTION="IN"
#DOWNTO="1"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="ins_i(31:0)"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (20,0) )
}
}
PIN 4, 0, 0
{
COORD (280,40)
VARIABLES
{
#DIRECTION="OUT"
#DOWNTO="1"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="alu_func(4:0)"
#NUMBER="0"
#VERILOG_TYPE="reg"
}
LINE 2, 0, 0
{
POINTS ( (-20,0), (0,0) )
}
}
PIN 6, 0, 0
{
COORD (280,80)
VARIABLES
{
#DIRECTION="OUT"
#DOWNTO="1"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="alu_we(0:0)"
#NUMBER="0"
#VERILOG_TYPE="reg"
}
LINE 2, 0, 0
{
POINTS ( (-20,0), (0,0) )
}
}
PIN 8, 0, 0
{
COORD (280,120)
VARIABLES
{
#DIRECTION="OUT"
#DOWNTO="1"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="cmp_ctl(2:0)"
#NUMBER="0"
#VERILOG_TYPE="reg"
}
LINE 2, 0, 0
{
POINTS ( (-20,0), (0,0) )
}
}
PIN 10, 0, 0
{
COORD (280,160)
VARIABLES
{
#DIRECTION="OUT"
#DOWNTO="1"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="dmem_ctl(3:0)"
#NUMBER="0"
#VERILOG_TYPE="reg"
}
LINE 2, 0, 0
{
POINTS ( (-20,0), (0,0) )
}
}
PIN 12, 0, 0
{
COORD (280,200)
VARIABLES
{
#DIRECTION="OUT"
#DOWNTO="1"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="ext_ctl(2:0)"
#NUMBER="0"
#VERILOG_TYPE="reg"
}
LINE 2, 0, 0
{
POINTS ( (-20,0), (0,0) )
}
}
PIN 14, 0, 0
{
COORD (280,240)
VARIABLES
{
#DIRECTION="OUT"
#DOWNTO="1"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="fsm_dly(2:0)"
#NUMBER="0"
#VERILOG_TYPE="reg"
}
LINE 2, 0, 0
{
POINTS ( (-20,0), (0,0) )
}
}
PIN 16, 0, 0
{
COORD (280,280)
VARIABLES
{
#DIRECTION="OUT"
#DOWNTO="1"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="muxa_ctl(1:0)"
#NUMBER="0"
#VERILOG_TYPE="reg"
}
LINE 2, 0, 0
{
POINTS ( (-20,0), (0,0) )
}
}
PIN 18, 0, 0
{
COORD (280,320)
VARIABLES
{
#DIRECTION="OUT"
#DOWNTO="1"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="muxb_ctl(1:0)"
#NUMBER="0"
#VERILOG_TYPE="reg"
}
LINE 2, 0, 0
{
POINTS ( (-20,0), (0,0) )
}
}
PIN 20, 0, 0
{
COORD (280,360)
VARIABLES
{
#DIRECTION="OUT"
#DOWNTO="1"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="pc_gen_ctl(2:0)"
#NUMBER="0"
#VERILOG_TYPE="reg"
}
LINE 2, 0, 0
{
POINTS ( (-20,0), (0,0) )
}
}
PIN 22, 0, 0
{
COORD (280,400)
VARIABLES
{
#DIRECTION="OUT"
#DOWNTO="1"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="rd_sel(1:0)"
#NUMBER="0"
#VERILOG_TYPE="reg"
}
LINE 2, 0, 0
{
POINTS ( (-20,0), (0,0) )
}
}
PIN 24, 0, 0
{
COORD (280,440)
VARIABLES
{
#DIRECTION="OUT"
#DOWNTO="1"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="wb_mux(0:0)"
#NUMBER="0"
#VERILOG_TYPE="reg"
}
LINE 2, 0, 0
{
POINTS ( (-20,0), (0,0) )
}
}
PIN 26, 0, 0
{
COORD (280,480)
VARIABLES
{
#DIRECTION="OUT"
#DOWNTO="1"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="wb_we(0:0)"
#NUMBER="0"
#VERILOG_TYPE="reg"
}
LINE 2, 0, 0
{
POINTS ( (-20,0), (0,0) )
}
}
}
}
}
}
PAGE ""
{
PAGEHEADER
{
PAGESIZE (2200,1700)
MARGINS (200,200,200,200)
RECT (0,0,100,200)
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BODY
{
INSTANCE 99, 0, 0
{
VARIABLES
{
#COMPONENT="BusInput"
#LIBRARY="#terminals"
#REFERENCE="ins_i(31:0)"
#SYMBOL="BusInput"
}
COORD (460,460)
VERTEXES ( (2,5800) )
}
TEXT 100, 0, 0
{
TEXT "$#REFERENCE"
RECT (220,443,409,478)
ALIGN 6
MARGINS (1,1)
PARENT 99
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INSTANCE 566, 0, 0
{
VARIABLES
{
#COMPONENT="Input"
#LIBRARY="#terminals"
#REFERENCE="clk"
#SYMBOL="Input"
}
COORD (480,360)
VERTEXES ( (2,5362) )
}
TEXT 567, 0, 0
{
TEXT "$#REFERENCE"
RECT (376,343,429,378)
ALIGN 6
MARGINS (1,1)
PARENT 566
}
INSTANCE 632, 0, 0
{
VARIABLES
{
#COMPONENT="BusOutput"
#LIBRARY="#terminals"
#REFERENCE="alu_func_o(4:0)"
#SYMBOL="BusOutput"
#VERILOG_TYPE="wire"
}
COORD (1600,420)
VERTEXES ( (2,4058) )
}
TEXT 633, 0, 0
{
TEXT "$#REFERENCE"
RECT (1652,403,1909,438)
ALIGN 4
MARGINS (1,1)
PARENT 632
}
INSTANCE 637, 0, 0
{
VARIABLES
{
#COMPONENT="BusOutput"
#LIBRARY="#terminals"
#REFERENCE="alu_we_o(0:0)"
#SYMBOL="BusOutput"
#VERILOG_TYPE="wire"
}
COORD (1600,460)
VERTEXES ( (2,4060) )
}
TEXT 638, 0, 0
{
TEXT "$#REFERENCE"
RECT (1652,443,1875,478)
ALIGN 4
MARGINS (1,1)
PARENT 637
}
INSTANCE 642, 0, 0
{
VARIABLES
{
#COMPONENT="BusOutput"
#LIBRARY="#terminals"
#REFERENCE="cmp_ctl_o(2:0)"
#SYMBOL="BusOutput"
#VERILOG_TYPE="wire"
}
COORD (1600,500)
VERTEXES ( (2,4062) )
}
TEXT 643, 0, 0
{
TEXT "$#REFERENCE"
RECT (1652,483,1892,518)
ALIGN 4
MARGINS (1,1)
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}
INSTANCE 647, 0, 0
{
VARIABLES
{
#COMPONENT="BusOutput"
#LIBRARY="#terminals"
#REFERENCE="dmem_ctl_o(3:0)"
#SYMBOL="BusOutput"
#VERILOG_TYPE="wire"
}
COORD (1600,540)
VERTEXES ( (2,4064) )
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TEXT 648, 0, 0
{
TEXT "$#REFERENCE"
RECT (1652,523,1909,558)
ALIGN 4
MARGINS (1,1)
PARENT 647
}
INSTANCE 652, 0, 0
{
VARIABLES
{
#COMPONENT="BusOutput"
#LIBRARY="#terminals"
#REFERENCE="dmem_ctl_ur_o(3:0)"
#SYMBOL="BusOutput"
#VERILOG_TYPE="wire"
}
COORD (1600,580)
VERTEXES ( (2,4066) )
}
TEXT 653, 0, 0
{
TEXT "$#REFERENCE"
RECT (1652,563,1960,598)
ALIGN 4
MARGINS (1,1)
PARENT 652
}
INSTANCE 657, 0, 0
{
VARIABLES
{
#COMPONENT="BusOutput"
#LIBRARY="#terminals"
#REFERENCE="ext_ctl_o(2:0)"
#SYMBOL="BusOutput"
#VERILOG_TYPE="wire"
}
COORD (1600,620)
VERTEXES ( (2,4068) )
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TEXT 658, 0, 0
{
TEXT "$#REFERENCE"
RECT (1652,603,1892,638)
ALIGN 4
MARGINS (1,1)
PARENT 657
}
INSTANCE 662, 0, 0
{
VARIABLES
{
#COMPONENT="BusOutput"
#LIBRARY="#terminals"
#REFERENCE="muxa_ctl_o(1:0)"
#SYMBOL="BusOutput"
#VERILOG_TYPE="wire"
}
COORD (1600,660)
VERTEXES ( (2,4070) )
}
TEXT 663, 0, 0
{
TEXT "$#REFERENCE"
RECT (1652,643,1909,678)
ALIGN 4
MARGINS (1,1)
PARENT 662
}
INSTANCE 667, 0, 0
{
VARIABLES
{
#COMPONENT="BusOutput"
#LIBRARY="#terminals"
#REFERENCE="muxb_ctl_o(1:0)"
#SYMBOL="BusOutput"
#VERILOG_TYPE="wire"
}
COORD (1600,700)
VERTEXES ( (2,4072) )
}
TEXT 668, 0, 0
{
TEXT "$#REFERENCE"
RECT (1652,683,1909,718)
ALIGN 4
MARGINS (1,1)
PARENT 667
}
INSTANCE 672, 0, 0
{
VARIABLES
{
#COMPONENT="BusOutput"
#LIBRARY="#terminals"
#REFERENCE="pc_gen_ctl_o(2:0)"
#SYMBOL="BusOutput"
#VERILOG_TYPE="wire"
}
COORD (1600,740)
VERTEXES ( (2,4074) )
}
TEXT 673, 0, 0
{
TEXT "$#REFERENCE"
RECT (1652,723,1943,758)
ALIGN 4
MARGINS (1,1)
PARENT 672
}
INSTANCE 677, 0, 0
{
VARIABLES
{
#COMPONENT="BusOutput"
#LIBRARY="#terminals"
#REFERENCE="rd_sel_o(1:0)"
#SYMBOL="BusOutput"
#VERILOG_TYPE="wire"
}
COORD (1600,780)
VERTEXES ( (2,4076) )
}
TEXT 678, 0, 0
{
TEXT "$#REFERENCE"
RECT (1652,763,1875,798)
ALIGN 4
MARGINS (1,1)
PARENT 677
}
INSTANCE 682, 0, 0
{
VARIABLES
{
#COMPONENT="BusOutput"
#LIBRARY="#terminals"
#REFERENCE="wb_mux_ctl_o(0:0)"
#SYMBOL="BusOutput"
}
COORD (1600,820)
VERTEXES ( (2,4078) )
}
TEXT 683, 0, 0
{
TEXT "$#REFERENCE"
RECT (1652,803,1943,838)
ALIGN 4
MARGINS (1,1)
PARENT 682
}
INSTANCE 687, 0, 0
{
VARIABLES
{
#COMPONENT="BusOutput"
#LIBRARY="#terminals"
#REFERENCE="wb_we_o(0:0)"
#SYMBOL="BusOutput"
}
COORD (1600,860)
VERTEXES ( (2,4080) )
}
TEXT 688, 0, 0
{
TEXT "$#REFERENCE"
RECT (1652,843,1858,878)
ALIGN 4
MARGINS (1,1)
PARENT 687
}
NET BUS 694, 0, 0
NET BUS 698, 0, 0
NET BUS 702, 0, 0
NET BUS 714, 0, 0
NET BUS 718, 0, 0
NET BUS 722, 0, 0
NET BUS 726, 0, 0
NET BUS 730, 0, 0
NET BUS 734, 0, 0
NET BUS 738, 0, 0
NET BUS 742, 0, 0
NET BUS 750, 0, 0
INSTANCE 1260, 0, 0
{
VARIABLES
{
#COMPONENT="BusOutput"
#LIBRARY="#terminals"
#REFERENCE="fsm_dly(2:0)"
#SYMBOL="BusOutput"
}
COORD (1600,1060)
VERTEXES ( (2,5812) )
}
TEXT 1261, 0, 0
{
TEXT "$#REFERENCE"
RECT (1652,1043,1858,1078)
ALIGN 4
MARGINS (1,1)
PARENT 1260
}
NET BUS 1391, 0, 0
NET WIRE 2028, 0, 0
NET BUS 2040, 0, 0
NET BUS 2048, 0, 0
NET BUS 2056, 0, 0
NET BUS 2064, 0, 0
NET BUS 2072, 0, 0
NET BUS 2086, 0, 0
NET BUS 2094, 0, 0
NET BUS 2102, 0, 0
NET BUS 2110, 0, 0
NET BUS 2118, 0, 0
NET BUS 2126, 0, 0
INSTANCE 2216, 0, 0
{
VARIABLES
{
#COMPONENT="pipelinedregs"
#LIBRARY="#default"
#REFERENCE="pipereg"
#SYMBOL="pipelinedregs"
}
COORD (1160,380)
VERTEXES ( (26,4054), (30,4055), (46,4036), (4,4057), (8,4059), (12,4061), (16,4063), (20,4065), (24,4067), (28,4069), (32,4071), (36,4073), (40,4075), (44,4077), (48,4079), (10,5361), (2,5802), (6,5804), (18,5808), (22,5810), (34,5814), (38,5816), (42,5919), (50,5927), (52,5948), (54,5976), (14,5983) )
}
TEXT 2217, 0, 0
{
TEXT "$#REFERENCE"
RECT (1160,344,1281,379)
ALIGN 8
MARGINS (1,1)
PARENT 2216
}
TEXT 2221, 0, 0
{
TEXT "$#COMPONENT"
RECT (1160,1020,1383,1055)
MARGINS (1,1)
PARENT 2216
}
INSTANCE 2281, 0, 0
{
VARIABLES
{
#COMPONENT="Input"
#LIBRARY="#terminals"
#REFERENCE="id2ra_ctl_clr"
#SYMBOL="Input"
}
COORD (740,1000)
VERTEXES ( (2,4053) )
}
TEXT 2282, 0, 0
{
TEXT "$#REFERENCE"
RECT (466,983,689,1018)
ALIGN 6
MARGINS (1,1)
PARENT 2281
}
INSTANCE 2286, 0, 0
{
VARIABLES
{
#COMPONENT="Input"
#LIBRARY="#terminals"
#REFERENCE="id2ra_ctl_cls"
#SYMBOL="Input"
}
COORD (740,1040)
VERTEXES ( (2,4056) )
}
TEXT 2287, 0, 0
{
TEXT "$#REFERENCE"
RECT (466,1023,689,1058)
ALIGN 6
MARGINS (1,1)
PARENT 2286
}
INSTANCE 2291, 0, 0
{
VARIABLES
{
#COMPONENT="Input"
#LIBRARY="#terminals"
#REFERENCE="ra2ex_ctl_clr"
#SYMBOL="Input"
}
COORD (740,1080)
VERTEXES ( (2,4035) )
}
TEXT 2292, 0, 0
{
TEXT "$#REFERENCE"
RECT (466,1063,689,1098)
ALIGN 6
MARGINS (1,1)
PARENT 2291
}
NET WIRE 2298, 0, 0
NET WIRE 2306, 0, 0
NET WIRE 2314, 0, 0
NET BUS 2344, 0, 0
VTX 4035, 0, 0
{
COORD (740,1080)
}
VTX 4036, 0, 0
{
COORD (1160,860)
}
VTX 4053, 0, 0
{
COORD (740,1000)
}
VTX 4054, 0, 0
{
COORD (1160,660)
}
VTX 4055, 0, 0
{
COORD (1160,700)
}
VTX 4056, 0, 0
{
COORD (740,1040)
}
VTX 4057, 0, 0
{
COORD (1560,420)
}
VTX 4058, 0, 0
{
COORD (1600,420)
}
VTX 4059, 0, 0
{
COORD (1560,460)
}
VTX 4060, 0, 0
{
COORD (1600,460)
}
VTX 4061, 0, 0
{
COORD (1560,500)
}
VTX 4062, 0, 0
{
COORD (1600,500)
}
VTX 4063, 0, 0
{
COORD (1560,540)
}
VTX 4064, 0, 0
{
COORD (1600,540)
}
VTX 4065, 0, 0
{
COORD (1560,580)
}
VTX 4066, 0, 0
{
COORD (1600,580)
}
VTX 4067, 0, 0
{
COORD (1560,620)
}
VTX 4068, 0, 0
{
COORD (1600,620)
}
VTX 4069, 0, 0
{
COORD (1560,660)
}
VTX 4070, 0, 0
{
COORD (1600,660)
}
VTX 4071, 0, 0
{
COORD (1560,700)
}
VTX 4072, 0, 0
{
COORD (1600,700)
}
VTX 4073, 0, 0
{
COORD (1560,740)
}
VTX 4074, 0, 0
{
COORD (1600,740)
}
VTX 4075, 0, 0
{
COORD (1560,780)
}
VTX 4076, 0, 0
{
COORD (1600,780)
}
VTX 4077, 0, 0
{
COORD (1560,820)
}
VTX 4078, 0, 0
{
COORD (1600,820)
}
VTX 4079, 0, 0
{
COORD (1560,860)
}
VTX 4080, 0, 0
{
COORD (1600,860)
}
VTX 4090, 0, 0
{
COORD (980,1080)
}
WIRE 4091, 0, 0
{
NET 2314
VTX 4035, 4090
}
VTX 4092, 0, 0
{
COORD (980,880)
}
WIRE 4093, 0, 0
{
NET 2314
VTX 4090, 4092
}
VTX 4094, 0, 0
{
COORD (1140,880)
}
WIRE 4095, 0, 0
{
NET 2314
VTX 4092, 4094
}
VTX 4096, 0, 0
{
COORD (1140,860)
}
WIRE 4097, 0, 0
{
NET 2314
VTX 4094, 4096
}
WIRE 4098, 0, 0
{
NET 2314
VTX 4096, 4036
}
VTX 4139, 0, 0
{
COORD (940,1000)
}
WIRE 4140, 0, 0
{
NET 2298
VTX 4053, 4139
}
VTX 4141, 0, 0
{
COORD (940,660)
}
WIRE 4142, 0, 0
{
NET 2298
VTX 4139, 4141
}
WIRE 4143, 0, 0
{
NET 2298
VTX 4141, 4054
}
VTX 4144, 0, 0
{
COORD (1120,700)
}
WIRE 4145, 0, 0
{
NET 2306
VTX 4055, 4144
}
VTX 4146, 0, 0
{
COORD (1120,720)
}
WIRE 4147, 0, 0
{
NET 2306
VTX 4144, 4146
}
VTX 4148, 0, 0
{
COORD (960,720)
}
WIRE 4149, 0, 0
{
NET 2306
VTX 4146, 4148
}
VTX 4150, 0, 0
{
COORD (960,1040)
}
WIRE 4151, 0, 0
{
NET 2306
VTX 4148, 4150
}
WIRE 4152, 0, 0
{
NET 2306
VTX 4150, 4056
}
BUS 4153, 0, 0
{
NET 694
VTX 4057, 4058
}
BUS 4154, 0, 0
{
NET 698
VTX 4059, 4060
}
BUS 4155, 0, 0
{
NET 702
VTX 4061, 4062
}
BUS 4156, 0, 0
{
NET 714
VTX 4063, 4064
}
BUS 4157, 0, 0
{
NET 718
VTX 4065, 4066
}
BUS 4158, 0, 0
{
NET 722
VTX 4067, 4068
}
BUS 4159, 0, 0
{
NET 726
VTX 4069, 4070
}
BUS 4160, 0, 0
{
NET 730
VTX 4071, 4072
}
BUS 4161, 0, 0
{
NET 734
VTX 4073, 4074
}
BUS 4162, 0, 0
{
NET 738
VTX 4075, 4076
}
BUS 4163, 0, 0
{
NET 742
VTX 4077, 4078
}
BUS 4164, 0, 0
{
NET 750
VTX 4079, 4080
}
VTX 5361, 0, 0
{
COORD (1160,500)
}
VTX 5362, 0, 0
{
COORD (480,360)
}
VTX 5363, 0, 0
{
COORD (1040,500)
}
WIRE 5364, 0, 0
{
NET 2028
VTX 5361, 5363
}
VTX 5365, 0, 0
{
COORD (1040,360)
}
WIRE 5366, 0, 0
{
NET 2028
VTX 5363, 5365
}
WIRE 5367, 0, 0
{
NET 2028
VTX 5365, 5362
}
INSTANCE 5632, 0, 0
{
VARIABLES
{
#COMPONENT="decoder3"
#LIBRARY="#default"
#REFERENCE="decoder"
#SYMBOL="decoder3"
}
COORD (500,380)
VERTEXES ( (2,5801), (4,5803), (6,5805), (10,5809), (12,5811), (14,5813), (16,5815), (18,5817), (20,5920), (22,5926), (24,5950), (26,5977), (8,5985) )
}
TEXT 5633, 0, 0
{
TEXT "$#REFERENCE"
RECT (500,344,621,379)
ALIGN 8
MARGINS (1,1)
PARENT 5632
}
TEXT 5637, 0, 0
{
TEXT "$#COMPONENT"
RECT (500,900,638,935)
MARGINS (1,1)
PARENT 5632
}
VTX 5800, 0, 0
{
COORD (460,460)
}
VTX 5801, 0, 0
{
COORD (500,420)
}
VTX 5802, 0, 0
{
COORD (1160,420)
}
VTX 5803, 0, 0
{
COORD (780,420)
}
VTX 5804, 0, 0
{
COORD (1160,460)
}
VTX 5805, 0, 0
{
COORD (780,460)
}
VTX 5808, 0, 0
{
COORD (1160,580)
}
VTX 5809, 0, 0
{
COORD (780,540)
}
VTX 5810, 0, 0
{
COORD (1160,620)
}
VTX 5811, 0, 0
{
COORD (780,580)
}
VTX 5812, 0, 0
{
COORD (1600,1060)
}
VTX 5813, 0, 0
{
COORD (780,620)
}
VTX 5814, 0, 0
{
COORD (1160,740)
}
VTX 5815, 0, 0
{
COORD (780,660)
}
VTX 5816, 0, 0
{
COORD (1160,780)
}
VTX 5817, 0, 0
{
COORD (780,700)
}
VTX 5826, 0, 0
{
COORD (480,460)
}
BUS 5827, 0, 0
{
NET 2344
VTX 5800, 5826
}
VTX 5828, 0, 0
{
COORD (480,420)
}
BUS 5829, 0, 0
{
NET 2344
VTX 5826, 5828
}
BUS 5830, 0, 0
{
NET 2344
VTX 5828, 5801
}
BUS 5831, 0, 0
{
NET 2040
VTX 5802, 5803
}
BUS 5832, 0, 0
{
NET 2048
VTX 5804, 5805
}
VTX 5842, 0, 0
{
COORD (1060,580)
}
BUS 5843, 0, 0
{
NET 2064
VTX 5808, 5842
}
VTX 5844, 0, 0
{
COORD (1060,540)
}
BUS 5845, 0, 0
{
NET 2064
VTX 5842, 5844
}
BUS 5846, 0, 0
{
NET 2064
VTX 5844, 5809
}
VTX 5847, 0, 0
{
COORD (1040,620)
}
BUS 5848, 0, 0
{
NET 2072
VTX 5810, 5847
}
VTX 5849, 0, 0
{
COORD (1040,580)
}
BUS 5850, 0, 0
{
NET 2072
VTX 5847, 5849
}
BUS 5851, 0, 0
{
NET 2072
VTX 5849, 5811
}
VTX 5852, 0, 0
{
COORD (1020,1060)
}
BUS 5853, 0, 0
{
NET 1391
VTX 5812, 5852
}
VTX 5854, 0, 0
{
COORD (1020,620)
}
BUS 5855, 0, 0
{
NET 1391
VTX 5852, 5854
}
BUS 5856, 0, 0
{
NET 1391
VTX 5854, 5813
}
VTX 5857, 0, 0
{
COORD (920,740)
}
BUS 5858, 0, 0
{
NET 2086
VTX 5814, 5857
}
VTX 5859, 0, 0
{
COORD (920,660)
}
BUS 5860, 0, 0
{
NET 2086
VTX 5857, 5859
}
BUS 5861, 0, 0
{
NET 2086
VTX 5859, 5815
}
VTX 5862, 0, 0
{
COORD (900,780)
}
BUS 5863, 0, 0
{
NET 2094
VTX 5816, 5862
}
VTX 5864, 0, 0
{
COORD (900,700)
}
BUS 5865, 0, 0
{
NET 2094
VTX 5862, 5864
}
BUS 5866, 0, 0
{
NET 2094
VTX 5864, 5817
}
VTX 5919, 0, 0
{
COORD (1160,820)
}
VTX 5920, 0, 0
{
COORD (780,740)
}
VTX 5921, 0, 0
{
COORD (880,820)
}
BUS 5922, 0, 0
{
NET 2102
VTX 5919, 5921
}
VTX 5923, 0, 0
{
COORD (880,740)
}
BUS 5924, 0, 0
{
NET 2102
VTX 5921, 5923
}
BUS 5925, 0, 0
{
NET 2102
VTX 5923, 5920
}
VTX 5926, 0, 0
{
COORD (780,780)
}
VTX 5927, 0, 0
{
COORD (1160,900)
}
VTX 5928, 0, 0
{
COORD (840,780)
}
BUS 5929, 0, 0
{
NET 2110
VTX 5926, 5928
}
VTX 5930, 0, 0
{
COORD (840,840)
}
BUS 5931, 0, 0
{
NET 2110
VTX 5928, 5930
}
VTX 5932, 0, 0
{
COORD (1120,840)
}
BUS 5933, 0, 0
{
NET 2110
VTX 5930, 5932
}
VTX 5934, 0, 0
{
COORD (1120,900)
}
BUS 5935, 0, 0
{
NET 2110
VTX 5932, 5934
}
BUS 5936, 0, 0
{
NET 2110
VTX 5934, 5927
}
VTX 5948, 0, 0
{
COORD (1160,940)
}
VTX 5950, 0, 0
{
COORD (780,820)
}
VTX 5951, 0, 0
{
COORD (860,940)
}
BUS 5952, 0, 0
{
NET 2118
VTX 5948, 5951
}
VTX 5953, 0, 0
{
COORD (860,860)
}
BUS 5954, 0, 0
{
NET 2118
VTX 5951, 5953
}
VTX 5956, 0, 0
{
COORD (820,820)
}
BUS 5957, 0, 0
{
NET 2118
VTX 5950, 5956
}
VTX 5958, 0, 0
{
COORD (820,860)
}
BUS 5959, 0, 0
{
NET 2118
VTX 5956, 5958
}
BUS 5961, 0, 0
{
NET 2118
VTX 5953, 5958
}
VTX 5976, 0, 0
{
COORD (1160,980)
}
VTX 5977, 0, 0
{
COORD (780,860)
}
VTX 5978, 0, 0
{
COORD (800,980)
}
BUS 5979, 0, 0
{
NET 2126
VTX 5976, 5978
}
VTX 5980, 0, 0
{
COORD (800,860)
}
BUS 5981, 0, 0
{
NET 2126
VTX 5978, 5980
}
BUS 5982, 0, 0
{
NET 2126
VTX 5980, 5977
}
VTX 5983, 0, 0
{
COORD (1160,540)
}
VTX 5984, 0, 0
{
COORD (900,500)
}
VTX 5985, 0, 0
{
COORD (780,500)
}
VTX 5986, 0, 0
{
COORD (1080,540)
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