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[/] [mips789/] [branches/] [mcupro/] [dbe/] [forward.BDE] - Rev 56

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SCHM0103

HEADER
{
 FREEID 1671
 VARIABLES
 {
  #BLOCKTABLE_FILE="#table.bde"
  #BLOCKTABLE_INCLUDED="1"
  #LANGUAGE="VERILOG"
  #MODULE="forward2"
  AUTHOR="YlmF"
  COMPANY="WwW.YlmF.CoM"
  CREATIONDATE="2008-8-10"
  TITLE="No Title"
 }
 SYMBOL "#default" "forward_node" "forward_node"
 {
  HEADER
  {
   VARIABLES
   {
    #DESCRIPTION=""
    #LANGUAGE="VERILOG"
    #MODIFIED="1218305310"
   }
  }
  PAGE "" 
  {
   PAGEHEADER
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    RECT (0,0,320,240)
    FREEID 15
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    RECT  1, -1, 0
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     VARIABLES
     {
      #OUTLINE_FILLING="1"
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    TEXT  3, 0, 0
    {
     TEXT "$#NAME"
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    }
    TEXT  5, 0, 0
    {
     TEXT "$#NAME"
     RECT (172,30,295,54)
     ALIGN 6
     MARGINS (1,1)
     PARENT 4
    }
    TEXT  7, 0, 0
    {
     TEXT "$#NAME"
     RECT (25,70,181,94)
     ALIGN 4
     MARGINS (1,1)
     PARENT 6
    }
    TEXT  9, 0, 0
    {
     TEXT "$#NAME"
     RECT (25,110,93,134)
     ALIGN 4
     MARGINS (1,1)
     PARENT 8
    }
    TEXT  11, 0, 0
    {
     TEXT "$#NAME"
     RECT (25,150,181,174)
     ALIGN 4
     MARGINS (1,1)
     PARENT 10
    }
    TEXT  13, 0, 0
    {
     TEXT "$#NAME"
     RECT (25,190,104,214)
     ALIGN 4
     MARGINS (1,1)
     PARENT 12
    }
    PIN  2, 0, 0
    {
     COORD (0,40)
     VARIABLES
     {
      #DIRECTION="IN"
      #LENGTH="20"
      #MDA_RECORD_TOKEN="OTHER"
      #NAME="alu_we"
      #NUMBER="0"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (0,0), (20,0) )
     }
    }
    PIN  4, 0, 0
    {
     COORD (320,40)
     VARIABLES
     {
      #DIRECTION="OUT"
      #DOWNTO="1"
      #LENGTH="20"
      #MDA_RECORD_TOKEN="OTHER"
      #NAME="mux_fw(2:0)"
      #NUMBER="0"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (-20,0), (0,0) )
     }
    }
    PIN  6, 0, 0
    {
     COORD (0,80)
     VARIABLES
     {
      #DIRECTION="IN"
      #DOWNTO="1"
      #LENGTH="20"
      #MDA_RECORD_TOKEN="OTHER"
      #NAME="alu_wr_rn(4:0)"
      #NUMBER="0"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (0,0), (20,0) )
     }
    }
    PIN  8, 0, 0
    {
     COORD (0,120)
     VARIABLES
     {
      #DIRECTION="IN"
      #LENGTH="20"
      #MDA_RECORD_TOKEN="OTHER"
      #NAME="mem_we"
      #NUMBER="0"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (0,0), (20,0) )
     }
    }
    PIN  10, 0, 0
    {
     COORD (0,160)
     VARIABLES
     {
      #DIRECTION="IN"
      #DOWNTO="1"
      #LENGTH="20"
      #MDA_RECORD_TOKEN="OTHER"
      #NAME="mem_wr_rn(4:0)"
      #NUMBER="0"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (0,0), (20,0) )
     }
    }
    PIN  12, 0, 0
    {
     COORD (0,200)
     VARIABLES
     {
      #DIRECTION="IN"
      #DOWNTO="1"
      #LENGTH="20"
      #MDA_RECORD_TOKEN="OTHER"
      #NAME="rn(4:0)"
      #NUMBER="0"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (0,0), (20,0) )
     }
    }
   }
  }
 }
 SYMBOL "#default" "fw_latch5" "fw_latch5"
 {
  HEADER
  {
   VARIABLES
   {
    #DESCRIPTION=""
    #LANGUAGE="VERILOG"
    #MODIFIED="1218305297"
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  }
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    RECT (0,0,160,120)
    FREEID 8
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   {
    RECT  1, -1, 0
    {
     VARIABLES
     {
      #OUTLINE_FILLING="1"
     }
     AREA (20,0,140,120)
    }
    TEXT  3, 0, 0
    {
     TEXT "$#NAME"
     RECT (25,30,60,54)
     ALIGN 4
     MARGINS (1,1)
     PARENT 2
    }
    TEXT  5, 0, 0
    {
     TEXT "$#NAME"
     RECT (67,30,135,54)
     ALIGN 6
     MARGINS (1,1)
     PARENT 4
    }
    TEXT  7, 0, 0
    {
     TEXT "$#NAME"
     RECT (25,70,93,94)
     ALIGN 4
     MARGINS (1,1)
     PARENT 6
    }
    PIN  2, 0, 0
    {
     COORD (0,40)
     VARIABLES
     {
      #DIRECTION="IN"
      #LENGTH="20"
      #MDA_RECORD_TOKEN="OTHER"
      #NAME="clk"
      #NUMBER="0"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (0,0), (20,0) )
     }
    }
    PIN  4, 0, 0
    {
     COORD (160,40)
     VARIABLES
     {
      #DIRECTION="OUT"
      #DOWNTO="1"
      #LENGTH="20"
      #MDA_RECORD_TOKEN="OTHER"
      #NAME="q(4:0)"
      #NUMBER="0"
      #VERILOG_TYPE="reg"
     }
     LINE  2, 0, 0
     {
      POINTS ( (-20,0), (0,0) )
     }
    }
    PIN  6, 0, 0
    {
     COORD (0,80)
     VARIABLES
     {
      #DIRECTION="IN"
      #DOWNTO="1"
      #LENGTH="20"
      #MDA_RECORD_TOKEN="OTHER"
      #NAME="d(4:0)"
      #NUMBER="0"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (0,0), (20,0) )
     }
    }
   }
  }
 }
}

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  INSTANCE  56, 0, 0
  {
   VARIABLES
   {
    #COMPONENT="Input"
    #LIBRARY="#terminals"
    #REFERENCE="clk"
    #SYMBOL="Input"
   }
   COORD (1180,1120)
   VERTEXES ( (2,1535) )
  }
  TEXT  57, 0, 0
  {
   TEXT "$#REFERENCE"
   RECT (1076,1103,1129,1138)
   ALIGN 6
   MARGINS (1,1)
   PARENT 56
  }
  INSTANCE  74, 0, 0
  {
   VARIABLES
   {
    #COMPONENT="forward_node"
    #LIBRARY="#default"
    #REFERENCE="fw_alu_rs"
    #SYMBOL="forward_node"
   }
   COORD (1640,400)
   VERTEXES ( (2,1491), (6,1500), (8,1506), (10,1510), (12,1486), (4,1518) )
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  TEXT  76, 0, 0
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   TEXT "$#REFERENCE"
   RECT (1640,364,1795,399)
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   PARENT 74
  }
  TEXT  77, 0, 0
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   TEXT "$#COMPONENT"
   RECT (1640,640,1846,675)
   MARGINS (1,1)
   PARENT 74
  }
  INSTANCE  78, 0, 0
  {
   VARIABLES
   {
    #COMPONENT="fw_latch5"
    #LIBRARY="#default"
    #REFERENCE="fw_reg_rns"
    #SYMBOL="fw_latch5"
   }
   COORD (1360,560)
   VERTEXES ( (2,1489), (6,1513), (4,1487) )
  }
  TEXT  80, 0, 0
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   TEXT "$#REFERENCE"
   RECT (1360,524,1532,559)
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   MARGINS (1,1)
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  TEXT  81, 0, 0
  {
   TEXT "$#COMPONENT"
   RECT (1360,680,1515,715)
   MARGINS (1,1)
   PARENT 78
  }
  NET BUS  82, 0, 0
  INSTANCE  94, 0, 0
  {
   VARIABLES
   {
    #COMPONENT="forward_node"
    #LIBRARY="#default"
    #REFERENCE="fw_cmp_rs"
    #SYMBOL="forward_node"
   }
   COORD (1640,700)
   VERTEXES ( (2,1493), (6,1499), (8,1505), (10,1512), (12,1532), (4,1534) )
  }
  TEXT  96, 0, 0
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   TEXT "$#REFERENCE"
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   ALIGN 8
   MARGINS (1,1)
   PARENT 94
  }
  TEXT  97, 0, 0
  {
   TEXT "$#COMPONENT"
   RECT (1640,940,1846,975)
   MARGINS (1,1)
   PARENT 94
  }
  INSTANCE  98, 0, 0
  {
   VARIABLES
   {
    #COMPONENT="fw_latch5"
    #LIBRARY="#default"
    #REFERENCE="fw_reg_rnt"
    #SYMBOL="fw_latch5"
   }
   COORD (1360,1180)
   VERTEXES ( (2,1490), (6,1515), (4,1537) )
  }
  TEXT  100, 0, 0
  {
   TEXT "$#REFERENCE"
   RECT (1360,1144,1532,1179)
   ALIGN 8
   MARGINS (1,1)
   PARENT 98
  }
  TEXT  101, 0, 0
  {
   TEXT "$#COMPONENT"
   RECT (1360,1300,1515,1335)
   MARGINS (1,1)
   PARENT 98
  }
  INSTANCE  119, 0, 0
  {
   VARIABLES
   {
    #COMPONENT="forward_node"
    #LIBRARY="#default"
    #REFERENCE="fw_alu_rt"
    #SYMBOL="forward_node"
   }
   COORD (1640,1020)
   VERTEXES ( (2,1496), (6,1501), (8,1507), (10,1526), (12,1536), (4,1540) )
  }
  TEXT  120, 0, 0
  {
   TEXT "$#REFERENCE"
   RECT (1640,984,1795,1019)
   ALIGN 8
   MARGINS (1,1)
   PARENT 119
  }
  TEXT  121, 0, 0
  {
   TEXT "$#COMPONENT"
   RECT (1640,1260,1846,1295)
   MARGINS (1,1)
   PARENT 119
  }
  INSTANCE  122, 0, 0
  {
   VARIABLES
   {
    #COMPONENT="forward_node"
    #LIBRARY="#default"
    #REFERENCE="fw_cmp_rt"
    #SYMBOL="forward_node"
   }
   COORD (1640,1340)
   VERTEXES ( (2,1497), (6,1503), (8,1509), (10,1531), (12,1517), (4,1520) )
  }
  TEXT  123, 0, 0
  {
   TEXT "$#REFERENCE"
   RECT (1640,1304,1795,1339)
   ALIGN 8
   MARGINS (1,1)
   PARENT 122
  }
  TEXT  124, 0, 0
  {
   TEXT "$#COMPONENT"
   RECT (1640,1580,1846,1615)
   MARGINS (1,1)
   PARENT 122
  }
  INSTANCE  303, 0, 0
  {
   VARIABLES
   {
    #COMPONENT="BusInput"
    #LIBRARY="#terminals"
    #REFERENCE="fw_alu_rn(4:0)"
    #SYMBOL="BusInput"
    #VERILOG_TYPE="wire"
   }
   COORD (1180,780)
   VERTEXES ( (2,1528) )
  }
  TEXT  304, 0, 0
  {
   TEXT "$#REFERENCE"
   RECT (889,763,1129,798)
   ALIGN 6
   MARGINS (1,1)
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  }
  INSTANCE  308, 0, 0
  {
   VARIABLES
   {
    #COMPONENT="BusInput"
    #LIBRARY="#terminals"
    #REFERENCE="fw_mem_rn(4:0)"
    #SYMBOL="BusInput"
   }
   COORD (1180,980)
   VERTEXES ( (2,1529) )
  }
  TEXT  309, 0, 0
  {
   TEXT "$#REFERENCE"
   RECT (889,963,1129,998)
   ALIGN 6
   MARGINS (1,1)
   PARENT 308
  }
  INSTANCE  313, 0, 0
  {
   VARIABLES
   {
    #COMPONENT="Input"
    #LIBRARY="#terminals"
    #REFERENCE="alu_we"
    #SYMBOL="Input"
   }
   COORD (1180,740)
   VERTEXES ( (2,1523) )
  }
  TEXT  314, 0, 0
  {
   TEXT "$#REFERENCE"
   RECT (1025,723,1129,758)
   ALIGN 6
   MARGINS (1,1)
   PARENT 313
  }
  INSTANCE  318, 0, 0
  {
   VARIABLES
   {
    #COMPONENT="Input"
    #LIBRARY="#terminals"
    #REFERENCE="mem_We"
    #SYMBOL="Input"
   }
   COORD (1180,820)
   VERTEXES ( (2,1527) )
  }
  TEXT  319, 0, 0
  {
   TEXT "$#REFERENCE"
   RECT (1025,803,1129,838)
   ALIGN 6
   MARGINS (1,1)
   PARENT 318
  }
  INSTANCE  354, 0, 0
  {
   VARIABLES
   {
    #COMPONENT="BusInput"
    #LIBRARY="#terminals"
    #REFERENCE="rnt_i(4:0)"
    #SYMBOL="BusInput"
    #VERILOG_TYPE="wire"
   }
   COORD (1180,1260)
   VERTEXES ( (2,1524) )
  }
  TEXT  355, 0, 0
  {
   TEXT "$#REFERENCE"
   RECT (957,1243,1129,1278)
   ALIGN 6
   MARGINS (1,1)
   PARENT 354
  }
  INSTANCE  359, 0, 0
  {
   VARIABLES
   {
    #COMPONENT="BusInput"
    #LIBRARY="#terminals"
    #REFERENCE="rns_i(4:0)"
    #SYMBOL="BusInput"
    #VERILOG_TYPE="wire"
   }
   COORD (1180,640)
   VERTEXES ( (2,1522) )
  }
  TEXT  360, 0, 0
  {
   TEXT "$#REFERENCE"
   RECT (957,623,1129,658)
   ALIGN 6
   MARGINS (1,1)
   PARENT 359
  }
  NET WIRE  410, 0, 0
  NET BUS  447, 0, 0
  NET WIRE  472, 0, 0
  NET BUS  550, 0, 0
  NET BUS  559, 0, 0
  INSTANCE  597, 0, 0
  {
   VARIABLES
   {
    #COMPONENT="BusOutput"
    #LIBRARY="#terminals"
    #REFERENCE="alu_rt_fw(2:0)"
    #SYMBOL="BusOutput"
    #VERILOG_TYPE="wire"
   }
   COORD (2060,1060)
   VERTEXES ( (2,1538) )
  }
  TEXT  598, 0, 0
  {
   TEXT "$#REFERENCE"
   RECT (2112,1043,2352,1078)
   ALIGN 4
   MARGINS (1,1)
   PARENT 597
  }
  INSTANCE  606, 0, 0
  {
   VARIABLES
   {
    #COMPONENT="BusOutput"
    #LIBRARY="#terminals"
    #REFERENCE="cmp_rs_fw(2:0)"
    #SYMBOL="BusOutput"
    #VERILOG_TYPE="wire"
   }
   COORD (2060,740)
   VERTEXES ( (2,1533) )
  }
  TEXT  607, 0, 0
  {
   TEXT "$#REFERENCE"
   RECT (2112,723,2352,758)
   ALIGN 4
   MARGINS (1,1)
   PARENT 606
  }
  INSTANCE  615, 0, 0
  {
   VARIABLES
   {
    #COMPONENT="BusOutput"
    #LIBRARY="#terminals"
    #REFERENCE="cmp_rt_fw(2:0)"
    #SYMBOL="BusOutput"
    #VERILOG_TYPE="wire"
   }
   COORD (2040,1380)
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  }
  TEXT  616, 0, 0
  {
   TEXT "$#REFERENCE"
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   ALIGN 4
   MARGINS (1,1)
   PARENT 615
  }
  NET BUS  620, 0, 0
  INSTANCE  624, 0, 0
  {
   VARIABLES
   {
    #COMPONENT="BusOutput"
    #LIBRARY="#terminals"
    #REFERENCE="dmem_fw(2:0)"
    #SYMBOL="BusOutput"
    #VERILOG_TYPE="wire"
   }
   COORD (2060,1200)
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  INSTANCE  633, 0, 0
  {
   VARIABLES
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    #COMPONENT="BusOutput"
    #LIBRARY="#terminals"
    #REFERENCE="alu_rs_fw(2:0)"
    #SYMBOL="BusOutput"
    #VERILOG_TYPE="wire"
   }
   COORD (2040,440)
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  {
   TEXT "$#REFERENCE"
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   MARGINS (1,1)
   PARENT 633
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  NET BUS  635, 0, 0
  NET BUS  937, 0, 0
  NET BUS  1100, 0, 0
  NET BUS  1163, 0, 0
  NET WIRE  1175, 0, 0
  NET BUS  1345, 0, 0
  VTX  1486, 0, 0
  {
   COORD (1640,600)
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  VTX  1487, 0, 0
  {
   COORD (1520,600)
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  VTX  1488, 0, 0
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   COORD (1340,1120)
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  VTX  1489, 0, 0
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   COORD (1360,600)
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  VTX  1490, 0, 0
  {
   COORD (1360,1220)
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  VTX  1491, 0, 0
  {
   COORD (1640,440)
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  VTX  1492, 0, 0
  {
   COORD (1300,740)
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  VTX  1493, 0, 0
  {
   COORD (1640,740)
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  VTX  1494, 0, 0
  {
   COORD (1460,740)
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  VTX  1495, 0, 0
  {
   COORD (1580,1060)
  }
  VTX  1496, 0, 0
  {
   COORD (1640,1060)
  }
  VTX  1497, 0, 0
  {
   COORD (1640,1380)
  }
  VTX  1498, 0, 0
  {
   COORD (1560,780)
  }
  VTX  1499, 0, 0
  {
   COORD (1640,780)
  }
  VTX  1500, 0, 0
  {
   COORD (1640,480)
  }
  VTX  1501, 0, 0
  {
   COORD (1640,1100)
  }
  VTX  1502, 0, 0
  {
   COORD (1560,1100)
  }
  VTX  1503, 0, 0
  {
   COORD (1640,1420)
  }
  VTX  1504, 0, 0
  {
   COORD (1600,820)
  }
  VTX  1505, 0, 0
  {
   COORD (1640,820)
  }
  VTX  1506, 0, 0
  {
   COORD (1640,520)
  }
  VTX  1507, 0, 0
  {
   COORD (1640,1140)
  }
  VTX  1508, 0, 0
  {
   COORD (1600,1140)
  }
  VTX  1509, 0, 0
  {
   COORD (1640,1460)
  }
  VTX  1510, 0, 0
  {
   COORD (1640,560)
  }
  VTX  1511, 0, 0
  {
   COORD (1540,860)
  }
  VTX  1512, 0, 0
  {
   COORD (1640,860)
  }
  VTX  1513, 0, 0
  {
   COORD (1360,640)
  }
  VTX  1514, 0, 0
  {
   COORD (1320,640)
  }
  VTX  1515, 0, 0
  {
   COORD (1360,1260)
  }
  VTX  1516, 0, 0
  {
   COORD (1340,1260)
  }
  VTX  1517, 0, 0
  {
   COORD (1640,1540)
  }
  VTX  1518, 0, 0
  {
   COORD (1960,440)
  }
  VTX  1519, 0, 0
  {
   COORD (2040,440)
  }
  VTX  1520, 0, 0
  {
   COORD (1960,1380)
  }
  VTX  1521, 0, 0
  {
   COORD (2040,1380)
  }
  VTX  1522, 0, 0
  {
   COORD (1180,640)
  }
  VTX  1523, 0, 0
  {
   COORD (1180,740)
  }
  VTX  1524, 0, 0
  {
   COORD (1180,1260)
  }
  VTX  1525, 0, 0
  {
   COORD (1540,980)
  }
  VTX  1526, 0, 0
  {
   COORD (1640,1180)
  }
  VTX  1527, 0, 0
  {
   COORD (1180,820)
  }
  VTX  1528, 0, 0
  {
   COORD (1180,780)
  }
  VTX  1529, 0, 0
  {
   COORD (1180,980)
  }
  VTX  1530, 0, 0
  {
   COORD (1300,980)
  }
  VTX  1531, 0, 0
  {
   COORD (1640,1500)
  }
  VTX  1532, 0, 0
  {
   COORD (1640,900)
  }
  VTX  1533, 0, 0
  {
   COORD (2060,740)
  }
  VTX  1534, 0, 0
  {
   COORD (1960,740)
  }
  VTX  1535, 0, 0
  {
   COORD (1180,1120)
  }
  VTX  1536, 0, 0
  {
   COORD (1640,1220)
  }
  VTX  1537, 0, 0
  {
   COORD (1520,1220)
  }
  VTX  1538, 0, 0
  {
   COORD (2060,1060)
  }
  VTX  1539, 0, 0
  {
   COORD (2020,1060)
  }
  VTX  1540, 0, 0
  {
   COORD (1960,1060)
  }
  VTX  1541, 0, 0
  {
   COORD (2060,1200)
  }
  BUS  1542, 0, 0
  {
   NET 82
   VTX 1486, 1487
  }
  VTX  1543, 0, 0
  {
   COORD (1340,600)
  }
  WIRE  1544, 0, 0
  {
   NET 1175
   VTX 1488, 1543
  }
  WIRE  1545, 0, 0
  {
   NET 1175
   VTX 1543, 1489
  }
  VTX  1546, 0, 0
  {
   COORD (1340,1220)
  }
  WIRE  1547, 0, 0
  {
   NET 1175
   VTX 1488, 1546
  }
  WIRE  1548, 0, 0
  {
   NET 1175
   VTX 1546, 1490
  }
  VTX  1549, 0, 0
  {
   COORD (1300,440)
  }
  WIRE  1550, 0, 0
  {
   NET 410
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  }
  WIRE  1551, 0, 0
  {
   NET 410
   VTX 1549, 1492
  }
  WIRE  1552, 0, 0
  {
   NET 410
   VTX 1493, 1494
  }
  WIRE  1553, 0, 0
  {
   NET 410
   VTX 1494, 1492
  }
  VTX  1554, 0, 0
  {
   COORD (1460,1060)
  }
  WIRE  1555, 0, 0
  {
   NET 410
   VTX 1494, 1554
  }
  WIRE  1556, 0, 0
  {
   NET 410
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  }
  WIRE  1557, 0, 0
  {
   NET 410
   VTX 1495, 1496
  }
  VTX  1558, 0, 0
  {
   COORD (1580,1380)
  }
  WIRE  1559, 0, 0
  {
   NET 410
   VTX 1495, 1558
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  WIRE  1560, 0, 0
  {
   NET 410
   VTX 1558, 1497
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  BUS  1561, 0, 0
  {
   NET 447
   VTX 1498, 1499
  }
  VTX  1562, 0, 0
  {
   COORD (1560,480)
  }
  BUS  1563, 0, 0
  {
   NET 447
   VTX 1500, 1562
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  BUS  1564, 0, 0
  {
   NET 447
   VTX 1562, 1498
  }
  BUS  1565, 0, 0
  {
   NET 447
   VTX 1501, 1502
  }
  BUS  1566, 0, 0
  {
   NET 447
   VTX 1502, 1498
  }
  VTX  1567, 0, 0
  {
   COORD (1560,1420)
  }
  BUS  1568, 0, 0
  {
   NET 447
   VTX 1503, 1567
  }
  BUS  1569, 0, 0
  {
   NET 447
   VTX 1567, 1502
  }
  WIRE  1570, 0, 0
  {
   NET 472
   VTX 1504, 1505
  }
  VTX  1571, 0, 0
  {
   COORD (1600,520)
  }
  WIRE  1572, 0, 0
  {
   NET 472
   VTX 1506, 1571
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  WIRE  1573, 0, 0
  {
   NET 472
   VTX 1571, 1504
  }
  WIRE  1574, 0, 0
  {
   NET 472
   VTX 1507, 1508
  }
  WIRE  1575, 0, 0
  {
   NET 472
   VTX 1508, 1504
  }
  VTX  1576, 0, 0
  {
   COORD (1600,1460)
  }
  WIRE  1577, 0, 0
  {
   NET 472
   VTX 1508, 1576
  }
  WIRE  1578, 0, 0
  {
   NET 472
   VTX 1576, 1509
  }
  VTX  1579, 0, 0
  {
   COORD (1540,560)
  }
  BUS  1580, 0, 0
  {
   NET 1100
   VTX 1510, 1579
  }
  BUS  1581, 0, 0
  {
   NET 1100
   VTX 1579, 1511
  }
  BUS  1582, 0, 0
  {
   NET 1100
   VTX 1512, 1511
  }
  BUS  1583, 0, 0
  {
   NET 550
   VTX 1513, 1514
  }
  BUS  1584, 0, 0
  {
   NET 559
   VTX 1515, 1516
  }
  VTX  1585, 0, 0
  {
   COORD (1340,1540)
  }
  BUS  1586, 0, 0
  {
   NET 559
   VTX 1516, 1585
  }
  BUS  1587, 0, 0
  {
   NET 559
   VTX 1585, 1517
  }
  BUS  1588, 0, 0
  {
   NET 635
   VTX 1518, 1519
  }
  BUS  1589, 0, 0
  {
   NET 620
   VTX 1520, 1521
  }
  BUS  1590, 0, 0
  {
   NET 550
   VTX 1514, 1522
  }
  WIRE  1591, 0, 0
  {
   NET 410
   VTX 1492, 1523
  }
  BUS  1592, 0, 0
  {
   NET 559
   VTX 1516, 1524
  }
  VTX  1593, 0, 0
  {
   COORD (1540,1180)
  }
  BUS  1594, 0, 0
  {
   NET 1100
   VTX 1525, 1593
  }
  BUS  1595, 0, 0
  {
   NET 1100
   VTX 1593, 1526
  }
  WIRE  1596, 0, 0
  {
   NET 472
   VTX 1504, 1527
  }
  BUS  1597, 0, 0
  {
   NET 447
   VTX 1498, 1528
  }
  BUS  1598, 0, 0
  {
   NET 1100
   VTX 1525, 1511
  }
  BUS  1599, 0, 0
  {
   NET 1100
   VTX 1529, 1530
  }
  BUS  1600, 0, 0
  {
   NET 1100
   VTX 1530, 1525
  }
  VTX  1601, 0, 0
  {
   COORD (1300,1500)
  }
  BUS  1602, 0, 0
  {
   NET 1100
   VTX 1531, 1601
  }
  BUS  1603, 0, 0
  {
   NET 1100
   VTX 1601, 1530
  }
  VTX  1604, 0, 0
  {
   COORD (1320,900)
  }
  BUS  1605, 0, 0
  {
   NET 550
   VTX 1514, 1604
  }
  BUS  1606, 0, 0
  {
   NET 550
   VTX 1604, 1532
  }
  BUS  1607, 0, 0
  {
   NET 1163
   VTX 1533, 1534
  }
  WIRE  1608, 0, 0
  {
   NET 1175
   VTX 1488, 1535
  }
  BUS  1609, 0, 0
  {
   NET 937
   VTX 1536, 1537
  }
  BUS  1610, 0, 0
  {
   NET 1345
   VTX 1538, 1539
  }
  BUS  1611, 0, 0
  {
   NET 1345
   VTX 1539, 1540
  }
  VTX  1612, 0, 0
  {
   COORD (2020,1200)
  }
  BUS  1613, 0, 0
  {
   NET 1345
   VTX 1539, 1612
  }
  BUS  1614, 0, 0
  {
   NET 1345
   VTX 1612, 1541
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