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[/] [mips789/] [branches/] [mcupro/] [verilog/] [mips_core/] [big_alu.v] - Rev 53
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///////////////////////////////////////////////////////////////////// //// Author: Liwei //// //// //// //// //// //// If you encountered any problem, please contact : //// //// Email: mcupro@yahoo.com.hk or mcupro@opencores.org //// //// //// //// Downloaded from: //// //// http://www.opencores.org/pdownloads.cgi/list/mips789 //// ///////////////////////////////////////////////////////////////////// //// //// //// Copyright (C) 2006-2007 Liwei //// //// mcupro@yahoo.com.hk //// //// //// //// //// //// This source file may be used and distributed freely without //// //// restriction provided that this copyright statement is not //// //// removed from the file and any derivative work contains the //// //// original copyright notice and the associated disclaimer. //// //// //// //// Please let the author know if it is used //// //// for commercial purpose. //// //// //// //// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// //// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// //// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// //// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// //// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// //// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// //// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// //// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// //// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// //// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// //// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// //// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// //// POSSIBILITY OF SUCH DAMAGE. //// //// //// ///////////////////////////////////////////////////////////////////// //// //// //// //// //// Date of Creation: 2007.8.1 //// //// //// //// Version: 0.0.1 //// //// //// //// Description: //// //// //// //// //// ///////////////////////////////////////////////////////////////////// //// //// //// Change log: //// //// //// ///////////////////////////////////////////////////////////////////// module big_alu(clk,rst,a,b,c,ctl,busy); input clk,rst ; input [31:0] a,b ; output [31:0] c ; output busy ; input [4:0]ctl ; wire [31:0] mul_div_c; wire [31:0] alu_c; wire [31:0] shift_c; assign c =mul_div_c | alu_c | shift_c ;//save the pc to register /* muldiv_ff muldiv_ff( .clk_i(clk), .rst_i(rst),//sys signal .op_type(ctl), .op1(a), .op2(b), // .busy_o(busy), .res(mul_div_c) ); */ muldiv mips_muldiv( .ready(busy), .rst(rst), .op1(a), .op2(b), .clk(clk), .dout(mul_div_c), .func(ctl) ); alu mips_alu( .a(a), .b(b), .alu_out(alu_c), .alu_func(ctl) ); shifter mips_shifter( .a(b), .shift_out(shift_c), .shift_func(ctl), .shift_amount(a) ); endmodule
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