Subversion Repositories mips789

SCHM0103

HEADER
{
 FREEID 3011
 VARIABLES
 {
  #BLOCKTABLE_FILE="#table.bde"
  #BLOCKTABLE_INCLUDED="1"
  #LANGUAGE="VERILOG"
  #MODULE="mips_top123"
  AUTHOR="YlmF"
  COMPANY="WwW.YlmF.CoM"
  CREATIONDATE="2008-8-13"
  TITLE="No Title"
 }
 SYMBOL "#default" "mem_array" "mem_array"
 {
  HEADER
  {
   VARIABLES
   {
    #DESCRIPTION=""
    #LANGUAGE="VERILOG"
    #MODIFIED="1218631627"
   }
  }
  PAGE "" 
  {
   PAGEHEADER
   {
    RECT (0,0,300,280)
    FREEID 19
   }
   
   BODY
   {
    RECT  1, -1, 0
    {
     VARIABLES
     {
      #OUTLINE_FILLING="1"
     }
     AREA (20,0,280,280)
    }
    TEXT  3, 0, 0
    {
     TEXT "$#NAME"
     RECT (25,30,60,54)
     ALIGN 4
     MARGINS (1,1)
     PARENT 2
    }
    TEXT  5, 0, 0
    {
     TEXT "$#NAME"
     RECT (163,30,275,54)
     ALIGN 6
     MARGINS (1,1)
     PARENT 4
    }
    TEXT  7, 0, 0
    {
     TEXT "$#NAME"
     RECT (25,70,126,94)
     ALIGN 4
     MARGINS (1,1)
     PARENT 6
    }
    TEXT  9, 0, 0
    {
     TEXT "$#NAME"
     RECT (152,70,275,94)
     ALIGN 6
     MARGINS (1,1)
     PARENT 8
    }
    TEXT  11, 0, 0
    {
     TEXT "$#NAME"
     RECT (25,110,137,134)
     ALIGN 4
     MARGINS (1,1)
     PARENT 10
    }
    TEXT  13, 0, 0
    {
     TEXT "$#NAME"
     RECT (25,150,192,174)
     ALIGN 4
     MARGINS (1,1)
     PARENT 12
    }
    TEXT  15, 0, 0
    {
     TEXT "$#NAME"
     RECT (25,190,192,214)
     ALIGN 4
     MARGINS (1,1)
     PARENT 14
    }
    TEXT  17, 0, 0
    {
     TEXT "$#NAME"
     RECT (25,230,126,254)
     ALIGN 4
     MARGINS (1,1)
     PARENT 16
    }
    PIN  2, 0, 0
    {
     COORD (0,40)
     VARIABLES
     {
      #DIRECTION="IN"
      #LENGTH="20"
      #MDA_RECORD_TOKEN="OTHER"
      #NAME="clk"
      #NUMBER="0"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (0,0), (20,0) )
     }
    }
    PIN  4, 0, 0
    {
     COORD (300,40)
     VARIABLES
     {
      #DIRECTION="OUT"
      #DOWNTO="1"
      #LENGTH="20"
      #MDA_RECORD_TOKEN="OTHER"
      #NAME="dout(31:0)"
      #NUMBER="0"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (-20,0), (0,0) )
     }
    }
    PIN  6, 0, 0
    {
     COORD (0,80)
     VARIABLES
     {
      #DIRECTION="IN"
      #DOWNTO="1"
      #LENGTH="20"
      #MDA_RECORD_TOKEN="OTHER"
      #NAME="din(31:0)"
      #NUMBER="0"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (0,0), (20,0) )
     }
    }
    PIN  8, 0, 0
    {
     COORD (300,80)
     VARIABLES
     {
      #DIRECTION="OUT"
      #DOWNTO="1"
      #LENGTH="20"
      #MDA_RECORD_TOKEN="OTHER"
      #NAME="ins_o(31:0)"
      #NUMBER="0"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (-20,0), (0,0) )
     }
    }
    PIN  10, 0, 0
    {
     COORD (0,120)
     VARIABLES
     {
      #DIRECTION="IN"
      #DOWNTO="1"
      #LENGTH="20"
      #MDA_RECORD_TOKEN="OTHER"
      #NAME="pc_i(31:0)"
      #NUMBER="0"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (0,0), (20,0) )
     }
    }
    PIN  12, 0, 0
    {
     COORD (0,160)
     VARIABLES
     {
      #DIRECTION="IN"
      #DOWNTO="1"
      #LENGTH="20"
      #MDA_RECORD_TOKEN="OTHER"
      #NAME="rd_addr_i(31:0)"
      #NUMBER="0"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (0,0), (20,0) )
     }
    }
    PIN  14, 0, 0
    {
     COORD (0,200)
     VARIABLES
     {
      #DIRECTION="IN"
      #DOWNTO="1"
      #LENGTH="20"
      #MDA_RECORD_TOKEN="OTHER"
      #NAME="wr_addr_i(31:0)"
      #NUMBER="0"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (0,0), (20,0) )
     }
    }
    PIN  16, 0, 0
    {
     COORD (0,240)
     VARIABLES
     {
      #DIRECTION="IN"
      #DOWNTO="1"
      #LENGTH="20"
      #MDA_RECORD_TOKEN="OTHER"
      #NAME="wren(3:0)"
      #NUMBER="0"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (0,0), (20,0) )
     }
    }
   }
  }
 }
 SYMBOL "#default" "mips_seg7led" "mips_seg7led"
 {
  HEADER
  {
   VARIABLES
   {
    #DESCRIPTION=""
    #LANGUAGE="VERILOG"
    #MODIFIED="1218632224"
   }
  }
  PAGE "" 
  {
   PAGEHEADER
   {
    RECT (0,0,400,240)
    FREEID 17
   }
   
   BODY
   {
    RECT  1, -1, 0
    {
     VARIABLES
     {
      #OUTLINE_FILLING="1"
     }
     AREA (20,0,380,240)
    }
    TEXT  3, 0, 0
    {
     TEXT "$#NAME"
     RECT (25,30,159,54)
     ALIGN 4
     MARGINS (1,1)
     PARENT 2
    }
    TEXT  5, 0, 0
    {
     TEXT "$#NAME"
     RECT (230,30,375,54)
     ALIGN 6
     MARGINS (1,1)
     PARENT 4
    }
    TEXT  7, 0, 0
    {
     TEXT "$#NAME"
     RECT (25,70,60,94)
     ALIGN 4
     MARGINS (1,1)
     PARENT 6
    }
    TEXT  9, 0, 0
    {
     TEXT "$#NAME"
     RECT (230,70,375,94)
     ALIGN 6
     MARGINS (1,1)
     PARENT 8
    }
    TEXT  11, 0, 0
    {
     TEXT "$#NAME"
     RECT (25,110,126,134)
     ALIGN 4
     MARGINS (1,1)
     PARENT 10
    }
    TEXT  13, 0, 0
    {
     TEXT "$#NAME"
     RECT (25,150,192,174)
     ALIGN 4
     MARGINS (1,1)
     PARENT 12
    }
    TEXT  15, 0, 0
    {
     TEXT "$#NAME"
     RECT (25,190,60,214)
     ALIGN 4
     MARGINS (1,1)
     PARENT 14
    }
    PIN  2, 0, 0
    {
     COORD (0,40)
     VARIABLES
     {
      #DIRECTION="IN"
      #DOWNTO="1"
      #LENGTH="20"
      #MDA_RECORD_TOKEN="OTHER"
      #NAME="addr_i(31:0)"
      #NUMBER="0"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (0,0), (20,0) )
     }
    }
    PIN  4, 0, 0
    {
     COORD (400,40)
     VARIABLES
     {
      #DIRECTION="OUT"
      #DOWNTO="1"
      #LENGTH="20"
      #MDA_RECORD_TOKEN="OTHER"
      #NAME="seg7led1(6:0)"
      #NUMBER="0"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (-20,0), (0,0) )
     }
    }
    PIN  6, 0, 0
    {
     COORD (0,80)
     VARIABLES
     {
      #DIRECTION="IN"
      #LENGTH="20"
      #MDA_RECORD_TOKEN="OTHER"
      #NAME="clk"
      #NUMBER="0"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (0,0), (20,0) )
     }
    }
    PIN  8, 0, 0
    {
     COORD (400,80)
     VARIABLES
     {
      #DIRECTION="OUT"
      #DOWNTO="1"
      #LENGTH="20"
      #MDA_RECORD_TOKEN="OTHER"
      #NAME="seg7led2(6:0)"
      #NUMBER="0"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (-20,0), (0,0) )
     }
    }
    PIN  10, 0, 0
    {
     COORD (0,120)
     VARIABLES
     {
      #DIRECTION="IN"
      #DOWNTO="1"
      #LENGTH="20"
      #MDA_RECORD_TOKEN="OTHER"
      #NAME="din(31:0)"
      #NUMBER="0"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (0,0), (20,0) )
     }
    }
    PIN  12, 0, 0
    {
     COORD (0,160)
     VARIABLES
     {
      #DIRECTION="IN"
      #DOWNTO="1"
      #LENGTH="20"
      #MDA_RECORD_TOKEN="OTHER"
      #NAME="dmem_ctl_i(3:0)"
      #NUMBER="0"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (0,0), (20,0) )
     }
    }
    PIN  14, 0, 0
    {
     COORD (0,200)
     VARIABLES
     {
      #DIRECTION="IN"
      #LENGTH="20"
      #MDA_RECORD_TOKEN="OTHER"
      #NAME="rst"
      #NUMBER="0"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (0,0), (20,0) )
     }
    }
   }
  }
 }
 SYMBOL "#default" "mips_core1" "mips_core1"
 {
  HEADER
  {
   VARIABLES
   {
    #DESCRIPTION=""
    #LANGUAGE="VERILOG"
    #MODIFIED="1218631794"
   }
  }
  PAGE "" 
  {
   PAGEHEADER
   {
    RECT (0,0,440,360)
    FREEID 33
   }
   
   BODY
   {
    RECT  1, -1, 0
    {
     VARIABLES
     {
      #OUTLINE_FILLING="1"
     }
     AREA (20,0,420,360)
    }
    TEXT  3, 0, 0
    {
     TEXT "$#NAME"
     RECT (25,30,60,54)
     ALIGN 4
     MARGINS (1,1)
     PARENT 2
    }
    TEXT  5, 0, 0
    {
     TEXT "$#NAME"
     RECT (237,30,415,54)
     ALIGN 6
     MARGINS (1,1)
     PARENT 4
    }
    TEXT  7, 0, 0
    {
     TEXT "$#NAME"
     RECT (25,70,181,94)
     ALIGN 4
     MARGINS (1,1)
     PARENT 6
    }
    TEXT  9, 0, 0
    {
     TEXT "$#NAME"
     RECT (237,70,415,94)
     ALIGN 6
     MARGINS (1,1)
     PARENT 8
    }
    TEXT  11, 0, 0
    {
     TEXT "$#NAME"
     RECT (25,110,181,134)
     ALIGN 4
     MARGINS (1,1)
     PARENT 10
    }
    TEXT  13, 0, 0
    {
     TEXT "$#NAME"
     RECT (215,110,415,134)
     ALIGN 6
     MARGINS (1,1)
     PARENT 12
    }
    TEXT  15, 0, 0
    {
     TEXT "$#NAME"
     RECT (25,150,82,174)
     ALIGN 4
     MARGINS (1,1)
     PARENT 14
    }
    TEXT  17, 0, 0
    {
     TEXT "$#NAME"
     RECT (347,150,415,174)
     ALIGN 6
     MARGINS (1,1)
     PARENT 16
    }
    TEXT  19, 0, 0
    {
     TEXT "$#NAME"
     RECT (25,190,60,214)
     ALIGN 4
     MARGINS (1,1)
     PARENT 18
    }
    TEXT  21, 0, 0
    {
     TEXT "$#NAME"
     RECT (248,190,415,214)
     ALIGN 6
     MARGINS (1,1)
     PARENT 20
    }
    TEXT  23, 0, 0
    {
     TEXT "$#NAME"
     RECT (25,230,159,254)
     ALIGN 4
     MARGINS (1,1)
     PARENT 22
    }
    TEXT  25, 0, 0
    {
     TEXT "$#NAME"
     RECT (270,230,415,254)
     ALIGN 6
     MARGINS (1,1)
     PARENT 24
    }
    TEXT  27, 0, 0
    {
     TEXT "$#NAME"
     RECT (25,270,181,294)
     ALIGN 4
     MARGINS (1,1)
     PARENT 26
    }
    TEXT  29, 0, 0
    {
     TEXT "$#NAME"
     RECT (270,270,415,294)
     ALIGN 6
     MARGINS (1,1)
     PARENT 28
    }
    TEXT  31, 0, 0
    {
     TEXT "$#NAME"
     RECT (248,310,415,334)
     ALIGN 6
     MARGINS (1,1)
     PARENT 30
    }
    PIN  2, 0, 0
    {
     COORD (0,40)
     VARIABLES
     {
      #DIRECTION="IN"
      #LENGTH="20"
      #MDA_RECORD_TOKEN="OTHER"
      #NAME="clk"
      #NUMBER="0"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (0,0), (20,0) )
     }
    }
    PIN  4, 0, 0
    {
     COORD (440,40)
     VARIABLES
     {
      #DIRECTION="OUT"
      #DOWNTO="1"
      #LENGTH="20"
      #MDA_RECORD_TOKEN="OTHER"
      #NAME="cop_addr_o(31:0)"
      #NUMBER="0"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (-20,0), (0,0) )
     }
    }
    PIN  6, 0, 0
    {
     COORD (0,80)
     VARIABLES
     {
      #DIRECTION="IN"
      #DOWNTO="1"
      #LENGTH="20"
      #MDA_RECORD_TOKEN="OTHER"
      #NAME="cop_dout(31:0)"
      #NUMBER="0"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (0,0), (20,0) )
     }
    }
    PIN  8, 0, 0
    {
     COORD (440,80)
     VARIABLES
     {
      #DIRECTION="OUT"
      #DOWNTO="1"
      #LENGTH="20"
      #MDA_RECORD_TOKEN="OTHER"
      #NAME="cop_data_o(31:0)"
      #NUMBER="0"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (-20,0), (0,0) )
     }
    }
    PIN  10, 0, 0
    {
     COORD (0,120)
     VARIABLES
     {
      #DIRECTION="IN"
      #DOWNTO="1"
      #LENGTH="20"
      #MDA_RECORD_TOKEN="OTHER"
      #NAME="irq_addr(31:0)"
      #NUMBER="0"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (0,0), (20,0) )
     }
    }
    PIN  12, 0, 0
    {
     COORD (440,120)
     VARIABLES
     {
      #DIRECTION="OUT"
      #DOWNTO="1"
      #LENGTH="20"
      #MDA_RECORD_TOKEN="OTHER"
      #NAME="cop_mem_ctl_o(3:0)"
      #NUMBER="0"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (-20,0), (0,0) )
     }
    }
    PIN  14, 0, 0
    {
     COORD (0,160)
     VARIABLES
     {
      #DIRECTION="IN"
      #LENGTH="20"
      #MDA_RECORD_TOKEN="OTHER"
      #NAME="irq_i"
      #NUMBER="0"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (0,0), (20,0) )
     }
    }
    PIN  16, 0, 0
    {
     COORD (440,160)
     VARIABLES
     {
      #DIRECTION="OUT"
      #LENGTH="20"
      #MDA_RECORD_TOKEN="OTHER"
      #NAME="iack_o"
      #NUMBER="0"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (-20,0), (0,0) )
     }
    }
    PIN  18, 0, 0
    {
     COORD (0,200)
     VARIABLES
     {
      #DIRECTION="IN"
      #LENGTH="20"
      #MDA_RECORD_TOKEN="OTHER"
      #NAME="rst"
      #NUMBER="0"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (0,0), (20,0) )
     }
    }
    PIN  20, 0, 0
    {
     COORD (440,200)
     VARIABLES
     {
      #DIRECTION="OUT"
      #DOWNTO="1"
      #LENGTH="20"
      #MDA_RECORD_TOKEN="OTHER"
      #NAME="zz_addr_o(31:0)"
      #NUMBER="0"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (-20,0), (0,0) )
     }
    }
    PIN  22, 0, 0
    {
     COORD (0,240)
     VARIABLES
     {
      #DIRECTION="IN"
      #DOWNTO="1"
      #LENGTH="20"
      #MDA_RECORD_TOKEN="OTHER"
      #NAME="zz_din(31:0)"
      #NUMBER="0"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (0,0), (20,0) )
     }
    }
    PIN  24, 0, 0
    {
     COORD (440,240)
     VARIABLES
     {
      #DIRECTION="OUT"
      #DOWNTO="1"
      #LENGTH="20"
      #MDA_RECORD_TOKEN="OTHER"
      #NAME="zz_dout(31:0)"
      #NUMBER="0"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (-20,0), (0,0) )
     }
    }
    PIN  26, 0, 0
    {
     COORD (0,280)
     VARIABLES
     {
      #DIRECTION="IN"
      #DOWNTO="1"
      #LENGTH="20"
      #MDA_RECORD_TOKEN="OTHER"
      #NAME="zz_ins_i(31:0)"
      #NUMBER="0"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (0,0), (20,0) )
     }
    }
    PIN  28, 0, 0
    {
     COORD (440,280)
     VARIABLES
     {
      #DIRECTION="OUT"
      #DOWNTO="1"
      #LENGTH="20"
      #MDA_RECORD_TOKEN="OTHER"
      #NAME="zz_pc_o(31:0)"
      #NUMBER="0"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (-20,0), (0,0) )
     }
    }
    PIN  30, 0, 0
    {
     COORD (440,320)
     VARIABLES
     {
      #DIRECTION="OUT"
      #DOWNTO="1"
      #LENGTH="20"
      #MDA_RECORD_TOKEN="OTHER"
      #NAME="zz_wr_en_o(3:0)"
      #NUMBER="0"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (-20,0), (0,0) )
     }
    }
   }
  }
 }
}

PAGE ""
{
 PAGEHEADER
 {
  PAGESIZE (2200,1700)
  MARGINS (200,200,200,200)
  RECT (0,0,100,200)
 }
 
 BODY
 {
  INSTANCE  678, 0, 0
  {
   VARIABLES
   {
    #COMPONENT="mem_array"
    #LIBRARY="#default"
    #REFERENCE="ram_4k"
    #SYMBOL="mem_array"
   }
   COORD (1380,800)
   VERTEXES ( (2,2127), (6,2152), (10,2154), (12,2118), (14,2119), (16,2146), (8,2123), (4,2336) )
  }
  TEXT  679, 0, 0
  {
   TEXT "$#REFERENCE"
   RECT (1380,764,1484,799)
   ALIGN 8
   MARGINS (1,1)
   PARENT 678
  }
  TEXT  683, 0, 0
  {
   TEXT "$#COMPONENT"
   RECT (1380,1080,1535,1115)
   MARGINS (1,1)
   PARENT 678
  }
  INSTANCE  786, 0, 0
  {
   VARIABLES
   {
    #COMPONENT="Input"
    #LIBRARY="#terminals"
    #REFERENCE="clk"
    #SYMBOL="Input"
   }
   COORD (520,680)
   VERTEXES ( (2,2138) )
  }
  TEXT  787, 0, 0
  {
   TEXT "$#REFERENCE"
   RECT (416,663,469,698)
   ALIGN 6
   MARGINS (1,1)
   PARENT 786
  }
  INSTANCE  808, 0, 0
  {
   VARIABLES
   {
    #COMPONENT="Input"
    #LIBRARY="#terminals"
    #REFERENCE="rst"
    #SYMBOL="Input"
   }
   COORD (520,920)
   VERTEXES ( (2,2132) )
  }
  TEXT  809, 0, 0
  {
   TEXT "$#REFERENCE"
   RECT (416,903,469,938)
   ALIGN 6
   MARGINS (1,1)
   PARENT 808
  }
  INSTANCE  940, 0, 0
  {
   VARIABLES
   {
    #COMPONENT="Input"
    #LIBRARY="#terminals"
    #REFERENCE="key2"
    #SYMBOL="Input"
   }
   COORD (520,880)
   VERTEXES ( (2,2125) )
  }
  TEXT  941, 0, 0
  {
   TEXT "$#REFERENCE"
   RECT (399,863,469,898)
   ALIGN 6
   MARGINS (1,1)
   PARENT 940
  }
  NET WIRE  945, 0, 0
  INSTANCE  1285, 0, 0
  {
   VARIABLES
   {
    #COMPONENT="mips_seg7led"
    #LIBRARY="#default"
    #REFERENCE="seg7led"
    #SYMBOL="mips_seg7led"
   }
   COORD (1200,380)
   VERTEXES ( (6,2139), (14,2137), (4,2134), (8,2136), (2,2850), (10,2885), (12,2892) )
  }
  TEXT  1286, 0, 0
  {
   TEXT "$#REFERENCE"
   RECT (1200,344,1321,379)
   ALIGN 8
   MARGINS (1,1)
   PARENT 1285
  }
  TEXT  1290, 0, 0
  {
   TEXT "$#COMPONENT"
   RECT (1200,620,1406,655)
   MARGINS (1,1)
   PARENT 1285
  }
  NET BUS  1338, 0, 0
  NET BUS  1342, 0, 0
  INSTANCE  1344, 0, 0
  {
   VARIABLES
   {
    #COMPONENT="BusOutput"
    #LIBRARY="#terminals"
    #REFERENCE="seg7led1(6:0)"
    #SYMBOL="BusOutput"
   }
   COORD (1660,420)
   VERTEXES ( (2,2133) )
  }
  TEXT  1345, 0, 0
  {
   TEXT "$#REFERENCE"
   RECT (1712,403,1935,438)
   ALIGN 4
   MARGINS (1,1)
   PARENT 1344
  }
  INSTANCE  1349, 0, 0
  {
   VARIABLES
   {
    #COMPONENT="BusOutput"
    #LIBRARY="#terminals"
    #REFERENCE="seg7led2(6:0)"
    #SYMBOL="BusOutput"
   }
   COORD (1660,460)
   VERTEXES ( (2,2135) )
  }
  TEXT  1350, 0, 0
  {
   TEXT "$#REFERENCE"
   RECT (1712,443,1935,478)
   ALIGN 4
   MARGINS (1,1)
   PARENT 1349
  }
  NET WIRE  1367, 0, 0
  NET WIRE  1376, 0, 0
  INSTANCE  1698, 0, 0
  {
   VARIABLES
   {
    #COMPONENT="mips_core1"
    #LIBRARY="#default"
    #REFERENCE="mips_core_"
    #SYMBOL="mips_core1"
   }
   COORD (620,720)
   VERTEXES ( (2,2129), (6,2148), (10,2150), (14,2124), (18,2130), (26,2122), (20,2156), (24,2153), (28,2155), (30,2147), (22,2335), (4,2851), (8,2886), (12,2893) )
  }
  TEXT  1699, 0, 0
  {
   TEXT "$#REFERENCE"
   RECT (620,684,792,719)
   ALIGN 8
   MARGINS (1,1)
   PARENT 1698
  }
  TEXT  1703, 0, 0
  {
   TEXT "$#COMPONENT"
   RECT (660,1080,832,1115)
   MARGINS (1,1)
   PARENT 1698
  }
  NET BUS  2014, 0, 0
  NET BUS  2018, 0, 0
  INSTANCE  2020, 0, 0
  {
   VARIABLES
   {
    #COMPONENT="BusInput"
    #LIBRARY="#terminals"
    #REFERENCE="cop_data(31:0)"
    #SYMBOL="BusInput"
   }
   COORD (520,800)
   VERTEXES ( (2,2149) )
  }
  TEXT  2021, 0, 0
  {
   TEXT "$#REFERENCE"
   RECT (229,783,469,818)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2020
  }
  INSTANCE  2025, 0, 0
  {
   VARIABLES
   {
    #COMPONENT="BusInput"
    #LIBRARY="#terminals"
    #REFERENCE="irq_addr(31:0)"
    #SYMBOL="BusInput"
   }
   COORD (520,840)
   VERTEXES ( (2,2151) )
  }
  TEXT  2026, 0, 0
  {
   TEXT "$#REFERENCE"
   RECT (229,823,469,858)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2025
  }
  VTX  2117, 0, 0
  {
   COORD (1360,960)
  }
  VTX  2118, 0, 0
  {
   COORD (1380,960)
  }
  VTX  2119, 0, 0
  {
   COORD (1380,1000)
  }
  VTX  2122, 0, 0
  {
   COORD (620,1000)
  }
  VTX  2123, 0, 0
  {
   COORD (1680,880)
  }
  VTX  2124, 0, 0
  {
   COORD (620,880)
  }
  VTX  2125, 0, 0
  {
   COORD (520,880)
  }
  VTX  2126, 0, 0
  {
   COORD (640,680)
  }
  VTX  2127, 0, 0
  {
   COORD (1380,840)
  }
  VTX  2128, 0, 0
  {
   COORD (620,680)
  }
  VTX  2129, 0, 0
  {
   COORD (620,760)
  }
  VTX  2130, 0, 0
  {
   COORD (620,920)
  }
  VTX  2131, 0, 0
  {
   COORD (600,920)
  }
  VTX  2132, 0, 0
  {
   COORD (520,920)
  }
  VTX  2133, 0, 0
  {
   COORD (1660,420)
  }
  VTX  2134, 0, 0
  {
   COORD (1600,420)
  }
  VTX  2135, 0, 0
  {
   COORD (1660,460)
  }
  VTX  2136, 0, 0
  {
   COORD (1600,460)
  }
  VTX  2137, 0, 0
  {
   COORD (1200,580)
  }
  VTX  2138, 0, 0
  {
   COORD (520,680)
  }
  VTX  2139, 0, 0
  {
   COORD (1200,460)
  }
  VTX  2146, 0, 0
  {
   COORD (1380,1040)
  }
  VTX  2147, 0, 0
  {
   COORD (1060,1040)
  }
  VTX  2148, 0, 0
  {
   COORD (620,800)
  }
  VTX  2149, 0, 0
  {
   COORD (520,800)
  }
  VTX  2150, 0, 0
  {
   COORD (620,840)
  }
  VTX  2151, 0, 0
  {
   COORD (520,840)
  }
  VTX  2152, 0, 0
  {
   COORD (1380,880)
  }
  VTX  2153, 0, 0
  {
   COORD (1060,960)
  }
  VTX  2154, 0, 0
  {
   COORD (1380,920)
  }
  VTX  2155, 0, 0
  {
   COORD (1060,1000)
  }
  VTX  2156, 0, 0
  {
   COORD (1060,920)
  }
  BUS  2157, 0, 0
  {
   NET 2557
   VTX 2117, 2118
  }
  VTX  2158, 0, 0
  {
   COORD (1360,1000)
  }
  BUS  2159, 0, 0
  {
   NET 2557
   VTX 2117, 2158
  }
  BUS  2160, 0, 0
  {
   NET 2557
   VTX 2158, 2119
  }
  VTX  2170, 0, 0
  {
   COORD (610,1000)
  }
  BUS  2171, 0, 0
  {
   NET 2560
   VTX 2122, 2170
  }
  VTX  2172, 0, 0
  {
   COORD (610,1100)
  }
  BUS  2173, 0, 0
  {
   NET 2560
   VTX 2170, 2172
  }
  VTX  2174, 0, 0
  {
   COORD (1700,1100)
  }
  BUS  2175, 0, 0
  {
   NET 2560
   VTX 2172, 2174
   VARIABLES
   {
    #NAMED="1"
   }
  }
  VTX  2176, 0, 0
  {
   COORD (1700,880)
  }
  BUS  2177, 0, 0
  {
   NET 2560
   VTX 2174, 2176
  }
  BUS  2178, 0, 0
  {
   NET 2560
   VTX 2176, 2123
  }
  WIRE  2179, 0, 0
  {
   NET 945
   VTX 2124, 2125
  }
  VTX  2180, 0, 0
  {
   COORD (1340,680)
  }
  WIRE  2181, 0, 0
  {
   NET 1376
   VTX 2126, 2180
  }
  VTX  2182, 0, 0
  {
   COORD (1340,840)
  }
  WIRE  2183, 0, 0
  {
   NET 1376
   VTX 2180, 2182
  }
  WIRE  2184, 0, 0
  {
   NET 1376
   VTX 2182, 2127
  }
  WIRE  2185, 0, 0
  {
   NET 1376
   VTX 2128, 2129
  }
  WIRE  2186, 0, 0
  {
   NET 1367
   VTX 2130, 2131
  }
  WIRE  2187, 0, 0
  {
   NET 1367
   VTX 2131, 2132
  }
  BUS  2188, 0, 0
  {
   NET 1338
   VTX 2133, 2134
  }
  BUS  2189, 0, 0
  {
   NET 1342
   VTX 2135, 2136
  }
  VTX  2190, 0, 0
  {
   COORD (600,580)
  }
  WIRE  2191, 0, 0
  {
   NET 1367
   VTX 2131, 2190
  }
  WIRE  2192, 0, 0
  {
   NET 1367
   VTX 2190, 2137
  }
  WIRE  2193, 0, 0
  {
   NET 1376
   VTX 2138, 2128
  }
  VTX  2194, 0, 0
  {
   COORD (640,460)
  }
  WIRE  2195, 0, 0
  {
   NET 1376
   VTX 2139, 2194
  }
  WIRE  2196, 0, 0
  {
   NET 1376
   VTX 2194, 2126
  }
  WIRE  2197, 0, 0
  {
   NET 1376
   VTX 2126, 2128
  }
  BUS  2217, 0, 0
  {
   NET 2559
   VTX 2146, 2147
   VARIABLES
   {
    #NAMED="1"
   }
  }
  BUS  2218, 0, 0
  {
   NET 2014
   VTX 2148, 2149
  }
  BUS  2219, 0, 0
  {
   NET 2018
   VTX 2150, 2151
  }
  VTX  2220, 0, 0
  {
   COORD (1120,880)
  }
  BUS  2221, 0, 0
  {
   NET 2426
   VTX 2152, 2220
   VARIABLES
   {
    #NAMED="1"
   }
  }
  VTX  2222, 0, 0
  {
   COORD (1120,960)
  }
  BUS  2223, 0, 0
  {
   NET 2426
   VTX 2220, 2222
  }
  BUS  2224, 0, 0
  {
   NET 2426
   VTX 2222, 2153
  }
  VTX  2225, 0, 0
  {
   COORD (1280,920)
  }
  BUS  2226, 0, 0
  {
   NET 2558
   VTX 2154, 2225
  }
  VTX  2227, 0, 0
  {
   COORD (1280,1000)
  }
  BUS  2228, 0, 0
  {
   NET 2558
   VTX 2225, 2227
  }
  BUS  2229, 0, 0
  {
   NET 2558
   VTX 2227, 2155
   VARIABLES
   {
    #NAMED="1"
   }
  }
  VTX  2230, 0, 0
  {
   COORD (1200,960)
  }
  BUS  2231, 0, 0
  {
   NET 2557
   VTX 2117, 2230
  }
  VTX  2232, 0, 0
  {
   COORD (1200,920)
  }
  BUS  2233, 0, 0
  {
   NET 2557
   VTX 2230, 2232
  }
  BUS  2234, 0, 0
  {
   NET 2557
   VTX 2232, 2156
   VARIABLES
   {
    #NAMED="1"
   }
  }
  VTX  2335, 0, 0
  {
   COORD (620,960)
  }
  VTX  2336, 0, 0
  {
   COORD (1680,840)
  }
  VTX  2337, 0, 0
  {
   COORD (580,960)
  }
  BUS  2338, 0, 0
  {
   NET 2561
   VTX 2335, 2337
  }
  VTX  2339, 0, 0
  {
   COORD (580,1120)
  }
  BUS  2340, 0, 0
  {
   NET 2561
   VTX 2337, 2339
  }
  VTX  2341, 0, 0
  {
   COORD (1720,1120)
  }
  BUS  2342, 0, 0
  {
   NET 2561
   VTX 2339, 2341
   VARIABLES
   {
    #NAMED="1"
   }
  }
  VTX  2343, 0, 0
  {
   COORD (1720,840)
  }
  BUS  2344, 0, 0
  {
   NET 2561
   VTX 2341, 2343
  }
  BUS  2345, 0, 0
  {
   NET 2561
   VTX 2343, 2336
  }
  NET BUS  2411, 0, 0
  {
   VARIABLES
   {
    #MDA_RECORD_TOKEN="OTHER"
    #NAME="cop_addr(31:0)"
    #VERILOG_TYPE="wire"
   }
  }
  TEXT  2412, 0, 0
  {
   TEXT "$#NAME"
   RECT (980,386,1178,415)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2855
  }
  NET BUS  2416, 0, 0
  {
   VARIABLES
   {
    #MDA_RECORD_TOKEN="OTHER"
    #NAME="data2cop(31:0)"
    #VERILOG_TYPE="wire"
   }
  }
  TEXT  2417, 0, 0
  {
   TEXT "$#NAME"
   RECT (900,626,1098,655)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2890
  }
  NET BUS  2421, 0, 0
  {
   VARIABLES
   {
    #MDA_RECORD_TOKEN="OTHER"
    #NAME="cop_mem_ctl(3:0)"
    #VERILOG_TYPE="wire"
   }
  }
  TEXT  2422, 0, 0
  {
   TEXT "$#NAME"
   RECT (1167,751,1393,780)
   ALIGN 9
   MARGINS (1,1)
   PARENT 2898
  }
  NET BUS  2426, 0, 0
  {
   VARIABLES
   {
    #MDA_RECORD_TOKEN="OTHER"
    #NAME="data2mem(31:0)"
    #VERILOG_TYPE="wire"
   }
  }
  TEXT  2427, 0, 0
  {
   TEXT "$#NAME"
   RECT (1151,850,1349,879)
   ALIGN 9
   MARGINS (1,1)
   PARENT 2221
  }
  TEXT  2432, 0, 0
  {
   TEXT "$#NAME"
   RECT (1031,890,1229,919)
   ALIGN 9
   MARGINS (1,1)
   PARENT 2234
  }
  TEXT  2437, 0, 0
  {
   TEXT "$#NAME"
   RECT (1113,970,1227,999)
   ALIGN 9
   MARGINS (1,1)
   PARENT 2229
  }
  TEXT  2442, 0, 0
  {
   TEXT "$#NAME"
   RECT (1149,1010,1291,1039)
   ALIGN 9
   MARGINS (1,1)
   PARENT 2217
  }
  TEXT  2456, 0, 0
  {
   TEXT "$#NAME"
   RECT (954,1131,1166,1160)
   ALIGN 9
   MARGINS (1,1)
   PARENT 2342
  }
  TEXT  2525, 0, 0
  {
   TEXT "$#NAME"
   RECT (1101,1071,1299,1100)
   ALIGN 9
   MARGINS (1,1)
   PARENT 2175
  }
  NET BUS  2557, 0, 0
  {
   VARIABLES
   {
    #MDA_RECORD_TOKEN="OTHER"
    #NAME="mem_Addr(31:0)"
    #VERILOG_TYPE="wire"
   }
  }
  NET BUS  2558, 0, 0
  {
   VARIABLES
   {
    #MDA_RECORD_TOKEN="OTHER"
    #NAME="pc(31:0)"
    #VERILOG_TYPE="wire"
   }
  }
  NET BUS  2559, 0, 0
  {
   VARIABLES
   {
    #MDA_RECORD_TOKEN="OTHER"
    #NAME="wr_en(3:0)"
    #VERILOG_TYPE="wire"
   }
  }
  NET BUS  2560, 0, 0
  {
   VARIABLES
   {
    #MDA_RECORD_TOKEN="OTHER"
    #NAME="ins2core(31:0)"
    #VERILOG_TYPE="wire"
   }
  }
  NET BUS  2561, 0, 0
  {
   VARIABLES
   {
    #MDA_RECORD_TOKEN="OTHER"
    #NAME="data2core(31:0)"
    #VERILOG_TYPE="wire"
   }
  }
  VTX  2850, 0, 0
  {
   COORD (1200,420)
  }
  VTX  2851, 0, 0
  {
   COORD (1060,760)
  }
  VTX  2852, 0, 0
  {
   COORD (1120,420)
  }
  BUS  2853, 0, 0
  {
   NET 2411
   VTX 2850, 2852
  }
  VTX  2854, 0, 0
  {
   COORD (1120,760)
  }
  BUS  2855, 0, 0
  {
   NET 2411
   VTX 2852, 2854
   VARIABLES
   {
    #NAMED="1"
   }
  }
  BUS  2856, 0, 0
  {
   NET 2411
   VTX 2854, 2851
  }
  VTX  2885, 0, 0
  {
   COORD (1200,500)
  }
  VTX  2886, 0, 0
  {
   COORD (1060,800)
  }
  VTX  2887, 0, 0
  {
   COORD (1140,500)
  }
  BUS  2888, 0, 0
  {
   NET 2416
   VTX 2885, 2887
  }
  VTX  2889, 0, 0
  {
   COORD (1140,800)
  }
  BUS  2890, 0, 0
  {
   NET 2416
   VTX 2887, 2889
   VARIABLES
   {
    #NAMED="1"
   }
  }
  BUS  2891, 0, 0
  {
   NET 2416
   VTX 2889, 2886
  }
  VTX  2892, 0, 0
  {
   COORD (1200,540)
  }
  VTX  2893, 0, 0
  {
   COORD (1060,840)
  }
  VTX  2894, 0, 0
  {
   COORD (1160,540)
  }
  BUS  2895, 0, 0
  {
   NET 2421
   VTX 2892, 2894
  }
  VTX  2896, 0, 0
  {
   COORD (1160,840)
  }
  BUS  2897, 0, 0
  {
   NET 2421
   VTX 2894, 2896
  }
  BUS  2898, 0, 0
  {
   NET 2421
   VTX 2896, 2893
   VARIABLES
   {
    #NAMED="1"
   }
  }
 }
 
}

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