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https://opencores.org/ocsvn/mips789/mips789/trunk
Subversion Repositories mips789
[/] [mips789/] [tags/] [arelease/] [synplify_prj/] [rev_1/] [syntmp/] [fifo512_cyclone_srr.htm] - Rev 53
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<!@TC:1223605606>
#Program: Synplify Pro 8.1
#OS: Windows_NT
<a name=compilerReport24>$ Start of Compile
#Fri Oct 10 10:26:44 2008
Synplicity Verilog Compiler, version 3.1.0, Build 049R, built May 3 2005
Copyright (C) 1994-2005, Synplicity Inc. All Rights Reserved
@I::"C:\Program Files\Synplicity\fpga_81\lib\altera\altera.v"
@I::"C:\Program Files\Synplicity\fpga_81\lib\altera\cyclone.v"
@I::"C:\Program Files\Synplicity\fpga_81\lib\altera\altera_mf.v"
@I::"C:\Program Files\Synplicity\fpga_81\lib\altera\altera_lpm.v"
@I::"E:\mips789\mips789\rtl\verilog\EXEC_stage.v"
@I:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":"E:\mips789\mips789\rtl\verilog\include.h"
@I:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":"E:\mips789\mips789\rtl\verilog\include.h"
@N: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:694:80:694:93:@N::@XP_MSG">exec_stage.v(694)</a><!@TM:1223605606> | Read parallel_case directive
@I::"E:\mips789\mips789\rtl\verilog\RF_components.v"
@I:"E:\mips789\mips789\rtl\verilog\RF_components.v":"E:\mips789\mips789\rtl\verilog\include.h"
@I::"E:\mips789\mips789\rtl\verilog\RF_stage.v"
@I:"E:\mips789\mips789\rtl\verilog\RF_stage.v":"E:\mips789\mips789\rtl\verilog\include.h"
@I::"E:\mips789\mips789\rtl\verilog\ctl_fsm.v"
@I:"E:\mips789\mips789\rtl\verilog\ctl_fsm.v":"E:\mips789\mips789\rtl\verilog\include.h"
@N: : <a href="e:\mips789\mips789\rtl\verilog\ctl_fsm.v:58:43:58:56:@N::@XP_MSG">ctl_fsm.v(58)</a><!@TM:1223605606> | Read parallel_case directive
@N: : <a href="e:\mips789\mips789\rtl\verilog\ctl_fsm.v:58:57:58:66:@N::@XP_MSG">ctl_fsm.v(58)</a><!@TM:1223605606> | Read full_case directive
<font color=#A52A2A>@W:<a href="@W:CG286:@XP_HELP">CG286</a> : <a href="e:\mips789\mips789\rtl\verilog\ctl_fsm.v:58:8:58:12:@W:CG286:@XP_MSG">ctl_fsm.v(58)</a><!@TM:1223605606> | Case statement has both a full_case directive and a default clause. The full_case directive is ignored.</font>
@I::"E:\mips789\mips789\rtl\verilog\decode_pipe.v"
@I:"E:\mips789\mips789\rtl\verilog\decode_pipe.v":"E:\mips789\mips789\rtl\verilog\include.h"
@N: : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:34:31:47:@N::@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605606> | Read parallel_case directive
@N: : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:34:45:34:58:@N::@XP_MSG">decode_pipe.v(34)</a><!@TM:1223605606> | Read parallel_case directive
@N: : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:533:47:533:60:@N::@XP_MSG">decode_pipe.v(533)</a><!@TM:1223605606> | Read parallel_case directive
@N: : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:835:49:835:62:@N::@XP_MSG">decode_pipe.v(835)</a><!@TM:1223605606> | Read parallel_case directive
@I::"E:\mips789\mips789\rtl\verilog\dvc.v"
@I:"E:\mips789\mips789\rtl\verilog\dvc.v":"E:\mips789\mips789\rtl\verilog\include.h"
@I::"E:\mips789\mips789\rtl\verilog\fifo.v"
@I:"E:\mips789\mips789\rtl\verilog\fifo.v":"E:\mips789\mips789\rtl\verilog\include.h"
@I::"E:\mips789\mips789\rtl\verilog\forward.v"
@I:"E:\mips789\mips789\rtl\verilog\forward.v":"E:\mips789\mips789\rtl\verilog\include.h"
@I::"E:\mips789\mips789\rtl\verilog\mem_module.v"
@I:"E:\mips789\mips789\rtl\verilog\mem_module.v":"E:\mips789\mips789\rtl\verilog\include.h"
@I::"E:\mips789\mips789\rtl\verilog\mips_core.v"
@I:"E:\mips789\mips789\rtl\verilog\mips_core.v":"E:\mips789\mips789\rtl\verilog\include.h"
@I::"E:\mips789\mips789\rtl\verilog\mips_dvc.v"
@I:"E:\mips789\mips789\rtl\verilog\mips_dvc.v":"E:\mips789\mips789\rtl\verilog\include.h"
@I::"E:\mips789\mips789\rtl\verilog\mips_sys.v"
@I:"E:\mips789\mips789\rtl\verilog\mips_sys.v":"E:\mips789\mips789\rtl\verilog\include.h"
@I::"E:\mips789\mips789\rtl\verilog\mips_uart.v"
@I:"E:\mips789\mips789\rtl\verilog\mips_uart.v":"E:\mips789\mips789\rtl\verilog\include.h"
@I::"E:\mips789\mips789\rtl\verilog\ram_module.v"
@I:"E:\mips789\mips789\rtl\verilog\ram_module.v":"E:\mips789\mips789\rtl\verilog\include.h"
@I::"E:\mips789\mips789\rtl\verilog\sim_ram.v"
@I::"E:\mips789\mips789\rtl\verilog\ulit.v"
@I:"E:\mips789\mips789\rtl\verilog\ulit.v":"E:\mips789\mips789\rtl\verilog\include.h"
@I::"E:\mips789\mips789\rtl\verilog\altera\fifo512_cyclone.v"
@N: : <a href="e:\mips789\mips789\rtl\verilog\altera\fifo512_cyclone.v:39:12:39:25:@N::@XP_MSG">fifo512_cyclone.v(39)</a><!@TM:1223605606> | Read directive translate_off
@N: : <a href="e:\mips789\mips789\rtl\verilog\altera\fifo512_cyclone.v:41:12:41:24:@N::@XP_MSG">fifo512_cyclone.v(41)</a><!@TM:1223605606> | Read directive translate_on
@N: : <a href="e:\mips789\mips789\rtl\verilog\altera\fifo512_cyclone.v:74:16:74:29:@N::@XP_MSG">fifo512_cyclone.v(74)</a><!@TM:1223605606> | Read directive translate_off
@N: : <a href="e:\mips789\mips789\rtl\verilog\altera\fifo512_cyclone.v:81:16:81:28:@N::@XP_MSG">fifo512_cyclone.v(81)</a><!@TM:1223605606> | Read directive translate_on
Verilog syntax check successful!
Options changed - recompiling
Selecting top level module mips_sys
@N: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:78:7:78:26:@N::@XP_MSG">mem_module.v(78)</a><!@TM:1223605618> | Synthesizing module infile_dmem_ctl_reg
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1223605618> | Input port bit <30> of dmem_addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1223605618> | Input port bit <29> of dmem_addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1223605618> | Input port bit <28> of dmem_addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1223605618> | Input port bit <27> of dmem_addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1223605618> | Input port bit <26> of dmem_addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1223605618> | Input port bit <25> of dmem_addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1223605618> | Input port bit <24> of dmem_addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1223605618> | Input port bit <23> of dmem_addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1223605618> | Input port bit <22> of dmem_addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1223605618> | Input port bit <21> of dmem_addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1223605618> | Input port bit <20> of dmem_addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1223605618> | Input port bit <19> of dmem_addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1223605618> | Input port bit <18> of dmem_addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1223605618> | Input port bit <17> of dmem_addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1223605618> | Input port bit <16> of dmem_addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1223605618> | Input port bit <15> of dmem_addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1223605618> | Input port bit <14> of dmem_addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1223605618> | Input port bit <13> of dmem_addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1223605618> | Input port bit <12> of dmem_addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1223605618> | Input port bit <11> of dmem_addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1223605618> | Input port bit <10> of dmem_addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1223605618> | Input port bit <9> of dmem_addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1223605618> | Input port bit <8> of dmem_addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1223605618> | Input port bit <7> of dmem_addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1223605618> | Input port bit <6> of dmem_addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1223605618> | Input port bit <5> of dmem_addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1223605618> | Input port bit <4> of dmem_addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1223605618> | Input port bit <3> of dmem_addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1223605618> | Input port bit <2> of dmem_addr_i[31:0] is unused</font>
@N: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:96:7:96:19:@N::@XP_MSG">mem_module.v(96)</a><!@TM:1223605618> | Synthesizing module mem_addr_ctl
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:102:4:102:8:@W:CL118:@XP_MSG">mem_module.v(102)</a><!@TM:1223605618> | Latch generated from always block for signal wr_en[3:0], probably caused by a missing assignment in an if or case stmt</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1223605618> | Input port bit <31> of addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1223605618> | Input port bit <30> of addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1223605618> | Input port bit <29> of addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1223605618> | Input port bit <28> of addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1223605618> | Input port bit <27> of addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1223605618> | Input port bit <26> of addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1223605618> | Input port bit <25> of addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1223605618> | Input port bit <24> of addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1223605618> | Input port bit <23> of addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1223605618> | Input port bit <22> of addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1223605618> | Input port bit <21> of addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1223605618> | Input port bit <20> of addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1223605618> | Input port bit <19> of addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1223605618> | Input port bit <18> of addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1223605618> | Input port bit <17> of addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1223605618> | Input port bit <16> of addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1223605618> | Input port bit <15> of addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1223605618> | Input port bit <14> of addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1223605618> | Input port bit <13> of addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1223605618> | Input port bit <12> of addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1223605618> | Input port bit <11> of addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1223605618> | Input port bit <10> of addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1223605618> | Input port bit <9> of addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1223605618> | Input port bit <8> of addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1223605618> | Input port bit <7> of addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1223605618> | Input port bit <6> of addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1223605618> | Input port bit <5> of addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1223605618> | Input port bit <4> of addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1223605618> | Input port bit <3> of addr_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1223605618> | Input port bit <2> of addr_i[31:0] is unused</font>
@N: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:199:7:199:18:@N::@XP_MSG">mem_module.v(199)</a><!@TM:1223605618> | Synthesizing module mem_din_ctl
@N: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:130:7:130:19:@N::@XP_MSG">mem_module.v(130)</a><!@TM:1223605618> | Synthesizing module mem_dout_ctl
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:161:4:161:8:@W:CL118:@XP_MSG">mem_module.v(161)</a><!@TM:1223605618> | Latch generated from always block for signal dout[31:0], probably caused by a missing assignment in an if or case stmt</font>
@N: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:4:7:4:17:@N::@XP_MSG">mem_module.v(4)</a><!@TM:1223605618> | Synthesizing module mem_module
@N: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:3:7:3:14:@N::@XP_MSG">ulit.v(3)</a><!@TM:1223605618> | Synthesizing module cal_cpi
@N: : <a href="e:\mips789\mips789\rtl\verilog\ctl_fsm.v:2:7:2:14:@N::@XP_MSG">ctl_fsm.v(2)</a><!@TM:1223605618> | Synthesizing module ctl_FSM
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="e:\mips789\mips789\rtl\verilog\ctl_fsm.v:58:8:58:12:@W:CL118:@XP_MSG">ctl_fsm.v(58)</a><!@TM:1223605618> | Latch generated from always block for signal zz_is_nop, probably caused by a missing assignment in an if or case stmt</font>
<font color=#A52A2A>@W:<a href="@W:CL113:@XP_HELP">CL113</a> : <a href="e:\mips789\mips789\rtl\verilog\ctl_fsm.v:58:8:58:12:@W:CL113:@XP_MSG">ctl_fsm.v(58)</a><!@TM:1223605618> | Feedback mux created for signal iack.</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="e:\mips789\mips789\rtl\verilog\ctl_fsm.v:58:8:58:12:@W:CL118:@XP_MSG">ctl_fsm.v(58)</a><!@TM:1223605618> | Latch generated from always block for signal iack, probably caused by a missing assignment in an if or case stmt</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="e:\mips789\mips789\rtl\verilog\ctl_fsm.v:58:8:58:12:@W:CL118:@XP_MSG">ctl_fsm.v(58)</a><!@TM:1223605618> | Latch generated from always block for signal next_delay_counter_Sreg0[5:0], probably caused by a missing assignment in an if or case stmt</font>
@N:<a href="@N:CL201:@XP_HELP">CL201</a> : <a href="e:\mips789\mips789\rtl\verilog\ctl_fsm.v:224:4:224:10:@N:CL201:@XP_MSG">ctl_fsm.v(224)</a><!@TM:1223605618> | Trying to extract state machine for register CurrState_Sreg0
Extracted state machine for register CurrState_Sreg0
State machine has 9 reachable states with original encodings of:
0000
0001
0010
0011
0100
0101
0110
0111
1000
@N: : <a href="e:\mips789\mips789\rtl\verilog\rf_components.v:50:7:50:13:@N::@XP_MSG">rf_components.v(50)</a><!@TM:1223605618> | Synthesizing module pc_gen
@N: : <a href="e:\mips789\mips789\rtl\verilog\rf_components.v:30:7:30:14:@N::@XP_MSG">rf_components.v(30)</a><!@TM:1223605618> | Synthesizing module compare
<font color=#A52A2A>@W:<a href="@W:CG133:@XP_HELP">CG133</a> : <a href="e:\mips789\mips789\rtl\verilog\rf_components.v:36:14:36:17:@W:CG133:@XP_MSG">rf_components.v(36)</a><!@TM:1223605618> | No assignment to sum</font>
@N: : <a href="e:\mips789\mips789\rtl\verilog\rf_components.v:2:7:2:10:@N::@XP_MSG">rf_components.v(2)</a><!@TM:1223605618> | Synthesizing module ext
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\rf_components.v:3:21:3:26:@W::@XP_MSG">rf_components.v(3)</a><!@TM:1223605618> | Input port bit <31> of ins_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\rf_components.v:3:21:3:26:@W::@XP_MSG">rf_components.v(3)</a><!@TM:1223605618> | Input port bit <30> of ins_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\rf_components.v:3:21:3:26:@W::@XP_MSG">rf_components.v(3)</a><!@TM:1223605618> | Input port bit <29> of ins_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\rf_components.v:3:21:3:26:@W::@XP_MSG">rf_components.v(3)</a><!@TM:1223605618> | Input port bit <28> of ins_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\rf_components.v:3:21:3:26:@W::@XP_MSG">rf_components.v(3)</a><!@TM:1223605618> | Input port bit <27> of ins_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\rf_components.v:3:21:3:26:@W::@XP_MSG">rf_components.v(3)</a><!@TM:1223605618> | Input port bit <26> of ins_i[31:0] is unused</font>
@N: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:104:7:104:22:@N::@XP_MSG">ulit.v(104)</a><!@TM:1223605618> | Synthesizing module r32_reg_clr_cls
@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:104:167:104:172:@N:CG179:@XP_MSG">ulit.v(104)</a><!@TM:1223605618> | Removing redundant assignment
@N: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:30:7:30:11:@N::@XP_MSG">ulit.v(30)</a><!@TM:1223605618> | Synthesizing module jack
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:31:21:31:26:@W::@XP_MSG">ulit.v(31)</a><!@TM:1223605618> | Input port bit <31> of ins_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:31:21:31:26:@W::@XP_MSG">ulit.v(31)</a><!@TM:1223605618> | Input port bit <30> of ins_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:31:21:31:26:@W::@XP_MSG">ulit.v(31)</a><!@TM:1223605618> | Input port bit <29> of ins_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:31:21:31:26:@W::@XP_MSG">ulit.v(31)</a><!@TM:1223605618> | Input port bit <28> of ins_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:31:21:31:26:@W::@XP_MSG">ulit.v(31)</a><!@TM:1223605618> | Input port bit <27> of ins_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:31:21:31:26:@W::@XP_MSG">ulit.v(31)</a><!@TM:1223605618> | Input port bit <26> of ins_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:31:21:31:26:@W::@XP_MSG">ulit.v(31)</a><!@TM:1223605618> | Input port bit <10> of ins_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:31:21:31:26:@W::@XP_MSG">ulit.v(31)</a><!@TM:1223605618> | Input port bit <9> of ins_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:31:21:31:26:@W::@XP_MSG">ulit.v(31)</a><!@TM:1223605618> | Input port bit <8> of ins_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:31:21:31:26:@W::@XP_MSG">ulit.v(31)</a><!@TM:1223605618> | Input port bit <7> of ins_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:31:21:31:26:@W::@XP_MSG">ulit.v(31)</a><!@TM:1223605618> | Input port bit <6> of ins_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:31:21:31:26:@W::@XP_MSG">ulit.v(31)</a><!@TM:1223605618> | Input port bit <5> of ins_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:31:21:31:26:@W::@XP_MSG">ulit.v(31)</a><!@TM:1223605618> | Input port bit <4> of ins_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:31:21:31:26:@W::@XP_MSG">ulit.v(31)</a><!@TM:1223605618> | Input port bit <3> of ins_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:31:21:31:26:@W::@XP_MSG">ulit.v(31)</a><!@TM:1223605618> | Input port bit <2> of ins_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:31:21:31:26:@W::@XP_MSG">ulit.v(31)</a><!@TM:1223605618> | Input port bit <1> of ins_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:31:21:31:26:@W::@XP_MSG">ulit.v(31)</a><!@TM:1223605618> | Input port bit <0> of ins_i[31:0] is unused</font>
@N: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:64:7:64:13:@N::@XP_MSG">ulit.v(64)</a><!@TM:1223605618> | Synthesizing module rd_sel
@N: : <a href="e:\mips789\mips789\rtl\verilog\rf_components.v:90:7:90:16:@N::@XP_MSG">rf_components.v(90)</a><!@TM:1223605618> | Synthesizing module reg_array
@N:<a href="@N:CL134:@XP_HELP">CL134</a> : <a href="e:\mips789\mips789\rtl\verilog\rf_components.v:140:4:140:10:@N:CL134:@XP_MSG">rf_components.v(140)</a><!@TM:1223605618> | Found RAM reg_bank, depth=32, width=32
@N:<a href="@N:CL134:@XP_HELP">CL134</a> : <a href="e:\mips789\mips789\rtl\verilog\rf_components.v:140:4:140:10:@N:CL134:@XP_MSG">rf_components.v(140)</a><!@TM:1223605618> | Found RAM reg_bank, depth=32, width=32
@N: : <a href="e:\mips789\mips789\rtl\verilog\forward.v:25:7:25:14:@N::@XP_MSG">forward.v(25)</a><!@TM:1223605618> | Synthesizing module fwd_mux
@N: : <a href="e:\mips789\mips789\rtl\verilog\rf_stage.v:3:7:3:15:@N::@XP_MSG">rf_stage.v(3)</a><!@TM:1223605618> | Synthesizing module rf_stage
<font color=#A52A2A>@W:<a href="@W:CS149:@XP_HELP">CS149</a> : <a href="e:\mips789\mips789\rtl\verilog\rf_stage.v:91:24:91:30:@W:CS149:@XP_MSG">rf_stage.v(91)</a><!@TM:1223605618> | Port width mismatch for port ins_no. Formal has width 101, Actual 1</font>
<font color=#A52A2A>@W:<a href="@W:CS149:@XP_HELP">CS149</a> : <a href="e:\mips789\mips789\rtl\verilog\rf_stage.v:90:24:90:30:@W:CS149:@XP_MSG">rf_stage.v(90)</a><!@TM:1223605618> | Port width mismatch for port clk_no. Formal has width 101, Actual 1</font>
<font color=#A52A2A>@W:<a href="@W:CL168:@XP_HELP">CL168</a> : <a href="e:\mips789\mips789\rtl\verilog\rf_stage.v:87:12:87:19:@W:CL168:@XP_MSG">rf_stage.v(87)</a><!@TM:1223605618> | Pruning instance CAL_CPI - not in use ...</font>
@N: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:521:7:521:16:@N::@XP_MSG">exec_stage.v(521)</a><!@TM:1223605618> | Synthesizing module muldiv_ff
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:572:4:572:10:@W:CL169:@XP_MSG">exec_stage.v(572)</a><!@TM:1223605618> | Pruning Register LAST_CYCLE_DEAL_SECTION.eqz </font>
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:572:4:572:10:@W:CL169:@XP_MSG">exec_stage.v(572)</a><!@TM:1223605618> | Pruning Register LAST_CYCLE_DEAL_SECTION.LAST_CYCLE_DEAL_SECTION_DEFAULT.op1s_eq_h64 </font>
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:572:4:572:10:@W:CL169:@XP_MSG">exec_stage.v(572)</a><!@TM:1223605618> | Pruning Register LAST_CYCLE_DEAL_SECTION.eqop2 </font>
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:572:4:572:10:@W:CL169:@XP_MSG">exec_stage.v(572)</a><!@TM:1223605618> | Pruning Register LAST_CYCLE_DEAL_SECTION.eqnop2 </font>
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:572:4:572:10:@W:CL169:@XP_MSG">exec_stage.v(572)</a><!@TM:1223605618> | Pruning Register LAST_CYCLE_DEAL_SECTION.LAST_CYCLE_DEAL_SECTION_DEFAULT.op1s_eq_op2s </font>
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:572:4:572:10:@W:CL169:@XP_MSG">exec_stage.v(572)</a><!@TM:1223605618> | Pruning Register START_SECTION.over[32:0] </font>
@N: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:233:7:233:10:@N::@XP_MSG">exec_stage.v(233)</a><!@TM:1223605618> | Synthesizing module alu
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:238:16:238:17:@W::@XP_MSG">exec_stage.v(238)</a><!@TM:1223605618> | No assignment to wire c</font>
@N: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:266:4:266:15:@N::@XP_MSG">exec_stage.v(266)</a><!@TM:1223605618> | Synthesizing module shifter_tak
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:270:25:270:51:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1223605618> | Input port bit <31> of shift_amount[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:270:25:270:51:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1223605618> | Input port bit <30> of shift_amount[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:270:25:270:51:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1223605618> | Input port bit <29> of shift_amount[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:270:25:270:51:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1223605618> | Input port bit <28> of shift_amount[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:270:25:270:51:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1223605618> | Input port bit <27> of shift_amount[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:270:25:270:51:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1223605618> | Input port bit <26> of shift_amount[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:270:25:270:51:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1223605618> | Input port bit <25> of shift_amount[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:270:25:270:51:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1223605618> | Input port bit <24> of shift_amount[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:270:25:270:51:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1223605618> | Input port bit <23> of shift_amount[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:270:25:270:51:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1223605618> | Input port bit <22> of shift_amount[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:270:25:270:51:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1223605618> | Input port bit <21> of shift_amount[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:270:25:270:51:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1223605618> | Input port bit <20> of shift_amount[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:270:25:270:51:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1223605618> | Input port bit <19> of shift_amount[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:270:25:270:51:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1223605618> | Input port bit <18> of shift_amount[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:270:25:270:51:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1223605618> | Input port bit <17> of shift_amount[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:270:25:270:51:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1223605618> | Input port bit <16> of shift_amount[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:270:25:270:51:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1223605618> | Input port bit <15> of shift_amount[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:270:25:270:51:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1223605618> | Input port bit <14> of shift_amount[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:270:25:270:51:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1223605618> | Input port bit <13> of shift_amount[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:270:25:270:51:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1223605618> | Input port bit <12> of shift_amount[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:270:25:270:51:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1223605618> | Input port bit <11> of shift_amount[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:270:25:270:51:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1223605618> | Input port bit <10> of shift_amount[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:270:25:270:51:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1223605618> | Input port bit <9> of shift_amount[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:270:25:270:51:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1223605618> | Input port bit <8> of shift_amount[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:270:25:270:51:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1223605618> | Input port bit <7> of shift_amount[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:270:25:270:51:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1223605618> | Input port bit <6> of shift_amount[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:270:25:270:51:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1223605618> | Input port bit <5> of shift_amount[31:0] is unused</font>
@N: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:138:7:138:14:@N::@XP_MSG">exec_stage.v(138)</a><!@TM:1223605618> | Synthesizing module big_alu
@N: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:22:7:22:12:@N::@XP_MSG">ulit.v(22)</a><!@TM:1223605618> | Synthesizing module add32
@N: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:188:7:188:15:@N::@XP_MSG">exec_stage.v(188)</a><!@TM:1223605618> | Synthesizing module alu_muxa
@N: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:212:7:212:15:@N::@XP_MSG">exec_stage.v(212)</a><!@TM:1223605618> | Synthesizing module alu_muxb
@N: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:150:7:150:14:@N::@XP_MSG">ulit.v(150)</a><!@TM:1223605618> | Synthesizing module r32_reg
@N: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:173:7:173:18:@N::@XP_MSG">ulit.v(173)</a><!@TM:1223605618> | Synthesizing module r32_reg_cls
@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:173:132:173:137:@N:CG179:@XP_MSG">ulit.v(173)</a><!@TM:1223605618> | Removing redundant assignment
@N: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:3:7:3:17:@N::@XP_MSG">exec_stage.v(3)</a><!@TM:1223605618> | Synthesizing module exec_stage
@N: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:54:7:54:11:@N::@XP_MSG">ulit.v(54)</a><!@TM:1223605618> | Synthesizing module or32
@N: : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:2:7:2:14:@N::@XP_MSG">decode_pipe.v(2)</a><!@TM:1223605618> | Synthesizing module decoder
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:CL118:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Latch generated from always block for signal alu_func[4:0], probably caused by a missing assignment in an if or case stmt</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:CL118:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Latch generated from always block for signal pc_gen_ctl[2:0], probably caused by a missing assignment in an if or case stmt</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:CL118:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Latch generated from always block for signal fsm_dly[2:0], probably caused by a missing assignment in an if or case stmt</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:CL118:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Latch generated from always block for signal ext_ctl[2:0], probably caused by a missing assignment in an if or case stmt</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:CL118:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Latch generated from always block for signal rd_sel[1:0], probably caused by a missing assignment in an if or case stmt</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:CL118:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Latch generated from always block for signal muxb_ctl[1:0], probably caused by a missing assignment in an if or case stmt</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:CL118:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Latch generated from always block for signal muxa_ctl[1:0], probably caused by a missing assignment in an if or case stmt</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:CL118:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Latch generated from always block for signal alu_we[0], probably caused by a missing assignment in an if or case stmt</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:CL118:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Latch generated from always block for signal dmem_ctl[3:0], probably caused by a missing assignment in an if or case stmt</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:CL118:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Latch generated from always block for signal cmp_ctl[2:0], probably caused by a missing assignment in an if or case stmt</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:CL118:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Latch generated from always block for signal wb_we[0], probably caused by a missing assignment in an if or case stmt</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:CL118:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Latch generated from always block for signal wb_mux[0], probably caused by a missing assignment in an if or case stmt</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:3:20:3:25:@W::@XP_MSG">decode_pipe.v(3)</a><!@TM:1223605618> | Input port bit <15> of ins_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:3:20:3:25:@W::@XP_MSG">decode_pipe.v(3)</a><!@TM:1223605618> | Input port bit <14> of ins_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:3:20:3:25:@W::@XP_MSG">decode_pipe.v(3)</a><!@TM:1223605618> | Input port bit <13> of ins_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:3:20:3:25:@W::@XP_MSG">decode_pipe.v(3)</a><!@TM:1223605618> | Input port bit <12> of ins_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:3:20:3:25:@W::@XP_MSG">decode_pipe.v(3)</a><!@TM:1223605618> | Input port bit <11> of ins_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:3:20:3:25:@W::@XP_MSG">decode_pipe.v(3)</a><!@TM:1223605618> | Input port bit <10> of ins_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:3:20:3:25:@W::@XP_MSG">decode_pipe.v(3)</a><!@TM:1223605618> | Input port bit <9> of ins_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:3:20:3:25:@W::@XP_MSG">decode_pipe.v(3)</a><!@TM:1223605618> | Input port bit <8> of ins_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:3:20:3:25:@W::@XP_MSG">decode_pipe.v(3)</a><!@TM:1223605618> | Input port bit <7> of ins_i[31:0] is unused</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:3:20:3:25:@W::@XP_MSG">decode_pipe.v(3)</a><!@TM:1223605618> | Input port bit <6> of ins_i[31:0] is unused</font>
@N: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:90:7:90:27:@N::@XP_MSG">ulit.v(90)</a><!@TM:1223605618> | Synthesizing module muxb_ctl_reg_clr_cls
@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:90:202:90:212:@N:CG179:@XP_MSG">ulit.v(90)</a><!@TM:1223605618> | Removing redundant assignment
@N: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:94:7:94:29:@N::@XP_MSG">ulit.v(94)</a><!@TM:1223605618> | Synthesizing module wb_mux_ctl_reg_clr_cls
@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:94:216:94:228:@N:CG179:@XP_MSG">ulit.v(94)</a><!@TM:1223605618> | Removing redundant assignment
@N: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:95:7:95:24:@N::@XP_MSG">ulit.v(95)</a><!@TM:1223605618> | Synthesizing module wb_we_reg_clr_cls
@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:95:181:95:188:@N:CG179:@XP_MSG">ulit.v(95)</a><!@TM:1223605618> | Removing redundant assignment
@N: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:141:7:141:16:@N::@XP_MSG">ulit.v(141)</a><!@TM:1223605618> | Synthesizing module wb_we_reg
@N: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:117:7:117:25:@N::@XP_MSG">ulit.v(117)</a><!@TM:1223605618> | Synthesizing module wb_mux_ctl_reg_clr
@N: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:113:7:113:23:@N::@XP_MSG">ulit.v(113)</a><!@TM:1223605618> | Synthesizing module muxb_ctl_reg_clr
@N: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:116:7:116:23:@N::@XP_MSG">ulit.v(116)</a><!@TM:1223605618> | Synthesizing module dmem_ctl_reg_clr
@N: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:114:7:114:23:@N::@XP_MSG">ulit.v(114)</a><!@TM:1223605618> | Synthesizing module alu_func_reg_clr
@N: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:112:7:112:23:@N::@XP_MSG">ulit.v(112)</a><!@TM:1223605618> | Synthesizing module muxa_ctl_reg_clr
@N: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:140:7:140:21:@N::@XP_MSG">ulit.v(140)</a><!@TM:1223605618> | Synthesizing module wb_mux_ctl_reg
@N: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:118:7:118:20:@N::@XP_MSG">ulit.v(118)</a><!@TM:1223605618> | Synthesizing module wb_we_reg_clr
@N: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:86:7:86:26:@N::@XP_MSG">ulit.v(86)</a><!@TM:1223605618> | Synthesizing module cmp_ctl_reg_clr_cls
@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:86:195:86:204:@N:CG179:@XP_MSG">ulit.v(86)</a><!@TM:1223605618> | Removing redundant assignment
@N: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:115:7:115:21:@N::@XP_MSG">ulit.v(115)</a><!@TM:1223605618> | Synthesizing module alu_we_reg_clr
@N: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:91:7:91:27:@N::@XP_MSG">ulit.v(91)</a><!@TM:1223605618> | Synthesizing module alu_func_reg_clr_cls
@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:91:202:91:212:@N:CG179:@XP_MSG">ulit.v(91)</a><!@TM:1223605618> | Removing redundant assignment
@N: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:93:7:93:27:@N::@XP_MSG">ulit.v(93)</a><!@TM:1223605618> | Synthesizing module dmem_ctl_reg_clr_cls
@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:93:202:93:212:@N:CG179:@XP_MSG">ulit.v(93)</a><!@TM:1223605618> | Removing redundant assignment
@N: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:84:7:84:26:@N::@XP_MSG">ulit.v(84)</a><!@TM:1223605618> | Synthesizing module ext_ctl_reg_clr_cls
@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:84:195:84:204:@N:CG179:@XP_MSG">ulit.v(84)</a><!@TM:1223605618> | Removing redundant assignment
@N: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:85:7:85:25:@N::@XP_MSG">ulit.v(85)</a><!@TM:1223605618> | Synthesizing module rd_sel_reg_clr_cls
@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:85:188:85:196:@N:CG179:@XP_MSG">ulit.v(85)</a><!@TM:1223605618> | Removing redundant assignment
@N: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:92:7:92:25:@N::@XP_MSG">ulit.v(92)</a><!@TM:1223605618> | Synthesizing module alu_we_reg_clr_cls
@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:92:188:92:196:@N:CG179:@XP_MSG">ulit.v(92)</a><!@TM:1223605618> | Removing redundant assignment
@N: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:89:7:89:27:@N::@XP_MSG">ulit.v(89)</a><!@TM:1223605618> | Synthesizing module muxa_ctl_reg_clr_cls
@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:89:202:89:212:@N:CG179:@XP_MSG">ulit.v(89)</a><!@TM:1223605618> | Removing redundant assignment
@N: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:87:7:87:29:@N::@XP_MSG">ulit.v(87)</a><!@TM:1223605618> | Synthesizing module pc_gen_ctl_reg_clr_cls
@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:87:216:87:228:@N:CG179:@XP_MSG">ulit.v(87)</a><!@TM:1223605618> | Removing redundant assignment
@N: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:139:7:139:19:@N::@XP_MSG">ulit.v(139)</a><!@TM:1223605618> | Synthesizing module dmem_ctl_reg
@N: : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:1090:7:1090:20:@N::@XP_MSG">decode_pipe.v(1090)</a><!@TM:1223605618> | Synthesizing module pipelinedregs
@N: : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:1419:7:1419:18:@N::@XP_MSG">decode_pipe.v(1419)</a><!@TM:1223605618> | Synthesizing module decode_pipe
@N: : <a href="e:\mips789\mips789\rtl\verilog\forward.v:12:7:12:19:@N::@XP_MSG">forward.v(12)</a><!@TM:1223605618> | Synthesizing module forward_node
@N: : <a href="e:\mips789\mips789\rtl\verilog\forward.v:4:7:4:16:@N::@XP_MSG">forward.v(4)</a><!@TM:1223605618> | Synthesizing module fw_latch5
@N: : <a href="e:\mips789\mips789\rtl\verilog\forward.v:41:7:41:14:@N::@XP_MSG">forward.v(41)</a><!@TM:1223605618> | Synthesizing module forward
@N: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:149:7:149:13:@N::@XP_MSG">ulit.v(149)</a><!@TM:1223605618> | Synthesizing module r5_reg
@N: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:43:7:43:13:@N::@XP_MSG">ulit.v(43)</a><!@TM:1223605618> | Synthesizing module wb_mux
@N: : <a href="e:\mips789\mips789\rtl\verilog\mips_core.v:3:7:3:16:@N::@XP_MSG">mips_core.v(3)</a><!@TM:1223605618> | Synthesizing module mips_core
@N: : <a href="e:\mips789\mips789\rtl\verilog\mips_uart.v:210:7:210:16:@N::@XP_MSG">mips_uart.v(210)</a><!@TM:1223605618> | Synthesizing module uart_read
@N:<a href="@N:CL201:@XP_HELP">CL201</a> : <a href="e:\mips789\mips789\rtl\verilog\mips_uart.v:274:4:274:10:@N:CL201:@XP_MSG">mips_uart.v(274)</a><!@TM:1223605618> | Trying to extract state machine for register ua_state
Extracted state machine for register ua_state
State machine has 5 reachable states with original encodings of:
000
001
010
011
100
@N: : <a href="e:\mips789\mips789\rtl\verilog\mips_uart.v:3:7:3:12:@N::@XP_MSG">mips_uart.v(3)</a><!@TM:1223605618> | Synthesizing module rxd_d
@N: : <a href="c:\program files\synplicity\fpga_81\lib\altera\altera_mf.v:3709:7:3709:13:@N::@XP_MSG">altera_mf.v(3709)</a><!@TM:1223605618> | Synthesizing module scfifo
lpm_width=32'b00000000000000000000000000001000
lpm_widthu=32'b00000000000000000000000000001001
lpm_numwords=32'b00000000000000000000001000000000
lpm_showahead=24'b010011110100011001000110
intended_device_family=56'b01000011011110010110001101101100011011110110111001100101
almost_full_value=32'b00000000000000000000000000000000
almost_empty_value=32'b00000000000000000000000000000000
underflow_checking=16'b0100111101001110
overflow_checking=16'b0100111101001110
allow_rwcycle_when_full=24'b010011110100011001000110
lpm_hint=152'b01010010010000010100110101011111010000100100110001001111010000110100101101011111010101000101100101010000010001010011110101000001010101010101010001001111
use_eab=16'b0100111101001110
add_ram_output_register=24'b010011110100011001000110
maximum_depth=32'b00000000000000000000000000000000
lpm_type=48'b011100110110001101100110011010010110011001101111
Generated name = scfifo_Z1
@N: : <a href="e:\mips789\mips789\rtl\verilog\altera\fifo512_cyclone.v:42:7:42:22:@N::@XP_MSG">fifo512_cyclone.v(42)</a><!@TM:1223605618> | Synthesizing module fifo512_cyclone
@N: : <a href="e:\mips789\mips789\rtl\verilog\mips_uart.v:70:7:70:17:@N::@XP_MSG">mips_uart.v(70)</a><!@TM:1223605618> | Synthesizing module uart_write
<font color=#A52A2A>@W:<a href="@W:CG133:@XP_HELP">CG133</a> : <a href="e:\mips789\mips789\rtl\verilog\mips_uart.v:94:9:94:21:@W:CG133:@XP_MSG">mips_uart.v(94)</a><!@TM:1223605618> | No assignment to write_done_n</font>
@N:<a href="@N:CL201:@XP_HELP">CL201</a> : <a href="e:\mips789\mips789\rtl\verilog\mips_uart.v:168:4:168:10:@N:CL201:@XP_MSG">mips_uart.v(168)</a><!@TM:1223605618> | Trying to extract state machine for register ua_state
Extracted state machine for register ua_state
State machine has 8 reachable states with original encodings of:
000
001
010
011
100
101
110
111
@N: : <a href="e:\mips789\mips789\rtl\verilog\mips_uart.v:12:7:12:12:@N::@XP_MSG">mips_uart.v(12)</a><!@TM:1223605618> | Synthesizing module uart0
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mips_uart.v:38:9:38:18:@W::@XP_MSG">mips_uart.v(38)</a><!@TM:1223605618> | No assignment to wire w_rxd_clr</font>
@N: : <a href="e:\mips789\mips789\rtl\verilog\dvc.v:52:7:52:17:@N::@XP_MSG">dvc.v(52)</a><!@TM:1223605618> | Synthesizing module seg7led_cv
@N: : <a href="e:\mips789\mips789\rtl\verilog\dvc.v:43:7:43:12:@N::@XP_MSG">dvc.v(43)</a><!@TM:1223605618> | Synthesizing module tmr_d
@N: : <a href="e:\mips789\mips789\rtl\verilog\dvc.v:3:7:3:11:@N::@XP_MSG">dvc.v(3)</a><!@TM:1223605618> | Synthesizing module tmr0
@N: : <a href="e:\mips789\mips789\rtl\verilog\mips_dvc.v:3:7:3:15:@N::@XP_MSG">mips_dvc.v(3)</a><!@TM:1223605618> | Synthesizing module mips_dvc
@N: : <a href="e:\mips789\mips789\rtl\verilog\mips_sys.v:4:7:4:15:@N::@XP_MSG">mips_sys.v(4)</a><!@TM:1223605618> | Synthesizing module mips_sys
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mips_sys.v:78:16:78:25:@W::@XP_MSG">mips_sys.v(78)</a><!@TM:1223605618> | No assignment to wire data2core</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mips_sys.v:79:16:79:24:@W::@XP_MSG">mips_sys.v(79)</a><!@TM:1223605618> | No assignment to wire data2mem</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mips_sys.v:80:16:80:24:@W::@XP_MSG">mips_sys.v(80)</a><!@TM:1223605618> | No assignment to wire ins2core</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mips_sys.v:81:16:81:24:@W::@XP_MSG">mips_sys.v(81)</a><!@TM:1223605618> | No assignment to wire mem_Addr</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mips_sys.v:82:16:82:18:@W::@XP_MSG">mips_sys.v(82)</a><!@TM:1223605618> | No assignment to wire pc</font>
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mips_sys.v:83:15:83:20:@W::@XP_MSG">mips_sys.v(83)</a><!@TM:1223605618> | No assignment to wire wr_en</font>
@END
Process took 0h:00m:11s realtime, 0h:00m:11s cputime
# Fri Oct 10 10:26:56 2008
###########################################################[
Version 8.1
<a name=mapperReport25>Synplicity Altera Technology Mapper, Version 8.1.0, Build 539R, Built May 6 2005
Copyright (C) 1994-2005, Synplicity Inc. All Rights Reserved
Running FSM Explorer ...
Automatic dissolve at startup in view:work.mem_module(verilog) of i_mem_din_ctl(mem_din_ctl)
Automatic dissolve at startup in view:work.mem_module(verilog) of i_mem_addr_ctl(mem_addr_ctl)
Automatic dissolve at startup in view:work.mem_module(verilog) of dmem_ctl_post(infile_dmem_ctl_reg)
Automatic dissolve at startup in view:work.rf_stage(verilog) of rs_fwd_rs(fwd_mux)
Automatic dissolve at startup in view:work.rf_stage(verilog) of rf_fwd_rt(fwd_mux)
Automatic dissolve at startup in view:work.rf_stage(verilog) of jack2(jack)
Automatic dissolve at startup in view:work.rf_stage(verilog) of jack1(jack)
Automatic dissolve at startup in view:work.rf_stage(verilog) of ins_reg(r32_reg_clr_cls)
Automatic dissolve at startup in view:work.rf_stage(verilog) of i_pc_gen(pc_gen)
Automatic dissolve at startup in view:work.exec_stage(verilog) of spc(r32_reg_cls)
Automatic dissolve at startup in view:work.exec_stage(verilog) of pc_nxt(r32_reg)
Automatic dissolve at startup in view:work.exec_stage(verilog) of i_alu_muxb(alu_muxb)
Automatic dissolve at startup in view:work.exec_stage(verilog) of i_alu_muxa(alu_muxa)
Automatic dissolve at startup in view:work.exec_stage(verilog) of dmem_fw_mux(fwd_mux)
Automatic dissolve at startup in view:work.exec_stage(verilog) of add4(add32)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U9(dmem_ctl_reg)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U8(pc_gen_ctl_reg_clr_cls)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U7(muxa_ctl_reg_clr_cls)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U6(alu_we_reg_clr_cls)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U5(rd_sel_reg_clr_cls)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U4(ext_ctl_reg_clr_cls)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U3(dmem_ctl_reg_clr_cls)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U26(alu_func_reg_clr_cls)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U24(alu_we_reg_clr)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U22(wb_we_reg)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U21(wb_mux_ctl_reg)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U20(wb_we_reg)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U2(cmp_ctl_reg_clr_cls)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U19(wb_we_reg_clr)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U18(wb_mux_ctl_reg)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U17(muxa_ctl_reg_clr)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U16(alu_func_reg_clr)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U15(dmem_ctl_reg_clr)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U14(muxb_ctl_reg_clr)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U13(wb_mux_ctl_reg_clr)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U12(wb_we_reg)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U11(wb_we_reg_clr_cls)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U10(wb_mux_ctl_reg_clr_cls)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U1(muxb_ctl_reg_clr_cls)
Automatic dissolve at startup in view:work.decode_pipe(verilog) of pipereg(pipelinedregs)
Automatic dissolve at startup in view:work.forward(verilog) of fw_reg_rnt(fw_latch5)
Automatic dissolve at startup in view:work.forward(verilog) of fw_reg_rns(fw_latch5)
Automatic dissolve at startup in view:work.mips_core(verilog) of wb_mux(wb_mux)
Automatic dissolve at startup in view:work.mips_core(verilog) of rt_reg(r32_reg)
Automatic dissolve at startup in view:work.mips_core(verilog) of rs_reg(r32_reg)
Automatic dissolve at startup in view:work.mips_core(verilog) of rnd_pass2(r5_reg)
Automatic dissolve at startup in view:work.mips_core(verilog) of rnd_pass1(r5_reg)
Automatic dissolve at startup in view:work.mips_core(verilog) of rnd_pass0(r5_reg)
Automatic dissolve at startup in view:work.mips_core(verilog) of pc(r32_reg)
Automatic dissolve at startup in view:work.mips_core(verilog) of ext_reg(r32_reg)
Automatic dissolve at startup in view:work.mips_core(verilog) of cop_dout_reg(r32_reg)
Automatic dissolve at startup in view:work.mips_core(verilog) of cop_data_reg(r32_reg)
Automatic dissolve at startup in view:work.mips_core(verilog) of cop_data_or(or32)
Automatic dissolve at startup in view:work.mips_core(verilog) of alu_pass1(r32_reg)
Automatic dissolve at startup in view:work.mips_core(verilog) of alu_pass0(r32_reg)
Automatic dissolve at startup in view:work.mips_core(verilog) of iexec_stage(exec_stage)
Automatic dissolve at startup in view:work.mips_core(verilog) of iRF_stage(rf_stage)
Automatic dissolve at startup in view:work.mips_core(verilog) of MEM_CTL(mem_module)
Automatic dissolve at startup in view:work.uart_write(verilog) of fifo(fifo512_cyclone)
Automatic dissolve at startup in view:work.uart0(verilog) of rxd_rdy_hold_lw(rxd_d)
Automatic dissolve at startup in view:work.tmr0(verilog) of itmr_d(tmr_d)
Warning: Found 30 combinational loops!
Each loop is reported with an instance in the loop
and nets connected to that instance.
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net fsm_dly_1[0]</font>
1) instance work.decoder(verilog)-fsm_dly_1[0], output net "fsm_dly_1[0]" in work.decoder(verilog)
input nets to instance:
net "fsm_dly_2[0]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net fsm_dly_1[1]</font>
2) instance work.decoder(verilog)-fsm_dly_1[2:1], output net "fsm_dly_1[1]" in work.decoder(verilog)
input nets to instance:
net "fsm_dly_2[1]" in work.decoder(verilog)
net "fsm_dly_2[2]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net fsm_dly_1[2]</font>
3) instance work.decoder(verilog)-fsm_dly_1[2:1], output net "fsm_dly_1[2]" in work.decoder(verilog)
input nets to instance:
net "fsm_dly_2[1]" in work.decoder(verilog)
net "fsm_dly_2[2]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net ext_ctl_1[0]</font>
4) instance work.decoder(verilog)-ext_ctl_1[0], output net "ext_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "ext_ctl_2[0]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net ext_ctl_1[1]</font>
5) instance work.decoder(verilog)-ext_ctl_1[1], output net "ext_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "ext_ctl_2[1]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net ext_ctl_1[2]</font>
6) instance work.decoder(verilog)-ext_ctl_1[2], output net "ext_ctl_1[2]" in work.decoder(verilog)
input nets to instance:
net "ext_ctl_2[2]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net rd_sel_1[0]</font>
7) instance work.decoder(verilog)-rd_sel_1[0], output net "rd_sel_1[0]" in work.decoder(verilog)
input nets to instance:
net "rd_sel_2[0]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net rd_sel_1[1]</font>
8) instance work.decoder(verilog)-rd_sel_1[1], output net "rd_sel_1[1]" in work.decoder(verilog)
input nets to instance:
net "rd_sel_2[1]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "un1_ins_i_22" in work.decoder(verilog)
net "fsm_dly373" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net cmp_ctl_1[0]</font>
9) instance work.decoder(verilog)-cmp_ctl_1[0], output net "cmp_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "cmp_ctl_2[0]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net cmp_ctl_1[1]</font>
10) instance work.decoder(verilog)-cmp_ctl_1[1], output net "cmp_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "cmp_ctl_2[1]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net cmp_ctl_1[2]</font>
11) instance work.decoder(verilog)-cmp_ctl_1[2], output net "cmp_ctl_1[2]" in work.decoder(verilog)
input nets to instance:
net "cmp_ctl_2[2]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net pc_gen_ctl_1[0]</font>
12) instance work.decoder(verilog)-pc_gen_ctl_1[0], output net "pc_gen_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "pc_gen_ctl_2[0]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net pc_gen_ctl_1[1]</font>
13) instance work.decoder(verilog)-pc_gen_ctl_1[1], output net "pc_gen_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "pc_gen_ctl_2[1]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net pc_gen_ctl_1[2]</font>
14) instance work.decoder(verilog)-pc_gen_ctl_1[2], output net "pc_gen_ctl_1[2]" in work.decoder(verilog)
input nets to instance:
net "pc_gen_ctl_2[2]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net muxa_ctl_1[0]</font>
15) instance work.decoder(verilog)-muxa_ctl_1[0], output net "muxa_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "muxa_ctl_2[0]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net muxa_ctl_1[1]</font>
16) instance work.decoder(verilog)-muxa_ctl_1[1], output net "muxa_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "muxa_ctl_2[1]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net muxb_ctl_1[0]</font>
17) instance work.decoder(verilog)-muxb_ctl_1[0], output net "muxb_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "muxb_ctl_2[0]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net muxb_ctl_1[1]</font>
18) instance work.decoder(verilog)-muxb_ctl_1[1], output net "muxb_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "muxb_ctl_2[1]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net alu_func_1[0]</font>
19) instance work.decoder(verilog)-alu_func_1[0], output net "alu_func_1[0]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[0]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net alu_func_1[1]</font>
20) instance work.decoder(verilog)-alu_func_1[1], output net "alu_func_1[1]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[1]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net alu_func_1[2]</font>
21) instance work.decoder(verilog)-alu_func_1[2], output net "alu_func_1[2]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[2]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net alu_func_1[3]</font>
22) instance work.decoder(verilog)-alu_func_1[3], output net "alu_func_1[3]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[3]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net alu_func_1[4]</font>
23) instance work.decoder(verilog)-alu_func_1[4], output net "alu_func_1[4]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[4]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net dmem_ctl_1[0]</font>
24) instance work.decoder(verilog)-dmem_ctl_1[0], output net "dmem_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "dmem_ctl_2[0]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net dmem_ctl_1[1]</font>
25) instance work.decoder(verilog)-dmem_ctl_1[1], output net "dmem_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "dmem_ctl_2[1]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "un1_ins_i_22" in work.decoder(verilog)
net "fsm_dly373" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net dmem_ctl_1[2]</font>
26) instance work.decoder(verilog)-dmem_ctl_1[2], output net "dmem_ctl_1[2]" in work.decoder(verilog)
input nets to instance:
net "dmem_ctl_2[2]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "un1_ins_i_24" in work.decoder(verilog)
net "un1_ins_i_15" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net dmem_ctl_1[3]</font>
27) instance work.decoder(verilog)-dmem_ctl_1[3], output net "dmem_ctl_1[3]" in work.decoder(verilog)
input nets to instance:
net "dmem_ctl_2[3]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net alu_we[0]</font>
28) instance work.decoder(verilog)-alu_we[0], output net "alu_we[0]" in work.decoder(verilog)
input nets to instance:
net "alu_we_1[0]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net wb_mux[0]</font>
29) instance work.decoder(verilog)-wb_mux[0], output net "wb_mux[0]" in work.decoder(verilog)
input nets to instance:
net "wb_mux_1[0]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net wb_we[0]</font>
30) instance work.decoder(verilog)-wb_we[0], output net "wb_we[0]" in work.decoder(verilog)
input nets to instance:
net "wb_we_1[0]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
End of loops
RTL optimization done.
Warning: Found 30 combinational loops!
Each loop is reported with an instance in the loop
and nets connected to that instance.
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net fsm_dly_1[0]</font>
1) instance work.decoder(verilog)-fsm_dly_1[0], output net "fsm_dly_1[0]" in work.decoder(verilog)
input nets to instance:
net "fsm_dly_2[0]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net fsm_dly_1[1]</font>
2) instance work.decoder(verilog)-fsm_dly_1[2:1], output net "fsm_dly_1[1]" in work.decoder(verilog)
input nets to instance:
net "fsm_dly_2[1]" in work.decoder(verilog)
net "fsm_dly_2[2]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net fsm_dly_1[2]</font>
3) instance work.decoder(verilog)-fsm_dly_1[2:1], output net "fsm_dly_1[2]" in work.decoder(verilog)
input nets to instance:
net "fsm_dly_2[1]" in work.decoder(verilog)
net "fsm_dly_2[2]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net wb_mux_1[0]</font>
4) instance work.decoder(verilog)-wb_mux_1[0], output net "wb_mux_1[0]" in work.decoder(verilog)
input nets to instance:
net "un1_alu_we_3_sqmuxa_4" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "un1_alu_we_3_sqmuxa" in work.decoder(verilog)
net "wb_mux[0]" in work.decoder(verilog)
net "un1_fsm_dly365" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net wb_we_1[0]</font>
5) instance work.decoder(verilog)-wb_we_1[0], output net "wb_we_1[0]" in work.decoder(verilog)
input nets to instance:
net "un1_alu_we_3_sqmuxa_3" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "un1_alu_we_3_sqmuxa" in work.decoder(verilog)
net "wb_we[0]" in work.decoder(verilog)
net "un1_fsm_dly362" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net alu_func_2[0]</font>
6) instance work.decoder(verilog)-alu_func_2[4:0], output net "alu_func_2[0]" in work.decoder(verilog)
input nets to instance:
net "alu_func_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_1_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_3_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_4_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_5_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_6_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_7_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_8_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_9_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_10_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_11_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_12_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_13_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_14_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_15_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_16_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_17_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_18_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_19_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_20_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_21_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_22_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_23_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_24_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_25_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_26_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_27_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_28_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_3_sqmuxa" in work.decoder(verilog)
net "alu_func_1[0]" in work.decoder(verilog)
net "alu_func_1[1]" in work.decoder(verilog)
net "alu_func_1[2]" in work.decoder(verilog)
net "alu_func_1[3]" in work.decoder(verilog)
net "alu_func_1[4]" in work.decoder(verilog)
net "alu_we_4_sqmuxa" in work.decoder(verilog)
net "alu_func_1[0]" in work.decoder(verilog)
net "alu_func_1[1]" in work.decoder(verilog)
net "alu_func_1[2]" in work.decoder(verilog)
net "alu_func_1[3]" in work.decoder(verilog)
net "alu_func_1[4]" in work.decoder(verilog)
net "fsm_dly350" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly351" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly352" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly353" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly354" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly355" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly356" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly357" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly358" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly359" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly360" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly361" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly362" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly363" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
net "alu_func_1[0]" in work.decoder(verilog)
net "alu_func_1[1]" in work.decoder(verilog)
net "alu_func_1[2]" in work.decoder(verilog)
net "alu_func_1[3]" in work.decoder(verilog)
net "alu_func_1[4]" in work.decoder(verilog)
net "fsm_dly365" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly366" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly367" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly368" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly369" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly370" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net alu_func_2[1]</font>
7) instance work.decoder(verilog)-alu_func_2[4:0], output net "alu_func_2[1]" in work.decoder(verilog)
input nets to instance:
net "alu_func_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_1_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_3_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_4_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_5_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_6_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_7_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_8_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_9_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_10_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_11_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_12_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_13_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_14_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_15_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_16_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_17_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_18_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_19_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_20_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_21_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_22_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_23_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_24_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_25_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_26_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_27_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_28_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_3_sqmuxa" in work.decoder(verilog)
net "alu_func_1[0]" in work.decoder(verilog)
net "alu_func_1[1]" in work.decoder(verilog)
net "alu_func_1[2]" in work.decoder(verilog)
net "alu_func_1[3]" in work.decoder(verilog)
net "alu_func_1[4]" in work.decoder(verilog)
net "alu_we_4_sqmuxa" in work.decoder(verilog)
net "alu_func_1[0]" in work.decoder(verilog)
net "alu_func_1[1]" in work.decoder(verilog)
net "alu_func_1[2]" in work.decoder(verilog)
net "alu_func_1[3]" in work.decoder(verilog)
net "alu_func_1[4]" in work.decoder(verilog)
net "fsm_dly350" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly351" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly352" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly353" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly354" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly355" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly356" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly357" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly358" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly359" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly360" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly361" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly362" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly363" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
net "alu_func_1[0]" in work.decoder(verilog)
net "alu_func_1[1]" in work.decoder(verilog)
net "alu_func_1[2]" in work.decoder(verilog)
net "alu_func_1[3]" in work.decoder(verilog)
net "alu_func_1[4]" in work.decoder(verilog)
net "fsm_dly365" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly366" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly367" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly368" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly369" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly370" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net alu_func_2[2]</font>
8) instance work.decoder(verilog)-alu_func_2[4:0], output net "alu_func_2[2]" in work.decoder(verilog)
input nets to instance:
net "alu_func_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_1_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_3_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_4_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_5_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_6_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_7_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_8_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_9_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_10_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_11_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_12_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_13_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_14_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_15_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_16_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_17_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_18_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_19_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_20_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_21_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_22_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_23_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_24_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_25_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_26_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_27_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_28_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_3_sqmuxa" in work.decoder(verilog)
net "alu_func_1[0]" in work.decoder(verilog)
net "alu_func_1[1]" in work.decoder(verilog)
net "alu_func_1[2]" in work.decoder(verilog)
net "alu_func_1[3]" in work.decoder(verilog)
net "alu_func_1[4]" in work.decoder(verilog)
net "alu_we_4_sqmuxa" in work.decoder(verilog)
net "alu_func_1[0]" in work.decoder(verilog)
net "alu_func_1[1]" in work.decoder(verilog)
net "alu_func_1[2]" in work.decoder(verilog)
net "alu_func_1[3]" in work.decoder(verilog)
net "alu_func_1[4]" in work.decoder(verilog)
net "fsm_dly350" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly351" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly352" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly353" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly354" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly355" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly356" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly357" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly358" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly359" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly360" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly361" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly362" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly363" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
net "alu_func_1[0]" in work.decoder(verilog)
net "alu_func_1[1]" in work.decoder(verilog)
net "alu_func_1[2]" in work.decoder(verilog)
net "alu_func_1[3]" in work.decoder(verilog)
net "alu_func_1[4]" in work.decoder(verilog)
net "fsm_dly365" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly366" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly367" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly368" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly369" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly370" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net alu_func_2[3]</font>
9) instance work.decoder(verilog)-alu_func_2[4:0], output net "alu_func_2[3]" in work.decoder(verilog)
input nets to instance:
net "alu_func_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_1_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_3_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_4_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_5_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_6_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_7_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_8_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_9_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_10_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_11_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_12_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_13_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_14_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_15_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_16_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_17_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_18_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_19_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_20_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_21_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_22_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_23_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_24_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_25_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_26_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_27_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_28_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_3_sqmuxa" in work.decoder(verilog)
net "alu_func_1[0]" in work.decoder(verilog)
net "alu_func_1[1]" in work.decoder(verilog)
net "alu_func_1[2]" in work.decoder(verilog)
net "alu_func_1[3]" in work.decoder(verilog)
net "alu_func_1[4]" in work.decoder(verilog)
net "alu_we_4_sqmuxa" in work.decoder(verilog)
net "alu_func_1[0]" in work.decoder(verilog)
net "alu_func_1[1]" in work.decoder(verilog)
net "alu_func_1[2]" in work.decoder(verilog)
net "alu_func_1[3]" in work.decoder(verilog)
net "alu_func_1[4]" in work.decoder(verilog)
net "fsm_dly350" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly351" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly352" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly353" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly354" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly355" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly356" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly357" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly358" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly359" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly360" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly361" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly362" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly363" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
net "alu_func_1[0]" in work.decoder(verilog)
net "alu_func_1[1]" in work.decoder(verilog)
net "alu_func_1[2]" in work.decoder(verilog)
net "alu_func_1[3]" in work.decoder(verilog)
net "alu_func_1[4]" in work.decoder(verilog)
net "fsm_dly365" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly366" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly367" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly368" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly369" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly370" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net alu_func_2[4]</font>
10) instance work.decoder(verilog)-alu_func_2[4:0], output net "alu_func_2[4]" in work.decoder(verilog)
input nets to instance:
net "alu_func_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_1_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_3_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_4_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_5_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_6_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_7_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_8_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_9_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_10_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_11_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_12_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_13_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_14_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_15_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_16_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_17_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_18_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_19_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_20_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_21_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_22_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_23_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_24_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_25_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_26_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_27_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_28_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_3_sqmuxa" in work.decoder(verilog)
net "alu_func_1[0]" in work.decoder(verilog)
net "alu_func_1[1]" in work.decoder(verilog)
net "alu_func_1[2]" in work.decoder(verilog)
net "alu_func_1[3]" in work.decoder(verilog)
net "alu_func_1[4]" in work.decoder(verilog)
net "alu_we_4_sqmuxa" in work.decoder(verilog)
net "alu_func_1[0]" in work.decoder(verilog)
net "alu_func_1[1]" in work.decoder(verilog)
net "alu_func_1[2]" in work.decoder(verilog)
net "alu_func_1[3]" in work.decoder(verilog)
net "alu_func_1[4]" in work.decoder(verilog)
net "fsm_dly350" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly351" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly352" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly353" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly354" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly355" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly356" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly357" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly358" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly359" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly360" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly361" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly362" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly363" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
net "alu_func_1[0]" in work.decoder(verilog)
net "alu_func_1[1]" in work.decoder(verilog)
net "alu_func_1[2]" in work.decoder(verilog)
net "alu_func_1[3]" in work.decoder(verilog)
net "alu_func_1[4]" in work.decoder(verilog)
net "fsm_dly365" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly366" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly367" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly368" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly369" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly370" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net alu_we_1[0]</font>
11) instance work.decoder(verilog)-alu_we_1[0], output net "alu_we_1[0]" in work.decoder(verilog)
input nets to instance:
net "alu_func_0_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_1_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_2_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_3_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_4_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_5_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_6_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_7_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_8_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_9_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_10_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_11_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_12_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_13_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_14_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_15_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_16_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_17_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_18_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_19_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_20_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_21_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_22_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_23_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_24_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_25_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_26_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_27_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_28_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_3_sqmuxa" in work.decoder(verilog)
net "alu_we[0]" in work.decoder(verilog)
net "alu_we_4_sqmuxa" in work.decoder(verilog)
net "alu_we[0]" in work.decoder(verilog)
net "fsm_dly350" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly351" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly352" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly353" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly354" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly355" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly356" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly357" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly358" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly359" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly360" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly361" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly362" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly363" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
net "alu_we[0]" in work.decoder(verilog)
net "fsm_dly365" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly366" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly367" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly368" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly369" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly370" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net ext_ctl_2[0]</font>
12) instance work.decoder(verilog)-ext_ctl_2[2:0], output net "ext_ctl_2[0]" in work.decoder(verilog)
input nets to instance:
net "alu_func_0_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_1_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_2_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_3_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_4_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_5_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_6_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_7_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_8_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_9_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_10_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_11_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_12_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_13_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_14_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_15_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_16_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_17_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_18_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_19_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_20_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_21_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_22_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_23_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_24_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_25_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_26_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_27_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_28_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_1_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_3_sqmuxa" in work.decoder(verilog)
net "ext_ctl_1[0]" in work.decoder(verilog)
net "ext_ctl_1[1]" in work.decoder(verilog)
net "ext_ctl_1[2]" in work.decoder(verilog)
net "alu_we_4_sqmuxa" in work.decoder(verilog)
net "ext_ctl_1[0]" in work.decoder(verilog)
net "ext_ctl_1[1]" in work.decoder(verilog)
net "ext_ctl_1[2]" in work.decoder(verilog)
net "fsm_dly350" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly351" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly352" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly353" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly354" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly355" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly356" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly357" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly358" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly359" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly360" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly361" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly362" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly363" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
net "ext_ctl_1[0]" in work.decoder(verilog)
net "ext_ctl_1[1]" in work.decoder(verilog)
net "ext_ctl_1[2]" in work.decoder(verilog)
net "fsm_dly365" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly366" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly367" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly368" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly369" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly370" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net ext_ctl_2[1]</font>
13) instance work.decoder(verilog)-ext_ctl_2[2:0], output net "ext_ctl_2[1]" in work.decoder(verilog)
input nets to instance:
net "alu_func_0_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_1_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_2_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_3_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_4_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_5_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_6_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_7_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_8_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_9_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_10_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_11_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_12_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_13_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_14_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_15_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_16_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_17_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_18_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_19_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_20_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_21_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_22_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_23_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_24_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_25_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_26_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_27_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_28_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_1_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_3_sqmuxa" in work.decoder(verilog)
net "ext_ctl_1[0]" in work.decoder(verilog)
net "ext_ctl_1[1]" in work.decoder(verilog)
net "ext_ctl_1[2]" in work.decoder(verilog)
net "alu_we_4_sqmuxa" in work.decoder(verilog)
net "ext_ctl_1[0]" in work.decoder(verilog)
net "ext_ctl_1[1]" in work.decoder(verilog)
net "ext_ctl_1[2]" in work.decoder(verilog)
net "fsm_dly350" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly351" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly352" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly353" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly354" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly355" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly356" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly357" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly358" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly359" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly360" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly361" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly362" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly363" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
net "ext_ctl_1[0]" in work.decoder(verilog)
net "ext_ctl_1[1]" in work.decoder(verilog)
net "ext_ctl_1[2]" in work.decoder(verilog)
net "fsm_dly365" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly366" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly367" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly368" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly369" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly370" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net ext_ctl_2[2]</font>
14) instance work.decoder(verilog)-ext_ctl_2[2:0], output net "ext_ctl_2[2]" in work.decoder(verilog)
input nets to instance:
net "alu_func_0_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_1_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_2_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_3_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_4_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_5_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_6_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_7_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_8_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_9_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_10_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_11_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_12_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_13_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_14_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_15_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_16_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_17_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_18_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_19_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_20_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_21_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_22_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_23_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_24_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_25_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_26_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_27_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_28_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_1_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_3_sqmuxa" in work.decoder(verilog)
net "ext_ctl_1[0]" in work.decoder(verilog)
net "ext_ctl_1[1]" in work.decoder(verilog)
net "ext_ctl_1[2]" in work.decoder(verilog)
net "alu_we_4_sqmuxa" in work.decoder(verilog)
net "ext_ctl_1[0]" in work.decoder(verilog)
net "ext_ctl_1[1]" in work.decoder(verilog)
net "ext_ctl_1[2]" in work.decoder(verilog)
net "fsm_dly350" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly351" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly352" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly353" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly354" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly355" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly356" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly357" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly358" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly359" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly360" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly361" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly362" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly363" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
net "ext_ctl_1[0]" in work.decoder(verilog)
net "ext_ctl_1[1]" in work.decoder(verilog)
net "ext_ctl_1[2]" in work.decoder(verilog)
net "fsm_dly365" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly366" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly367" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly368" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly369" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly370" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net muxa_ctl_2[0]</font>
15) instance work.decoder(verilog)-muxa_ctl_2[1:0], output net "muxa_ctl_2[0]" in work.decoder(verilog)
input nets to instance:
net "alu_func_0_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_1_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_2_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_3_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_4_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_5_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_6_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_7_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_8_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_9_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_10_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_11_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_12_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_13_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_14_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_15_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_16_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_17_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_18_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_19_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_20_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_21_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_22_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_23_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_24_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_25_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_26_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_27_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_28_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_3_sqmuxa" in work.decoder(verilog)
net "muxa_ctl_1[0]" in work.decoder(verilog)
net "muxa_ctl_1[1]" in work.decoder(verilog)
net "alu_we_4_sqmuxa" in work.decoder(verilog)
net "muxa_ctl_1[0]" in work.decoder(verilog)
net "muxa_ctl_1[1]" in work.decoder(verilog)
net "fsm_dly350" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly351" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly352" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly353" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly354" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly355" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly356" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly357" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly358" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly359" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly360" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly361" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly362" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly363" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
net "muxa_ctl_1[0]" in work.decoder(verilog)
net "muxa_ctl_1[1]" in work.decoder(verilog)
net "fsm_dly365" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly366" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly367" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly368" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly369" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly370" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net muxa_ctl_2[1]</font>
16) instance work.decoder(verilog)-muxa_ctl_2[1:0], output net "muxa_ctl_2[1]" in work.decoder(verilog)
input nets to instance:
net "alu_func_0_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_1_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_2_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_3_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_4_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_5_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_6_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_7_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_8_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_9_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_10_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_11_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_12_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_13_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_14_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_15_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_16_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_17_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_18_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_19_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_20_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_21_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_22_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_23_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_24_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_25_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_26_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_27_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_28_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_3_sqmuxa" in work.decoder(verilog)
net "muxa_ctl_1[0]" in work.decoder(verilog)
net "muxa_ctl_1[1]" in work.decoder(verilog)
net "alu_we_4_sqmuxa" in work.decoder(verilog)
net "muxa_ctl_1[0]" in work.decoder(verilog)
net "muxa_ctl_1[1]" in work.decoder(verilog)
net "fsm_dly350" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly351" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly352" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly353" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly354" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly355" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly356" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly357" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly358" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly359" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly360" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly361" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly362" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly363" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
net "muxa_ctl_1[0]" in work.decoder(verilog)
net "muxa_ctl_1[1]" in work.decoder(verilog)
net "fsm_dly365" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly366" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly367" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly368" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly369" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly370" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net muxb_ctl_2[0]</font>
17) instance work.decoder(verilog)-muxb_ctl_2[1:0], output net "muxb_ctl_2[0]" in work.decoder(verilog)
input nets to instance:
net "alu_func_0_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_1_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_2_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_3_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_4_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_5_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_6_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_7_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_8_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_9_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_10_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_11_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_12_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_13_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_14_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_15_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_16_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_17_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_18_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_19_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_20_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_21_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_22_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_23_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_24_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_25_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_26_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_27_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_28_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_3_sqmuxa" in work.decoder(verilog)
net "muxb_ctl_1[0]" in work.decoder(verilog)
net "muxb_ctl_1[1]" in work.decoder(verilog)
net "alu_we_4_sqmuxa" in work.decoder(verilog)
net "muxb_ctl_1[0]" in work.decoder(verilog)
net "muxb_ctl_1[1]" in work.decoder(verilog)
net "fsm_dly350" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly351" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly352" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly353" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly354" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly355" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly356" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly357" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly358" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly359" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly360" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly361" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly362" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly363" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
net "muxb_ctl_1[0]" in work.decoder(verilog)
net "muxb_ctl_1[1]" in work.decoder(verilog)
net "fsm_dly365" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly366" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly367" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly368" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly369" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly370" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net muxb_ctl_2[1]</font>
18) instance work.decoder(verilog)-muxb_ctl_2[1:0], output net "muxb_ctl_2[1]" in work.decoder(verilog)
input nets to instance:
net "alu_func_0_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_1_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_2_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_3_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_4_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_5_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_6_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_7_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_8_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_9_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_10_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_11_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_12_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_13_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_14_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_15_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_16_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_17_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_18_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_19_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_20_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_21_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_22_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_23_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_24_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_25_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_26_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_27_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_28_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_3_sqmuxa" in work.decoder(verilog)
net "muxb_ctl_1[0]" in work.decoder(verilog)
net "muxb_ctl_1[1]" in work.decoder(verilog)
net "alu_we_4_sqmuxa" in work.decoder(verilog)
net "muxb_ctl_1[0]" in work.decoder(verilog)
net "muxb_ctl_1[1]" in work.decoder(verilog)
net "fsm_dly350" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly351" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly352" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly353" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly354" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly355" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly356" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly357" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly358" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly359" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly360" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly361" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly362" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly363" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
net "muxb_ctl_1[0]" in work.decoder(verilog)
net "muxb_ctl_1[1]" in work.decoder(verilog)
net "fsm_dly365" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly366" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly367" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly368" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly369" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly370" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net pc_gen_ctl_2[0]</font>
19) instance work.decoder(verilog)-pc_gen_ctl_2[2:0], output net "pc_gen_ctl_2[0]" in work.decoder(verilog)
input nets to instance:
net "alu_func_0_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_1_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_2_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_3_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_4_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_5_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_6_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_7_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_8_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_9_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_10_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_11_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_12_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_13_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_14_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_15_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_16_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_17_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_18_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_19_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_20_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_21_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_22_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_23_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_24_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_25_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_26_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_27_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_28_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_1_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_3_sqmuxa" in work.decoder(verilog)
net "pc_gen_ctl_1[0]" in work.decoder(verilog)
net "pc_gen_ctl_1[1]" in work.decoder(verilog)
net "pc_gen_ctl_1[2]" in work.decoder(verilog)
net "alu_we_4_sqmuxa" in work.decoder(verilog)
net "pc_gen_ctl_1[0]" in work.decoder(verilog)
net "pc_gen_ctl_1[1]" in work.decoder(verilog)
net "pc_gen_ctl_1[2]" in work.decoder(verilog)
net "fsm_dly350" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly351" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly352" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly353" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly354" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly355" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly356" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly357" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly358" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly359" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly360" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly361" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly362" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly363" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
net "pc_gen_ctl_1[0]" in work.decoder(verilog)
net "pc_gen_ctl_1[1]" in work.decoder(verilog)
net "pc_gen_ctl_1[2]" in work.decoder(verilog)
net "fsm_dly365" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly366" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly367" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly368" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly369" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly370" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net pc_gen_ctl_2[1]</font>
20) instance work.decoder(verilog)-pc_gen_ctl_2[2:0], output net "pc_gen_ctl_2[1]" in work.decoder(verilog)
input nets to instance:
net "alu_func_0_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_1_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_2_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_3_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_4_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_5_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_6_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_7_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_8_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_9_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_10_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_11_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_12_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_13_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_14_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_15_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_16_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_17_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_18_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_19_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_20_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_21_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_22_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_23_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_24_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_25_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_26_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_27_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_28_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_1_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_3_sqmuxa" in work.decoder(verilog)
net "pc_gen_ctl_1[0]" in work.decoder(verilog)
net "pc_gen_ctl_1[1]" in work.decoder(verilog)
net "pc_gen_ctl_1[2]" in work.decoder(verilog)
net "alu_we_4_sqmuxa" in work.decoder(verilog)
net "pc_gen_ctl_1[0]" in work.decoder(verilog)
net "pc_gen_ctl_1[1]" in work.decoder(verilog)
net "pc_gen_ctl_1[2]" in work.decoder(verilog)
net "fsm_dly350" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly351" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly352" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly353" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly354" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly355" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly356" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly357" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly358" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly359" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly360" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly361" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly362" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly363" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
net "pc_gen_ctl_1[0]" in work.decoder(verilog)
net "pc_gen_ctl_1[1]" in work.decoder(verilog)
net "pc_gen_ctl_1[2]" in work.decoder(verilog)
net "fsm_dly365" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly366" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly367" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly368" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly369" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly370" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net pc_gen_ctl_2[2]</font>
21) instance work.decoder(verilog)-pc_gen_ctl_2[2:0], output net "pc_gen_ctl_2[2]" in work.decoder(verilog)
input nets to instance:
net "alu_func_0_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_1_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_2_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_3_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_4_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_5_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_6_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_7_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_8_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_9_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_10_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_11_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_12_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_13_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_14_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_15_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_16_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_17_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_18_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_19_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_20_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_21_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_22_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_23_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_24_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_25_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_26_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_27_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_28_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_1_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_3_sqmuxa" in work.decoder(verilog)
net "pc_gen_ctl_1[0]" in work.decoder(verilog)
net "pc_gen_ctl_1[1]" in work.decoder(verilog)
net "pc_gen_ctl_1[2]" in work.decoder(verilog)
net "alu_we_4_sqmuxa" in work.decoder(verilog)
net "pc_gen_ctl_1[0]" in work.decoder(verilog)
net "pc_gen_ctl_1[1]" in work.decoder(verilog)
net "pc_gen_ctl_1[2]" in work.decoder(verilog)
net "fsm_dly350" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly351" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly352" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly353" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly354" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly355" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly356" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly357" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly358" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly359" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly360" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly361" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly362" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly363" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
net "pc_gen_ctl_1[0]" in work.decoder(verilog)
net "pc_gen_ctl_1[1]" in work.decoder(verilog)
net "pc_gen_ctl_1[2]" in work.decoder(verilog)
net "fsm_dly365" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly366" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly367" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly368" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly369" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly370" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net rd_sel_2[0]</font>
22) instance work.decoder(verilog)-rd_sel_2[1:0], output net "rd_sel_2[0]" in work.decoder(verilog)
input nets to instance:
net "alu_func_0_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_1_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_2_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_3_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_4_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_5_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_6_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_7_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_8_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_9_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_10_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_11_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_12_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_13_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_14_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_15_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_16_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_17_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_18_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_19_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_20_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_21_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_22_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_23_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_24_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_25_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_26_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_27_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_28_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_3_sqmuxa" in work.decoder(verilog)
net "rd_sel_1[0]" in work.decoder(verilog)
net "rd_sel_1[1]" in work.decoder(verilog)
net "alu_we_4_sqmuxa" in work.decoder(verilog)
net "rd_sel_1[0]" in work.decoder(verilog)
net "rd_sel_1[1]" in work.decoder(verilog)
net "fsm_dly350" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly351" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly352" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly353" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly354" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly355" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly356" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly357" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly358" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly359" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly360" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly361" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly362" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly363" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
net "rd_sel_1[0]" in work.decoder(verilog)
net "rd_sel_1[1]" in work.decoder(verilog)
net "fsm_dly365" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly366" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly367" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly368" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly369" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly370" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net rd_sel_2[1]</font>
23) instance work.decoder(verilog)-rd_sel_2[1:0], output net "rd_sel_2[1]" in work.decoder(verilog)
input nets to instance:
net "alu_func_0_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_1_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_2_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_3_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_4_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_5_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_6_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_7_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_8_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_9_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_10_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_11_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_12_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_13_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_14_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_15_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_16_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_17_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_18_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_19_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_20_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_21_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_22_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_23_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_24_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_25_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_26_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_27_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_28_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_3_sqmuxa" in work.decoder(verilog)
net "rd_sel_1[0]" in work.decoder(verilog)
net "rd_sel_1[1]" in work.decoder(verilog)
net "alu_we_4_sqmuxa" in work.decoder(verilog)
net "rd_sel_1[0]" in work.decoder(verilog)
net "rd_sel_1[1]" in work.decoder(verilog)
net "fsm_dly350" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly351" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly352" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly353" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly354" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly355" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly356" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly357" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly358" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly359" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly360" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly361" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly362" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly363" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
net "rd_sel_1[0]" in work.decoder(verilog)
net "rd_sel_1[1]" in work.decoder(verilog)
net "fsm_dly365" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly366" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly367" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly368" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly369" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly370" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net cmp_ctl_2[0]</font>
24) instance work.decoder(verilog)-cmp_ctl_2[2:0], output net "cmp_ctl_2[0]" in work.decoder(verilog)
input nets to instance:
net "un1_fsm_dly352_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_1_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "un1_alu_we_3_sqmuxa" in work.decoder(verilog)
net "cmp_ctl_1[0]" in work.decoder(verilog)
net "cmp_ctl_1[1]" in work.decoder(verilog)
net "cmp_ctl_1[2]" in work.decoder(verilog)
net "fsm_dly352" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly353" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly354" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly355" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net cmp_ctl_2[1]</font>
25) instance work.decoder(verilog)-cmp_ctl_2[2:0], output net "cmp_ctl_2[1]" in work.decoder(verilog)
input nets to instance:
net "un1_fsm_dly352_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_1_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "un1_alu_we_3_sqmuxa" in work.decoder(verilog)
net "cmp_ctl_1[0]" in work.decoder(verilog)
net "cmp_ctl_1[1]" in work.decoder(verilog)
net "cmp_ctl_1[2]" in work.decoder(verilog)
net "fsm_dly352" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly353" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly354" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly355" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net cmp_ctl_2[2]</font>
26) instance work.decoder(verilog)-cmp_ctl_2[2:0], output net "cmp_ctl_2[2]" in work.decoder(verilog)
input nets to instance:
net "un1_fsm_dly352_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_1_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "un1_alu_we_3_sqmuxa" in work.decoder(verilog)
net "cmp_ctl_1[0]" in work.decoder(verilog)
net "cmp_ctl_1[1]" in work.decoder(verilog)
net "cmp_ctl_1[2]" in work.decoder(verilog)
net "fsm_dly352" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly353" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly354" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly355" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net dmem_ctl_2[0]</font>
27) instance work.decoder(verilog)-dmem_ctl_2[3:0], output net "dmem_ctl_2[0]" in work.decoder(verilog)
input nets to instance:
net "un1_fsm_dly365_2" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "un1_alu_we_3_sqmuxa" in work.decoder(verilog)
net "dmem_ctl_1[0]" in work.decoder(verilog)
net "dmem_ctl_1[1]" in work.decoder(verilog)
net "dmem_ctl_1[2]" in work.decoder(verilog)
net "dmem_ctl_1[3]" in work.decoder(verilog)
net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly365" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly366" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly368" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly369" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly370" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net dmem_ctl_2[1]</font>
28) instance work.decoder(verilog)-dmem_ctl_2[3:0], output net "dmem_ctl_2[1]" in work.decoder(verilog)
input nets to instance:
net "un1_fsm_dly365_2" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "un1_alu_we_3_sqmuxa" in work.decoder(verilog)
net "dmem_ctl_1[0]" in work.decoder(verilog)
net "dmem_ctl_1[1]" in work.decoder(verilog)
net "dmem_ctl_1[2]" in work.decoder(verilog)
net "dmem_ctl_1[3]" in work.decoder(verilog)
net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly365" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly366" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly368" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly369" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly370" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net dmem_ctl_2[2]</font>
29) instance work.decoder(verilog)-dmem_ctl_2[3:0], output net "dmem_ctl_2[2]" in work.decoder(verilog)
input nets to instance:
net "un1_fsm_dly365_2" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "un1_alu_we_3_sqmuxa" in work.decoder(verilog)
net "dmem_ctl_1[0]" in work.decoder(verilog)
net "dmem_ctl_1[1]" in work.decoder(verilog)
net "dmem_ctl_1[2]" in work.decoder(verilog)
net "dmem_ctl_1[3]" in work.decoder(verilog)
net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly365" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly366" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly368" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly369" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly370" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net dmem_ctl_2[3]</font>
30) instance work.decoder(verilog)-dmem_ctl_2[3:0], output net "dmem_ctl_2[3]" in work.decoder(verilog)
input nets to instance:
net "un1_fsm_dly365_2" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "un1_alu_we_3_sqmuxa" in work.decoder(verilog)
net "dmem_ctl_1[0]" in work.decoder(verilog)
net "dmem_ctl_1[1]" in work.decoder(verilog)
net "dmem_ctl_1[2]" in work.decoder(verilog)
net "dmem_ctl_1[3]" in work.decoder(verilog)
net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly365" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly366" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly368" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly369" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly370" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
End of loops
<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:150:83:150:89:@W:BN132:@XP_MSG">ulit.v(150)</a><!@TM:1223605618> | Removing sequential instance mips_core.alu_pass0.r32_o[0], because it is equivalent to instance mips_core.MEM_CTL.dmem_ctl_post.byte_addr_o[0]</font>
<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:150:83:150:89:@W:BN132:@XP_MSG">ulit.v(150)</a><!@TM:1223605618> | Removing sequential instance mips_core.alu_pass0.r32_o[1], because it is equivalent to instance mips_core.MEM_CTL.dmem_ctl_post.byte_addr_o[1]</font>
@N: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:572:4:572:10:@N::@XP_MSG">exec_stage.v(572)</a><!@TM:1223605618> | Found counter in view:work.muldiv_ff(verilog) inst count[5:0]
Warning: Found 30 combinational loops!
Each loop is reported with an instance in the loop
and nets connected to that instance.
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
1) instance fsm_dly_2[2:0] work.decoder(verilog)-fsm_dly_2[2:0], output net "fsm_dly_2[0]" in work.decoder(verilog)
input nets to instance:
net "alu_func_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_1_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_3_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_4_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_5_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_6_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_7_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_8_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_9_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_10_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_11_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_12_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_13_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_14_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_15_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_16_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_17_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_18_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_19_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_20_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_21_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_22_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_23_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_24_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_25_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_26_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_27_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_28_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_3_sqmuxa" in work.decoder(verilog)
net "fsm_dly_1[0]" in work.decoder(verilog)
net "fsm_dly_1[1]" in work.decoder(verilog)
net "fsm_dly_1[2]" in work.decoder(verilog)
net "alu_we_4_sqmuxa" in work.decoder(verilog)
net "fsm_dly_1[0]" in work.decoder(verilog)
net "fsm_dly_1[1]" in work.decoder(verilog)
net "fsm_dly_1[2]" in work.decoder(verilog)
net "fsm_dly350" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly351" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly352" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly353" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly354" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly355" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly356" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly357" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly358" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly359" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly360" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly361" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly362" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly363" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
net "fsm_dly_1[0]" in work.decoder(verilog)
net "fsm_dly_1[1]" in work.decoder(verilog)
net "fsm_dly_1[2]" in work.decoder(verilog)
net "fsm_dly365" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly366" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly367" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly368" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly369" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly370" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
2) instance fsm_dly_2[2:0] work.decoder(verilog)-fsm_dly_2[2:0], output net "fsm_dly_2[1]" in work.decoder(verilog)
input nets to instance:
net "alu_func_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_1_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_3_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_4_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_5_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_6_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_7_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_8_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_9_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_10_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_11_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_12_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_13_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_14_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_15_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_16_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_17_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_18_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_19_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_20_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_21_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_22_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_23_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_24_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_25_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_26_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_27_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_28_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_3_sqmuxa" in work.decoder(verilog)
net "fsm_dly_1[0]" in work.decoder(verilog)
net "fsm_dly_1[1]" in work.decoder(verilog)
net "fsm_dly_1[2]" in work.decoder(verilog)
net "alu_we_4_sqmuxa" in work.decoder(verilog)
net "fsm_dly_1[0]" in work.decoder(verilog)
net "fsm_dly_1[1]" in work.decoder(verilog)
net "fsm_dly_1[2]" in work.decoder(verilog)
net "fsm_dly350" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly351" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly352" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly353" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly354" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly355" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly356" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly357" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly358" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly359" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly360" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly361" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly362" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly363" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
net "fsm_dly_1[0]" in work.decoder(verilog)
net "fsm_dly_1[1]" in work.decoder(verilog)
net "fsm_dly_1[2]" in work.decoder(verilog)
net "fsm_dly365" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly366" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly367" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly368" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly369" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly370" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
3) instance fsm_dly_2[2:0] work.decoder(verilog)-fsm_dly_2[2:0], output net "fsm_dly_2[2]" in work.decoder(verilog)
input nets to instance:
net "alu_func_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_1_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_3_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_4_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_5_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_6_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_7_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_8_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_9_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_10_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_11_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_12_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_13_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_14_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_15_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_16_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_17_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_18_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_19_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_20_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_21_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_22_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_23_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_24_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_25_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_26_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_27_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_28_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_3_sqmuxa" in work.decoder(verilog)
net "fsm_dly_1[0]" in work.decoder(verilog)
net "fsm_dly_1[1]" in work.decoder(verilog)
net "fsm_dly_1[2]" in work.decoder(verilog)
net "alu_we_4_sqmuxa" in work.decoder(verilog)
net "fsm_dly_1[0]" in work.decoder(verilog)
net "fsm_dly_1[1]" in work.decoder(verilog)
net "fsm_dly_1[2]" in work.decoder(verilog)
net "fsm_dly350" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly351" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly352" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly353" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly354" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly355" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly356" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly357" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly358" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly359" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly360" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly361" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly362" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly363" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
net "fsm_dly_1[0]" in work.decoder(verilog)
net "fsm_dly_1[1]" in work.decoder(verilog)
net "fsm_dly_1[2]" in work.decoder(verilog)
net "fsm_dly365" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly366" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly367" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly368" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly369" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly370" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
4) instance ext_ctl_1[0] work.decoder(verilog)-ext_ctl_1[0], output net "ext_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "ext_ctl_2[0]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
5) instance ext_ctl_1[1] work.decoder(verilog)-ext_ctl_1[1], output net "ext_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "ext_ctl_2[1]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6) instance ext_ctl_1[2] work.decoder(verilog)-ext_ctl_1[2], output net "ext_ctl_1[2]" in work.decoder(verilog)
input nets to instance:
net "ext_ctl_2[2]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7) instance rd_sel_1[0] work.decoder(verilog)-rd_sel_1[0], output net "rd_sel_1[0]" in work.decoder(verilog)
input nets to instance:
net "rd_sel_2[0]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
8) instance rd_sel_1[1] work.decoder(verilog)-rd_sel_1[1], output net "rd_sel_1[1]" in work.decoder(verilog)
input nets to instance:
net "rd_sel_2[1]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "un1_ins_i_22" in work.decoder(verilog)
net "fsm_dly373" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
9) instance cmp_ctl_1[0] work.decoder(verilog)-cmp_ctl_1[0], output net "cmp_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "cmp_ctl_2[0]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
10) instance cmp_ctl_1[1] work.decoder(verilog)-cmp_ctl_1[1], output net "cmp_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "cmp_ctl_2[1]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
11) instance cmp_ctl_1[2] work.decoder(verilog)-cmp_ctl_1[2], output net "cmp_ctl_1[2]" in work.decoder(verilog)
input nets to instance:
net "cmp_ctl_2[2]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
12) instance pc_gen_ctl_1[0] work.decoder(verilog)-pc_gen_ctl_1[0], output net "pc_gen_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "pc_gen_ctl_2[0]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
13) instance pc_gen_ctl_1[1] work.decoder(verilog)-pc_gen_ctl_1[1], output net "pc_gen_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "pc_gen_ctl_2[1]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
14) instance pc_gen_ctl_1[2] work.decoder(verilog)-pc_gen_ctl_1[2], output net "pc_gen_ctl_1[2]" in work.decoder(verilog)
input nets to instance:
net "pc_gen_ctl_2[2]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
15) instance muxa_ctl_1[0] work.decoder(verilog)-muxa_ctl_1[0], output net "muxa_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "muxa_ctl_2[0]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
16) instance muxa_ctl_1[1] work.decoder(verilog)-muxa_ctl_1[1], output net "muxa_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "muxa_ctl_2[1]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
17) instance muxb_ctl_1[0] work.decoder(verilog)-muxb_ctl_1[0], output net "muxb_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "muxb_ctl_2[0]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
18) instance muxb_ctl_1[1] work.decoder(verilog)-muxb_ctl_1[1], output net "muxb_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "muxb_ctl_2[1]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
19) instance alu_func_1[0] work.decoder(verilog)-alu_func_1[0], output net "alu_func_1[0]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[0]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
20) instance alu_func_1[1] work.decoder(verilog)-alu_func_1[1], output net "alu_func_1[1]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[1]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
21) instance alu_func_1[2] work.decoder(verilog)-alu_func_1[2], output net "alu_func_1[2]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[2]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
22) instance alu_func_1[3] work.decoder(verilog)-alu_func_1[3], output net "alu_func_1[3]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[3]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
23) instance alu_func_1[4] work.decoder(verilog)-alu_func_1[4], output net "alu_func_1[4]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[4]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
24) instance dmem_ctl_1[0] work.decoder(verilog)-dmem_ctl_1[0], output net "dmem_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "dmem_ctl_2[0]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
25) instance dmem_ctl_1[1] work.decoder(verilog)-dmem_ctl_1[1], output net "dmem_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "dmem_ctl_2[1]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "un1_ins_i_22" in work.decoder(verilog)
net "fsm_dly373" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
26) instance dmem_ctl_1[2] work.decoder(verilog)-dmem_ctl_1[2], output net "dmem_ctl_1[2]" in work.decoder(verilog)
input nets to instance:
net "dmem_ctl_2[2]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "un1_ins_i_24" in work.decoder(verilog)
net "un1_ins_i_15" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
27) instance dmem_ctl_1[3] work.decoder(verilog)-dmem_ctl_1[3], output net "dmem_ctl_1[3]" in work.decoder(verilog)
input nets to instance:
net "dmem_ctl_2[3]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
28) instance alu_we[0] work.decoder(verilog)-alu_we[0], output net "alu_we[0]" in work.decoder(verilog)
input nets to instance:
net "alu_we_1[0]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
29) instance wb_mux[0] work.decoder(verilog)-wb_mux[0], output net "wb_mux[0]" in work.decoder(verilog)
input nets to instance:
net "wb_mux_1[0]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
30) instance wb_we[0] work.decoder(verilog)-wb_we[0], output net "wb_we[0]" in work.decoder(verilog)
input nets to instance:
net "wb_we_1[0]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
End of loops
Warning: Found 28 combinational loops!
Each loop is reported with an instance in the loop
and nets connected to that instance.
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
1) instance fsm_dly_2[2:0] work.decoder(verilog)-fsm_dly_2[2:0], output net "fsm_dly_2[0]" in work.decoder(verilog)
input nets to instance:
net "alu_func_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_1_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_3_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_4_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_5_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_6_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_7_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_8_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_9_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_10_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_11_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_12_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_13_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_14_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_15_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_16_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_17_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_18_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_19_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_20_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_21_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_22_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_23_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_24_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_25_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_26_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_27_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_28_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_3_sqmuxa" in work.decoder(verilog)
net "fsm_dly_1[0]" in work.decoder(verilog)
net "fsm_dly_1[1]" in work.decoder(verilog)
net "fsm_dly_1[2]" in work.decoder(verilog)
net "alu_we_4_sqmuxa" in work.decoder(verilog)
net "fsm_dly_1[0]" in work.decoder(verilog)
net "fsm_dly_1[1]" in work.decoder(verilog)
net "fsm_dly_1[2]" in work.decoder(verilog)
net "fsm_dly350" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly351" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "fsm_dly352" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly353" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly354" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly355" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly356" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly357" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly358" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly359" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly360" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly361" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly362" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly363" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
net "fsm_dly_1[0]" in work.decoder(verilog)
net "fsm_dly_1[1]" in work.decoder(verilog)
net "fsm_dly_1[2]" in work.decoder(verilog)
net "fsm_dly365" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly366" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly367" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly368" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly369" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "fsm_dly370" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
2) instance ext_ctl_1[0] work.decoder(verilog)-ext_ctl_1[0], output net "ext_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "ext_ctl_2[0]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
3) instance ext_ctl_1[1] work.decoder(verilog)-ext_ctl_1[1], output net "ext_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "ext_ctl_2[1]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
4) instance ext_ctl_1[2] work.decoder(verilog)-ext_ctl_1[2], output net "ext_ctl_1[2]" in work.decoder(verilog)
input nets to instance:
net "ext_ctl_2[2]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
5) instance rd_sel_1[0] work.decoder(verilog)-rd_sel_1[0], output net "rd_sel_1[0]" in work.decoder(verilog)
input nets to instance:
net "rd_sel_2[0]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6) instance rd_sel_1[1] work.decoder(verilog)-rd_sel_1[1], output net "rd_sel_1[1]" in work.decoder(verilog)
input nets to instance:
net "rd_sel_2[1]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "un1_ins_i_22" in work.decoder(verilog)
net "fsm_dly373" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7) instance cmp_ctl_1[0] work.decoder(verilog)-cmp_ctl_1[0], output net "cmp_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "cmp_ctl_2[0]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
8) instance cmp_ctl_1[1] work.decoder(verilog)-cmp_ctl_1[1], output net "cmp_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "cmp_ctl_2[1]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
9) instance cmp_ctl_1[2] work.decoder(verilog)-cmp_ctl_1[2], output net "cmp_ctl_1[2]" in work.decoder(verilog)
input nets to instance:
net "cmp_ctl_2[2]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
10) instance pc_gen_ctl_1[0] work.decoder(verilog)-pc_gen_ctl_1[0], output net "pc_gen_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "pc_gen_ctl_2[0]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
11) instance pc_gen_ctl_1[1] work.decoder(verilog)-pc_gen_ctl_1[1], output net "pc_gen_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "pc_gen_ctl_2[1]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
12) instance pc_gen_ctl_1[2] work.decoder(verilog)-pc_gen_ctl_1[2], output net "pc_gen_ctl_1[2]" in work.decoder(verilog)
input nets to instance:
net "pc_gen_ctl_2[2]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
13) instance muxa_ctl_1[0] work.decoder(verilog)-muxa_ctl_1[0], output net "muxa_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "muxa_ctl_2[0]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
14) instance muxa_ctl_1[1] work.decoder(verilog)-muxa_ctl_1[1], output net "muxa_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "muxa_ctl_2[1]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
15) instance muxb_ctl_1[0] work.decoder(verilog)-muxb_ctl_1[0], output net "muxb_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "muxb_ctl_2[0]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
16) instance muxb_ctl_1[1] work.decoder(verilog)-muxb_ctl_1[1], output net "muxb_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "muxb_ctl_2[1]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
17) instance alu_func_1[0] work.decoder(verilog)-alu_func_1[0], output net "alu_func_1[0]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[0]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
18) instance alu_func_1[1] work.decoder(verilog)-alu_func_1[1], output net "alu_func_1[1]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[1]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
19) instance alu_func_1[2] work.decoder(verilog)-alu_func_1[2], output net "alu_func_1[2]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[2]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
20) instance alu_func_1[3] work.decoder(verilog)-alu_func_1[3], output net "alu_func_1[3]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[3]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
21) instance alu_func_1[4] work.decoder(verilog)-alu_func_1[4], output net "alu_func_1[4]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[4]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
22) instance dmem_ctl_1[0] work.decoder(verilog)-dmem_ctl_1[0], output net "dmem_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "dmem_ctl_2[0]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
23) instance dmem_ctl_1[1] work.decoder(verilog)-dmem_ctl_1[1], output net "dmem_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "dmem_ctl_2[1]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "un1_ins_i_22" in work.decoder(verilog)
net "fsm_dly373" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
24) instance dmem_ctl_1[2] work.decoder(verilog)-dmem_ctl_1[2], output net "dmem_ctl_1[2]" in work.decoder(verilog)
input nets to instance:
net "dmem_ctl_2[2]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "un1_ins_i_24" in work.decoder(verilog)
net "un1_ins_i_15" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
25) instance dmem_ctl_1[3] work.decoder(verilog)-dmem_ctl_1[3], output net "dmem_ctl_1[3]" in work.decoder(verilog)
input nets to instance:
net "dmem_ctl_2[3]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
26) instance alu_we[0] work.decoder(verilog)-alu_we[0], output net "alu_we[0]" in work.decoder(verilog)
input nets to instance:
net "alu_we_1[0]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
27) instance wb_mux[0] work.decoder(verilog)-wb_mux[0], output net "wb_mux[0]" in work.decoder(verilog)
input nets to instance:
net "wb_mux_1[0]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
28) instance wb_we[0] work.decoder(verilog)-wb_we[0], output net "wb_we[0]" in work.decoder(verilog)
input nets to instance:
net "wb_we_1[0]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
End of loops
@N: : <a href="e:\mips789\mips789\rtl\verilog\mips_uart.v:243:4:243:10:@N::@XP_MSG">mips_uart.v(243)</a><!@TM:1223605618> | Found counter in view:work.uart_read(verilog) inst clk_ctr[15:0]
@N: : <a href="e:\mips789\mips789\rtl\verilog\mips_uart.v:256:4:256:10:@N::@XP_MSG">mips_uart.v(256)</a><!@TM:1223605618> | Found counter in view:work.uart_read(verilog) inst bit_ctr[2:0]
@N: : <a href="e:\mips789\mips789\rtl\verilog\mips_uart.v:138:4:138:10:@N::@XP_MSG">mips_uart.v(138)</a><!@TM:1223605618> | Found counter in view:work.uart_write(verilog) inst clk_ctr[15:0]
@N: : <a href="e:\mips789\mips789\rtl\verilog\mips_uart.v:151:4:151:10:@N::@XP_MSG">mips_uart.v(151)</a><!@TM:1223605618> | Found counter in view:work.uart_write(verilog) inst bit_ctr[2:0]
@N:<a href="@N:MO106:@XP_HELP">MO106</a> : <a href="e:\mips789\mips789\rtl\verilog\dvc.v:67:12:67:16:@N:MO106:@XP_MSG">dvc.v(67)</a><!@TM:1223605618> | Found ROM, 'seg_20[6:0]', 16 words by 7 bits
@N:<a href="@N:MO106:@XP_HELP">MO106</a> : <a href="e:\mips789\mips789\rtl\verilog\dvc.v:67:12:67:16:@N:MO106:@XP_MSG">dvc.v(67)</a><!@TM:1223605618> | Found ROM, 'seg[6:0]', 16 words by 7 bits
@N: : <a href="e:\mips789\mips789\rtl\verilog\dvc.v:23:4:23:10:@N::@XP_MSG">dvc.v(23)</a><!@TM:1223605618> | Found counter in view:work.tmr0(verilog) inst cntr[31:0]
Warning: Found 28 combinational loops!
Each loop is reported with an instance in the loop
and nets connected to that instance.
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
1) instance fsm_dly_2[0] work.decoder(verilog)-fsm_dly_2[0], output net "fsm_dly_2[0]" in work.decoder(verilog)
input nets to instance:
net "N_172" in work.decoder(verilog)
net "fsm_dly_1[0]" in work.decoder(verilog)
net "N_415" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
2) instance ext_ctl_1[0] work.decoder(verilog)-ext_ctl_1[0], output net "ext_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "ext_ctl_2[0]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
3) instance ext_ctl_1[1] work.decoder(verilog)-ext_ctl_1[1], output net "ext_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "ext_ctl_2[1]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
4) instance ext_ctl_1[2] work.decoder(verilog)-ext_ctl_1[2], output net "ext_ctl_1[2]" in work.decoder(verilog)
input nets to instance:
net "ext_ctl_2[2]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
5) instance rd_sel_1[0] work.decoder(verilog)-rd_sel_1[0], output net "rd_sel_1[0]" in work.decoder(verilog)
input nets to instance:
net "rd_sel_2[0]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6) instance rd_sel_1[1] work.decoder(verilog)-rd_sel_1[1], output net "rd_sel_1[1]" in work.decoder(verilog)
input nets to instance:
net "rd_sel_2[1]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "N_438" in work.decoder(verilog)
net "fsm_dly373" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7) instance cmp_ctl_1[0] work.decoder(verilog)-cmp_ctl_1[0], output net "cmp_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "cmp_ctl_2[0]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
8) instance cmp_ctl_1[1] work.decoder(verilog)-cmp_ctl_1[1], output net "cmp_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "cmp_ctl_2[1]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
9) instance cmp_ctl_1[2] work.decoder(verilog)-cmp_ctl_1[2], output net "cmp_ctl_1[2]" in work.decoder(verilog)
input nets to instance:
net "cmp_ctl_2[2]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
10) instance pc_gen_ctl_1[0] work.decoder(verilog)-pc_gen_ctl_1[0], output net "pc_gen_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "pc_gen_ctl_2[0]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
11) instance pc_gen_ctl_1[1] work.decoder(verilog)-pc_gen_ctl_1[1], output net "pc_gen_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "pc_gen_ctl_2[1]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
12) instance pc_gen_ctl_1[2] work.decoder(verilog)-pc_gen_ctl_1[2], output net "pc_gen_ctl_1[2]" in work.decoder(verilog)
input nets to instance:
net "pc_gen_ctl_2[2]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
13) instance muxa_ctl_1[0] work.decoder(verilog)-muxa_ctl_1[0], output net "muxa_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "muxa_ctl_2[0]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
14) instance muxa_ctl_1[1] work.decoder(verilog)-muxa_ctl_1[1], output net "muxa_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "muxa_ctl_2[1]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
15) instance muxb_ctl_1[0] work.decoder(verilog)-muxb_ctl_1[0], output net "muxb_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "muxb_ctl_2[0]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
16) instance muxb_ctl_1[1] work.decoder(verilog)-muxb_ctl_1[1], output net "muxb_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "muxb_ctl_2[1]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
17) instance alu_func_1[0] work.decoder(verilog)-alu_func_1[0], output net "alu_func_1[0]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[0]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
18) instance alu_func_1[1] work.decoder(verilog)-alu_func_1[1], output net "alu_func_1[1]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[1]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
19) instance alu_func_1[2] work.decoder(verilog)-alu_func_1[2], output net "alu_func_1[2]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[2]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
20) instance alu_func_1[3] work.decoder(verilog)-alu_func_1[3], output net "alu_func_1[3]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[3]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
21) instance alu_func_1[4] work.decoder(verilog)-alu_func_1[4], output net "alu_func_1[4]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[4]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
22) instance dmem_ctl_1[0] work.decoder(verilog)-dmem_ctl_1[0], output net "dmem_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "dmem_ctl_2[0]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
23) instance dmem_ctl_1[1] work.decoder(verilog)-dmem_ctl_1[1], output net "dmem_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "dmem_ctl_2[1]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "N_438" in work.decoder(verilog)
net "fsm_dly373" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
24) instance dmem_ctl_1[2] work.decoder(verilog)-dmem_ctl_1[2], output net "dmem_ctl_1[2]" in work.decoder(verilog)
input nets to instance:
net "dmem_ctl_2[2]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "un1_ins_i_24" in work.decoder(verilog)
net "un1_ins_i_15" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
25) instance dmem_ctl_1[3] work.decoder(verilog)-dmem_ctl_1[3], output net "dmem_ctl_1[3]" in work.decoder(verilog)
input nets to instance:
net "dmem_ctl_2[3]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
26) instance alu_we[0] work.decoder(verilog)-alu_we[0], output net "alu_we[0]" in work.decoder(verilog)
input nets to instance:
net "alu_we_1[0]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
27) instance wb_mux[0] work.decoder(verilog)-wb_mux[0], output net "wb_mux[0]" in work.decoder(verilog)
input nets to instance:
net "wb_mux_1[0]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
28) instance wb_we[0] work.decoder(verilog)-wb_we[0], output net "wb_we[0]" in work.decoder(verilog)
input nets to instance:
net "wb_we_1[0]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
End of loops
Warning: Found 28 combinational loops!
Each loop is reported with an instance in the loop
and nets connected to that instance.
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
1) instance fsm_dly_2[0] work.decoder(verilog)-fsm_dly_2[0], output net "fsm_dly_2[0]" in work.decoder(verilog)
input nets to instance:
net "N_172" in work.decoder(verilog)
net "fsm_dly_1[0]" in work.decoder(verilog)
net "N_415" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
2) instance ext_ctl_1[0] work.decoder(verilog)-ext_ctl_1[0], output net "ext_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "ext_ctl_2[0]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
3) instance ext_ctl_1[1] work.decoder(verilog)-ext_ctl_1[1], output net "ext_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "ext_ctl_2[1]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
4) instance ext_ctl_1[2] work.decoder(verilog)-ext_ctl_1[2], output net "ext_ctl_1[2]" in work.decoder(verilog)
input nets to instance:
net "ext_ctl_2[2]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
5) instance rd_sel_1[0] work.decoder(verilog)-rd_sel_1[0], output net "rd_sel_1[0]" in work.decoder(verilog)
input nets to instance:
net "rd_sel_2[0]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6) instance rd_sel_1[1] work.decoder(verilog)-rd_sel_1[1], output net "rd_sel_1[1]" in work.decoder(verilog)
input nets to instance:
net "rd_sel_2[1]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "N_438" in work.decoder(verilog)
net "fsm_dly373" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7) instance cmp_ctl_1[0] work.decoder(verilog)-cmp_ctl_1[0], output net "cmp_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "cmp_ctl_2[0]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
8) instance cmp_ctl_1[1] work.decoder(verilog)-cmp_ctl_1[1], output net "cmp_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "cmp_ctl_2[1]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
9) instance cmp_ctl_1[2] work.decoder(verilog)-cmp_ctl_1[2], output net "cmp_ctl_1[2]" in work.decoder(verilog)
input nets to instance:
net "cmp_ctl_2[2]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
10) instance pc_gen_ctl_1[0] work.decoder(verilog)-pc_gen_ctl_1[0], output net "pc_gen_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "pc_gen_ctl_2[0]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
11) instance pc_gen_ctl_1[1] work.decoder(verilog)-pc_gen_ctl_1[1], output net "pc_gen_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "pc_gen_ctl_2[1]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
12) instance pc_gen_ctl_1[2] work.decoder(verilog)-pc_gen_ctl_1[2], output net "pc_gen_ctl_1[2]" in work.decoder(verilog)
input nets to instance:
net "pc_gen_ctl_2[2]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
13) instance muxa_ctl_1[0] work.decoder(verilog)-muxa_ctl_1[0], output net "muxa_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "muxa_ctl_2[0]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
14) instance muxa_ctl_1[1] work.decoder(verilog)-muxa_ctl_1[1], output net "muxa_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "muxa_ctl_2[1]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
15) instance muxb_ctl_1[0] work.decoder(verilog)-muxb_ctl_1[0], output net "muxb_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "muxb_ctl_2[0]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
16) instance muxb_ctl_1[1] work.decoder(verilog)-muxb_ctl_1[1], output net "muxb_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "muxb_ctl_2[1]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
17) instance alu_func_1[0] work.decoder(verilog)-alu_func_1[0], output net "alu_func_1[0]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[0]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
18) instance alu_func_1[1] work.decoder(verilog)-alu_func_1[1], output net "alu_func_1[1]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[1]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
19) instance alu_func_1[2] work.decoder(verilog)-alu_func_1[2], output net "alu_func_1[2]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[2]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
20) instance alu_func_1[3] work.decoder(verilog)-alu_func_1[3], output net "alu_func_1[3]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[3]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
21) instance alu_func_1[4] work.decoder(verilog)-alu_func_1[4], output net "alu_func_1[4]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[4]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
22) instance dmem_ctl_1[0] work.decoder(verilog)-dmem_ctl_1[0], output net "dmem_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "dmem_ctl_2[0]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
23) instance dmem_ctl_1[1] work.decoder(verilog)-dmem_ctl_1[1], output net "dmem_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "dmem_ctl_2[1]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "N_438" in work.decoder(verilog)
net "fsm_dly373" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
24) instance dmem_ctl_1[2] work.decoder(verilog)-dmem_ctl_1[2], output net "dmem_ctl_1[2]" in work.decoder(verilog)
input nets to instance:
net "dmem_ctl_2[2]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "un1_ins_i_24" in work.decoder(verilog)
net "un1_ins_i_15" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
25) instance dmem_ctl_1[3] work.decoder(verilog)-dmem_ctl_1[3], output net "dmem_ctl_1[3]" in work.decoder(verilog)
input nets to instance:
net "dmem_ctl_2[3]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
26) instance alu_we[0] work.decoder(verilog)-alu_we[0], output net "alu_we[0]" in work.decoder(verilog)
input nets to instance:
net "alu_we_1[0]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
27) instance wb_mux[0] work.decoder(verilog)-wb_mux[0], output net "wb_mux[0]" in work.decoder(verilog)
input nets to instance:
net "wb_mux_1[0]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
28) instance wb_we[0] work.decoder(verilog)-wb_we[0], output net "wb_we[0]" in work.decoder(verilog)
input nets to instance:
net "wb_we_1[0]" in work.decoder(verilog)
net "un1_fsm_dly370" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
End of loops
Automatic dissolve during optimization of view:work.mips_core(verilog) of iRF_stage.reg_bank(reg_array)
Auto Dissolve of decoder_pipe (inst of view:work.decode_pipe(verilog))
Auto Dissolve of iRF_stage.i_cmp (inst of view:work.compare(verilog))
Auto Dissolve of mips_tmr0 (inst of view:work.tmr0(verilog))
Warning: Found 28 combinational loops!
Each loop is reported with an instance in the loop
and nets connected to that instance.
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
1) instance mips_core.decoder_pipe.idecoder.fsm_dly_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.fsm_dly_1[0], output net "mips_core.BUS197[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.fsm_dly_2[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
2) instance mips_core.decoder_pipe.idecoder.ext_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.ext_ctl_1[0], output net "mips_core.decoder_pipe.BUS2072[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.N_1345" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
3) instance mips_core.decoder_pipe.idecoder.ext_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.ext_ctl_1[1], output net "mips_core.decoder_pipe.BUS2072[1]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.N_1346" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
4) instance mips_core.decoder_pipe.idecoder.ext_ctl_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.ext_ctl_1[2], output net "mips_core.decoder_pipe.BUS2072[2]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.ext_ctl_2[2]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
5) instance mips_core.decoder_pipe.idecoder.rd_sel_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.rd_sel_1[0], output net "mips_core.decoder_pipe.BUS2110[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.rd_sel_2[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6) instance mips_core.decoder_pipe.idecoder.rd_sel_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.rd_sel_1[1], output net "mips_core.decoder_pipe.BUS2110[1]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.rd_sel_2[1]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_438" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.fsm_dly373" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7) instance mips_core.decoder_pipe.idecoder.cmp_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.cmp_ctl_1[0], output net "mips_core.decoder_pipe.BUS2056[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.cmp_ctl_2[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
8) instance mips_core.decoder_pipe.idecoder.cmp_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.cmp_ctl_1[1], output net "mips_core.decoder_pipe.BUS2056[1]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.cmp_ctl_2[1]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
9) instance mips_core.decoder_pipe.idecoder.cmp_ctl_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.cmp_ctl_1[2], output net "mips_core.decoder_pipe.BUS2056[2]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.cmp_ctl_2[2]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
10) instance mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[0], output net "mips_core.decoder_pipe.BUS2102[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.N_1348" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
11) instance mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[1], output net "mips_core.decoder_pipe.BUS2102[1]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.pc_gen_ctl_2[1]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
12) instance mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[2], output net "mips_core.decoder_pipe.BUS2102[2]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.N_1232_i" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
13) instance mips_core.decoder_pipe.idecoder.muxa_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxa_ctl_1[0], output net "mips_core.decoder_pipe.BUS2086[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.muxa_ctl_2[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
14) instance mips_core.decoder_pipe.idecoder.muxa_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxa_ctl_1[1], output net "mips_core.decoder_pipe.BUS2086[1]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.muxa_ctl_2[1]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
15) instance mips_core.decoder_pipe.idecoder.muxb_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxb_ctl_1[0], output net "mips_core.decoder_pipe.BUS2094[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.muxb_ctl_2[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
16) instance mips_core.decoder_pipe.idecoder.muxb_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxb_ctl_1[1], output net "mips_core.decoder_pipe.BUS2094[1]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.muxb_ctl_2[1]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
17) instance mips_core.decoder_pipe.idecoder.alu_func_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[0], output net "mips_core.decoder_pipe.BUS2040[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.alu_func_2[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
18) instance mips_core.decoder_pipe.idecoder.alu_func_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[1], output net "mips_core.decoder_pipe.BUS2040[1]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.alu_func_2[1]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
19) instance mips_core.decoder_pipe.idecoder.alu_func_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[2], output net "mips_core.decoder_pipe.BUS2040[2]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.N_1344" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
20) instance mips_core.decoder_pipe.idecoder.alu_func_1[3] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[3], output net "mips_core.decoder_pipe.BUS2040[3]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.alu_func_2[3]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
21) instance mips_core.decoder_pipe.idecoder.alu_func_1[4] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[4], output net "mips_core.decoder_pipe.BUS2040[4]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.alu_func_2[4]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
22) instance mips_core.decoder_pipe.idecoder.dmem_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[0], output net "mips_core.decoder_pipe.BUS2064[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
23) instance mips_core.decoder_pipe.idecoder.dmem_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[1], output net "mips_core.decoder_pipe.BUS2064[1]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[1]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_438" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.fsm_dly373" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
24) instance mips_core.decoder_pipe.idecoder.dmem_ctl_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[2], output net "mips_core.decoder_pipe.BUS2064[2]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[2]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_24" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_15" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
25) instance mips_core.decoder_pipe.idecoder.dmem_ctl_1[3] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[3], output net "mips_core.decoder_pipe.BUS2064[3]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[3]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
26) instance mips_core.decoder_pipe.idecoder.alu_we[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_we[0], output net "mips_core.decoder_pipe.BUS2048[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.alu_we_1[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
27) instance mips_core.decoder_pipe.idecoder.wb_mux[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.wb_mux[0], output net "mips_core.decoder_pipe.BUS2118[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.wb_mux_1[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
28) instance mips_core.decoder_pipe.idecoder.wb_we[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.wb_we[0], output net "mips_core.decoder_pipe.BUS2126[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.wb_we_1[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
End of loops
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:104:111:104:117:@W:BN116:@XP_MSG">ulit.v(104)</a><!@TM:1223605618> | Removing sequential instance mips_core.iRF_stage.ins_reg.r32_o[31] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:104:111:104:117:@W:BN116:@XP_MSG">ulit.v(104)</a><!@TM:1223605618> | Removing sequential instance mips_core.iRF_stage.ins_reg.r32_o[30] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:104:111:104:117:@W:BN116:@XP_MSG">ulit.v(104)</a><!@TM:1223605618> | Removing sequential instance mips_core.iRF_stage.ins_reg.r32_o[29] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:104:111:104:117:@W:BN116:@XP_MSG">ulit.v(104)</a><!@TM:1223605618> | Removing sequential instance mips_core.iRF_stage.ins_reg.r32_o[28] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:104:111:104:117:@W:BN116:@XP_MSG">ulit.v(104)</a><!@TM:1223605618> | Removing sequential instance mips_core.iRF_stage.ins_reg.r32_o[27] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:104:111:104:117:@W:BN116:@XP_MSG">ulit.v(104)</a><!@TM:1223605618> | Removing sequential instance mips_core.iRF_stage.ins_reg.r32_o[26] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
Warning: Found 28 combinational loops!
Each loop is reported with an instance in the loop
and nets connected to that instance.
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
1) instance mips_core.decoder_pipe.idecoder.fsm_dly_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.fsm_dly_1[0], output net "mips_core.BUS197[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.fsm_dly_2[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
2) instance mips_core.decoder_pipe.idecoder.ext_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.ext_ctl_1[0], output net "mips_core.decoder_pipe.BUS2072[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.N_1345" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
3) instance mips_core.decoder_pipe.idecoder.ext_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.ext_ctl_1[1], output net "mips_core.decoder_pipe.BUS2072[1]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.N_1346" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
4) instance mips_core.decoder_pipe.idecoder.ext_ctl_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.ext_ctl_1[2], output net "mips_core.decoder_pipe.BUS2072[2]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.ext_ctl_2[2]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
5) instance mips_core.decoder_pipe.idecoder.rd_sel_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.rd_sel_1[0], output net "mips_core.decoder_pipe.BUS2110[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.rd_sel_2[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6) instance mips_core.decoder_pipe.idecoder.rd_sel_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.rd_sel_1[1], output net "mips_core.decoder_pipe.BUS2110[1]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.rd_sel_2[1]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_438" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.fsm_dly373" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7) instance mips_core.decoder_pipe.idecoder.cmp_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.cmp_ctl_1[0], output net "mips_core.decoder_pipe.BUS2056[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.cmp_ctl_2[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
8) instance mips_core.decoder_pipe.idecoder.cmp_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.cmp_ctl_1[1], output net "mips_core.decoder_pipe.BUS2056[1]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.cmp_ctl_2[1]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
9) instance mips_core.decoder_pipe.idecoder.cmp_ctl_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.cmp_ctl_1[2], output net "mips_core.decoder_pipe.BUS2056[2]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.cmp_ctl_2[2]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
10) instance mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[0], output net "mips_core.decoder_pipe.BUS2102[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.N_1348" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
11) instance mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[1], output net "mips_core.decoder_pipe.BUS2102[1]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.pc_gen_ctl_2[1]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
12) instance mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[2], output net "mips_core.decoder_pipe.BUS2102[2]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.N_1232_i" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
13) instance mips_core.decoder_pipe.idecoder.muxa_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxa_ctl_1[0], output net "mips_core.decoder_pipe.BUS2086[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.muxa_ctl_2[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
14) instance mips_core.decoder_pipe.idecoder.muxa_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxa_ctl_1[1], output net "mips_core.decoder_pipe.BUS2086[1]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.muxa_ctl_2[1]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
15) instance mips_core.decoder_pipe.idecoder.muxb_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxb_ctl_1[0], output net "mips_core.decoder_pipe.BUS2094[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.muxb_ctl_2[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
16) instance mips_core.decoder_pipe.idecoder.muxb_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxb_ctl_1[1], output net "mips_core.decoder_pipe.BUS2094[1]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.muxb_ctl_2[1]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
17) instance mips_core.decoder_pipe.idecoder.alu_func_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[0], output net "mips_core.decoder_pipe.BUS2040[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.alu_func_2[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
18) instance mips_core.decoder_pipe.idecoder.alu_func_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[1], output net "mips_core.decoder_pipe.BUS2040[1]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.alu_func_2[1]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
19) instance mips_core.decoder_pipe.idecoder.alu_func_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[2], output net "mips_core.decoder_pipe.BUS2040[2]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.N_1344" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
20) instance mips_core.decoder_pipe.idecoder.alu_func_1[3] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[3], output net "mips_core.decoder_pipe.BUS2040[3]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.alu_func_2[3]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
21) instance mips_core.decoder_pipe.idecoder.alu_func_1[4] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[4], output net "mips_core.decoder_pipe.BUS2040[4]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.alu_func_2[4]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
22) instance mips_core.decoder_pipe.idecoder.dmem_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[0], output net "mips_core.decoder_pipe.BUS2064[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
23) instance mips_core.decoder_pipe.idecoder.dmem_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[1], output net "mips_core.decoder_pipe.BUS2064[1]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[1]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_438" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.fsm_dly373" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
24) instance mips_core.decoder_pipe.idecoder.dmem_ctl_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[2], output net "mips_core.decoder_pipe.BUS2064[2]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[2]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_18_m" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_15" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
25) instance mips_core.decoder_pipe.idecoder.dmem_ctl_1[3] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[3], output net "mips_core.decoder_pipe.BUS2064[3]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[3]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
26) instance mips_core.decoder_pipe.idecoder.alu_we[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_we[0], output net "mips_core.decoder_pipe.BUS2048[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.alu_we_1[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
27) instance mips_core.decoder_pipe.idecoder.wb_mux[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.wb_mux[0], output net "mips_core.decoder_pipe.BUS2118[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.wb_mux_1[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
28) instance mips_core.decoder_pipe.idecoder.wb_we[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.wb_we[0], output net "mips_core.decoder_pipe.BUS2126[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.wb_we_1[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
End of loops
Warning: Found 28 combinational loops!
Each loop is reported with an instance in the loop
and nets connected to that instance.
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
1) instance mips_core.decoder_pipe.idecoder.fsm_dly_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.fsm_dly_1[0], output net "mips_core.BUS197[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.fsm_dly_2[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
2) instance mips_core.decoder_pipe.idecoder.ext_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.ext_ctl_1[0], output net "mips_core.decoder_pipe.BUS2072[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.N_1345" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
3) instance mips_core.decoder_pipe.idecoder.ext_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.ext_ctl_1[1], output net "mips_core.decoder_pipe.BUS2072[1]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.N_1346" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
4) instance mips_core.decoder_pipe.idecoder.ext_ctl_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.ext_ctl_1[2], output net "mips_core.decoder_pipe.BUS2072[2]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.ext_ctl_2[2]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
5) instance mips_core.decoder_pipe.idecoder.rd_sel_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.rd_sel_1[0], output net "mips_core.decoder_pipe.BUS2110[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.rd_sel_2[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6) instance mips_core.decoder_pipe.idecoder.rd_sel_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.rd_sel_1[1], output net "mips_core.decoder_pipe.BUS2110[1]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.rd_sel_2[1]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_438" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.fsm_dly373" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7) instance mips_core.decoder_pipe.idecoder.cmp_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.cmp_ctl_1[0], output net "mips_core.decoder_pipe.BUS2056[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.cmp_ctl_2[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
8) instance mips_core.decoder_pipe.idecoder.cmp_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.cmp_ctl_1[1], output net "mips_core.decoder_pipe.BUS2056[1]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.cmp_ctl_2[1]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
9) instance mips_core.decoder_pipe.idecoder.cmp_ctl_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.cmp_ctl_1[2], output net "mips_core.decoder_pipe.BUS2056[2]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.cmp_ctl_2[2]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
10) instance mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[0], output net "mips_core.decoder_pipe.BUS2102[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.N_1348" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
11) instance mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[1], output net "mips_core.decoder_pipe.BUS2102[1]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.pc_gen_ctl_2[1]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
12) instance mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[2], output net "mips_core.decoder_pipe.BUS2102[2]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.N_1232_i" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
13) instance mips_core.decoder_pipe.idecoder.muxa_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxa_ctl_1[0], output net "mips_core.decoder_pipe.BUS2086[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.muxa_ctl_2[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
14) instance mips_core.decoder_pipe.idecoder.muxa_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxa_ctl_1[1], output net "mips_core.decoder_pipe.BUS2086[1]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.muxa_ctl_2[1]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
15) instance mips_core.decoder_pipe.idecoder.muxb_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxb_ctl_1[0], output net "mips_core.decoder_pipe.BUS2094[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.muxb_ctl_2[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
16) instance mips_core.decoder_pipe.idecoder.muxb_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxb_ctl_1[1], output net "mips_core.decoder_pipe.BUS2094[1]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.muxb_ctl_2[1]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
17) instance mips_core.decoder_pipe.idecoder.alu_func_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[0], output net "mips_core.decoder_pipe.BUS2040[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.alu_func_2[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
18) instance mips_core.decoder_pipe.idecoder.alu_func_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[1], output net "mips_core.decoder_pipe.BUS2040[1]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.alu_func_2[1]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
19) instance mips_core.decoder_pipe.idecoder.alu_func_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[2], output net "mips_core.decoder_pipe.BUS2040[2]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.N_1344" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
20) instance mips_core.decoder_pipe.idecoder.alu_func_1[3] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[3], output net "mips_core.decoder_pipe.BUS2040[3]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.alu_func_2[3]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
21) instance mips_core.decoder_pipe.idecoder.alu_func_1[4] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[4], output net "mips_core.decoder_pipe.BUS2040[4]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.alu_func_2[4]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
22) instance mips_core.decoder_pipe.idecoder.dmem_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[0], output net "mips_core.decoder_pipe.BUS2064[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
23) instance mips_core.decoder_pipe.idecoder.dmem_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[1], output net "mips_core.decoder_pipe.BUS2064[1]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[1]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_438" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.fsm_dly373" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
24) instance mips_core.decoder_pipe.idecoder.dmem_ctl_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[2], output net "mips_core.decoder_pipe.BUS2064[2]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[2]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_18_m" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_15" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
25) instance mips_core.decoder_pipe.idecoder.dmem_ctl_1[3] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[3], output net "mips_core.decoder_pipe.BUS2064[3]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[3]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
26) instance mips_core.decoder_pipe.idecoder.alu_we[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_we[0], output net "mips_core.decoder_pipe.BUS2048[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.alu_we_1[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
27) instance mips_core.decoder_pipe.idecoder.wb_mux[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.wb_mux[0], output net "mips_core.decoder_pipe.BUS2118[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.wb_mux_1[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
28) instance mips_core.decoder_pipe.idecoder.wb_we[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.wb_we[0], output net "mips_core.decoder_pipe.BUS2126[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.wb_we_1[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
End of loops
Warning: Found 28 combinational loops!
Each loop is reported with an instance in the loop
and nets connected to that instance.
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
1) instance mips_core.decoder_pipe.idecoder.fsm_dly_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.fsm_dly_1[0], output net "mips_core.BUS197[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.fsm_dly_2[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
2) instance mips_core.decoder_pipe.idecoder.ext_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.ext_ctl_1[0], output net "mips_core.decoder_pipe.BUS2072[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.N_1345" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
3) instance mips_core.decoder_pipe.idecoder.ext_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.ext_ctl_1[1], output net "mips_core.decoder_pipe.BUS2072[1]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.N_1346" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
4) instance mips_core.decoder_pipe.idecoder.ext_ctl_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.ext_ctl_1[2], output net "mips_core.decoder_pipe.BUS2072[2]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.ext_ctl_2[2]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
5) instance mips_core.decoder_pipe.idecoder.rd_sel_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.rd_sel_1[0], output net "mips_core.decoder_pipe.BUS2110[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.rd_sel_2[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6) instance mips_core.decoder_pipe.idecoder.rd_sel_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.rd_sel_1[1], output net "mips_core.decoder_pipe.BUS2110[1]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.rd_sel_2[1]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_438" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.fsm_dly373" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7) instance mips_core.decoder_pipe.idecoder.cmp_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.cmp_ctl_1[0], output net "mips_core.decoder_pipe.BUS2056[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.cmp_ctl_2[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
8) instance mips_core.decoder_pipe.idecoder.cmp_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.cmp_ctl_1[1], output net "mips_core.decoder_pipe.BUS2056[1]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.cmp_ctl_2[1]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
9) instance mips_core.decoder_pipe.idecoder.cmp_ctl_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.cmp_ctl_1[2], output net "mips_core.decoder_pipe.BUS2056[2]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.cmp_ctl_2[2]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
10) instance mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[0], output net "mips_core.decoder_pipe.BUS2102[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.N_1348" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
11) instance mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[1], output net "mips_core.decoder_pipe.BUS2102[1]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.pc_gen_ctl_2[1]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
12) instance mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[2], output net "mips_core.decoder_pipe.BUS2102[2]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.N_1232_i" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
13) instance mips_core.decoder_pipe.idecoder.muxa_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxa_ctl_1[0], output net "mips_core.decoder_pipe.BUS2086[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.muxa_ctl_2[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
14) instance mips_core.decoder_pipe.idecoder.muxa_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxa_ctl_1[1], output net "mips_core.decoder_pipe.BUS2086[1]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.muxa_ctl_2[1]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
15) instance mips_core.decoder_pipe.idecoder.muxb_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxb_ctl_1[0], output net "mips_core.decoder_pipe.BUS2094[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.muxb_ctl_2[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
16) instance mips_core.decoder_pipe.idecoder.muxb_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxb_ctl_1[1], output net "mips_core.decoder_pipe.BUS2094[1]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.muxb_ctl_2[1]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
17) instance mips_core.decoder_pipe.idecoder.alu_func_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[0], output net "mips_core.decoder_pipe.BUS2040[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.alu_func_2[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
18) instance mips_core.decoder_pipe.idecoder.alu_func_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[1], output net "mips_core.decoder_pipe.BUS2040[1]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.alu_func_2[1]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
19) instance mips_core.decoder_pipe.idecoder.alu_func_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[2], output net "mips_core.decoder_pipe.BUS2040[2]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.N_1344" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
20) instance mips_core.decoder_pipe.idecoder.alu_func_1[3] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[3], output net "mips_core.decoder_pipe.BUS2040[3]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.alu_func_2[3]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
21) instance mips_core.decoder_pipe.idecoder.alu_func_1[4] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[4], output net "mips_core.decoder_pipe.BUS2040[4]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.alu_func_2[4]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
22) instance mips_core.decoder_pipe.idecoder.dmem_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[0], output net "mips_core.decoder_pipe.BUS2064[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
23) instance mips_core.decoder_pipe.idecoder.dmem_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[1], output net "mips_core.decoder_pipe.BUS2064[1]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[1]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_438" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.fsm_dly373" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
24) instance mips_core.decoder_pipe.idecoder.dmem_ctl_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[2], output net "mips_core.decoder_pipe.BUS2064[2]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[2]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_18_m" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_15" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
25) instance mips_core.decoder_pipe.idecoder.dmem_ctl_1[3] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[3], output net "mips_core.decoder_pipe.BUS2064[3]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[3]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
26) instance mips_core.decoder_pipe.idecoder.alu_we[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_we[0], output net "mips_core.decoder_pipe.BUS2048[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.alu_we_1[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
27) instance mips_core.decoder_pipe.idecoder.wb_mux[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.wb_mux[0], output net "mips_core.decoder_pipe.BUS2118[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.wb_mux_1[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
28) instance mips_core.decoder_pipe.idecoder.wb_we[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.wb_we[0], output net "mips_core.decoder_pipe.BUS2126[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.wb_we_1[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
End of loops
Encoding state machine ScratchLib.imips_dvc.iuart0.uart_txd.ua_state_7_0c(gate_dflt)-imips_dvc.iuart0.uart_txd.ua_state[7:0]
original code -> new code
000 -> 00000000
001 -> 00000011
010 -> 00000101
011 -> 00001001
100 -> 00010001
101 -> 00100001
110 -> 01000001
111 -> 10000001
Encoding state machine ScratchLib.imips_dvc.iuart0.uart_rd_tak.ua_state_4_0c(gate_dflt)-imips_dvc.iuart0.uart_rd_tak.ua_state[4:0]
original code -> new code
000 -> 00000
001 -> 00011
010 -> 00101
011 -> 01001
100 -> 10001
Encoding state machine ScratchLib.mips_core.iRF_stage.MIAN_FSM.CurrState_Sreg0_8_0c(gate_dflt)-mips_core.iRF_stage.MIAN_FSM.CurrState_Sreg0[8:0]
original code -> new code
0000 -> 000000000
0001 -> 000000011
0010 -> 000000101
0011 -> 000001001
0100 -> 000010001
0101 -> 000100001
0110 -> 001000001
0111 -> 010000001
1000 -> 100000001
<font color=#A52A2A>@W:<a href="@W:FA140:@XP_HELP">FA140</a> : <a href="e:\mips789\mips789\rtl\verilog\ctl_fsm.v:126:16:126:17:@W:FA140:@XP_MSG">ctl_fsm.v(126)</a><!@TM:1223605618> | DFF ScratchLib.mips_core.iRF_stage.MIAN_FSM.CurrState_Sreg0_8_0c(gate_dflt)-mips_core.iRF_stage.MIAN_FSM.CurrState_Sreg0[5] is stuck at '0', removing ... </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\ctl_fsm.v:126:16:126:17:@W:BN116:@XP_MSG">ctl_fsm.v(126)</a><!@TM:1223605618> | Removing sequential instance mips_core.iRF_stage.MIAN_FSM.CurrState_Sreg0[5] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
Warning: Found 27 combinational loops!
Each loop is reported with an instance in the loop
and nets connected to that instance.
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
1) instance mips_core.decoder_pipe.idecoder.ext_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.ext_ctl_1[0], output net "mips_core.decoder_pipe.BUS2072[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.N_1345" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
2) instance mips_core.decoder_pipe.idecoder.ext_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.ext_ctl_1[1], output net "mips_core.decoder_pipe.BUS2072[1]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.N_1346" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
3) instance mips_core.decoder_pipe.idecoder.ext_ctl_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.ext_ctl_1[2], output net "mips_core.decoder_pipe.BUS2072[2]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.ext_ctl_2[2]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
4) instance mips_core.decoder_pipe.idecoder.rd_sel_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.rd_sel_1[0], output net "mips_core.decoder_pipe.BUS2110[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.rd_sel_2[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
5) instance mips_core.decoder_pipe.idecoder.rd_sel_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.rd_sel_1[1], output net "mips_core.decoder_pipe.BUS2110[1]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.rd_sel_2[1]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_438" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.fsm_dly373" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6) instance mips_core.decoder_pipe.idecoder.cmp_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.cmp_ctl_1[0], output net "mips_core.decoder_pipe.BUS2056[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.cmp_ctl_2[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7) instance mips_core.decoder_pipe.idecoder.cmp_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.cmp_ctl_1[1], output net "mips_core.decoder_pipe.BUS2056[1]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.cmp_ctl_2[1]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
8) instance mips_core.decoder_pipe.idecoder.cmp_ctl_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.cmp_ctl_1[2], output net "mips_core.decoder_pipe.BUS2056[2]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.cmp_ctl_2[2]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
9) instance mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[0], output net "mips_core.decoder_pipe.BUS2102[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.N_1348" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
10) instance mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[1], output net "mips_core.decoder_pipe.BUS2102[1]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.pc_gen_ctl_2[1]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
11) instance mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[2], output net "mips_core.decoder_pipe.BUS2102[2]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.N_1232_i" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
12) instance mips_core.decoder_pipe.idecoder.muxa_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxa_ctl_1[0], output net "mips_core.decoder_pipe.BUS2086[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.muxa_ctl_2[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
13) instance mips_core.decoder_pipe.idecoder.muxa_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxa_ctl_1[1], output net "mips_core.decoder_pipe.BUS2086[1]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.muxa_ctl_2[1]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
14) instance mips_core.decoder_pipe.idecoder.muxb_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxb_ctl_1[0], output net "mips_core.decoder_pipe.BUS2094[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.muxb_ctl_2[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
15) instance mips_core.decoder_pipe.idecoder.muxb_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxb_ctl_1[1], output net "mips_core.decoder_pipe.BUS2094[1]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.muxb_ctl_2[1]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
16) instance mips_core.decoder_pipe.idecoder.alu_func_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[0], output net "mips_core.decoder_pipe.BUS2040[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.alu_func_2[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
17) instance mips_core.decoder_pipe.idecoder.alu_func_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[1], output net "mips_core.decoder_pipe.BUS2040[1]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.alu_func_2[1]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
18) instance mips_core.decoder_pipe.idecoder.alu_func_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[2], output net "mips_core.decoder_pipe.BUS2040[2]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.N_1344" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
19) instance mips_core.decoder_pipe.idecoder.alu_func_1[3] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[3], output net "mips_core.decoder_pipe.BUS2040[3]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.alu_func_2[3]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
20) instance mips_core.decoder_pipe.idecoder.alu_func_1[4] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[4], output net "mips_core.decoder_pipe.BUS2040[4]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.alu_func_2[4]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
21) instance mips_core.decoder_pipe.idecoder.dmem_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[0], output net "mips_core.decoder_pipe.BUS2064[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
22) instance mips_core.decoder_pipe.idecoder.dmem_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[1], output net "mips_core.decoder_pipe.BUS2064[1]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[1]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_438" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.fsm_dly373" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
23) instance mips_core.decoder_pipe.idecoder.dmem_ctl_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[2], output net "mips_core.decoder_pipe.BUS2064[2]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[2]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_18_m" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_15" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
24) instance mips_core.decoder_pipe.idecoder.dmem_ctl_1[3] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[3], output net "mips_core.decoder_pipe.BUS2064[3]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[3]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
25) instance mips_core.decoder_pipe.idecoder.alu_we[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_we[0], output net "mips_core.decoder_pipe.BUS2048[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.alu_we_1[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
26) instance mips_core.decoder_pipe.idecoder.wb_mux[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.wb_mux[0], output net "mips_core.decoder_pipe.BUS2118[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.wb_mux_1[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
27) instance mips_core.decoder_pipe.idecoder.wb_we[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.wb_we[0], output net "mips_core.decoder_pipe.BUS2126[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.wb_we_1[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
End of loops
Warning: Found 28 combinational loops!
Each loop is reported with an instance in the loop
and nets connected to that instance.
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net mips_core.BUS197[0]</font>
1) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.fsm_dly_1[0], output net "mips_core.BUS197[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.fsm_dly_2[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2072[0]</font>
2) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.ext_ctl_1[0], output net "mips_core.decoder_pipe.BUS2072[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.N_1345" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2072[1]</font>
3) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.ext_ctl_1[1], output net "mips_core.decoder_pipe.BUS2072[1]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.N_1346" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2072[2]</font>
4) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.ext_ctl_1[2], output net "mips_core.decoder_pipe.BUS2072[2]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.ext_ctl_2[2]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2110[0]</font>
5) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.rd_sel_1[0], output net "mips_core.decoder_pipe.BUS2110[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.rd_sel_2[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2110[1]</font>
6) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.rd_sel_1[1], output net "mips_core.decoder_pipe.BUS2110[1]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.rd_sel_2[1]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_438" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.fsm_dly373" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2056[0]</font>
7) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.cmp_ctl_1[0], output net "mips_core.decoder_pipe.BUS2056[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.cmp_ctl_2[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2056[1]</font>
8) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.cmp_ctl_1[1], output net "mips_core.decoder_pipe.BUS2056[1]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.cmp_ctl_2[1]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2056[2]</font>
9) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.cmp_ctl_1[2], output net "mips_core.decoder_pipe.BUS2056[2]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.cmp_ctl_2[2]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2102[0]</font>
10) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[0], output net "mips_core.decoder_pipe.BUS2102[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.N_1348" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2102[1]</font>
11) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[1], output net "mips_core.decoder_pipe.BUS2102[1]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.pc_gen_ctl_2[1]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2102[2]</font>
12) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[2], output net "mips_core.decoder_pipe.BUS2102[2]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.N_1232_i_0" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2086[0]</font>
13) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxa_ctl_1[0], output net "mips_core.decoder_pipe.BUS2086[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.muxa_ctl_2[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2086[1]</font>
14) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxa_ctl_1[1], output net "mips_core.decoder_pipe.BUS2086[1]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.muxa_ctl_2[1]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2094[0]</font>
15) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxb_ctl_1[0], output net "mips_core.decoder_pipe.BUS2094[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.muxb_ctl_2[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2094[1]</font>
16) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxb_ctl_1[1], output net "mips_core.decoder_pipe.BUS2094[1]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.muxb_ctl_2[1]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2040[0]</font>
17) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[0], output net "mips_core.decoder_pipe.BUS2040[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.alu_func_2[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2040[1]</font>
18) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[1], output net "mips_core.decoder_pipe.BUS2040[1]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.alu_func_2[1]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2040[2]</font>
19) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[2], output net "mips_core.decoder_pipe.BUS2040[2]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.N_1344" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2040[3]</font>
20) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[3], output net "mips_core.decoder_pipe.BUS2040[3]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.alu_func_2[3]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2040[4]</font>
21) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[4], output net "mips_core.decoder_pipe.BUS2040[4]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.alu_func_2[4]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2064[0]</font>
22) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[0], output net "mips_core.decoder_pipe.BUS2064[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2064[1]</font>
23) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[1], output net "mips_core.decoder_pipe.BUS2064[1]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[1]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_438" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.fsm_dly373" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2064[2]</font>
24) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[2], output net "mips_core.decoder_pipe.BUS2064[2]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[2]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_18_m" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_ins_i_15" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2064[3]</font>
25) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[3], output net "mips_core.decoder_pipe.BUS2064[3]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[3]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2048[0]</font>
26) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_we[0], output net "mips_core.decoder_pipe.BUS2048[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.alu_we_1[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2118[0]</font>
27) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.wb_mux[0], output net "mips_core.decoder_pipe.BUS2118[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.wb_mux_1[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2126[0]</font>
28) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.wb_we[0], output net "mips_core.decoder_pipe.BUS2126[0]" in work.mips_sys(verilog)
input nets to instance:
net "mips_core.decoder_pipe.idecoder.wb_we_1[0]" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
End of loops
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