Subversion Repositories mips789

#
# Synplicity Verification Interface File
# Generated using Synplify-pro
#
# Copyright (c) 1996-2005 Synplicity, Inc.
# All rights reserved
#

# Set logfile options
vif_set_result_file  mips_sys.vlf

# Set technology for TCL script
vif_set_technology -architecture FPGA -vendor Altera

# RTL and technology files
vif_add_library -original $env(QUARTUS_ROOTDIR)/eda/fv_lib/verilog
vif_add_file -original -verilog ../../rtl/verilog/EXEC_stage.v
vif_add_file -original -verilog ../../rtl/verilog/RF_components.v
vif_add_file -original -verilog ../../rtl/verilog/RF_stage.v
vif_add_file -original -verilog ../../rtl/verilog/ctl_fsm.v
vif_add_file -original -verilog ../../rtl/verilog/decode_pipe.v
vif_add_file -original -verilog ../../rtl/verilog/dvc.v
vif_add_file -original -verilog ../../rtl/verilog/fifo.v
vif_add_file -original -verilog ../../rtl/verilog/forward.v
vif_add_file -original -verilog ../../rtl/verilog/mem_module.v
vif_add_file -original -verilog ../../rtl/verilog/mips_core.v
vif_add_file -original -verilog ../../rtl/verilog/mips_dvc.v
vif_add_file -original -verilog ../../rtl/verilog/mips_sys.v
vif_add_file -original -verilog ../../rtl/verilog/mips_uart.v
vif_add_file -original -verilog ../../rtl/verilog/ram_module.v
vif_add_file -original -verilog ../../rtl/verilog/sim_ram.v
vif_add_file -original -verilog ../../rtl/verilog/ulit.v
vif_add_file -original -verilog ../../rtl/verilog/altera/fifo512_cyclone.v
vif_set_top_module -original -top mips_sys
 
vif_add_library -translated $env(QUARTUS_ROOTDIR)/eda/fv_lib/verilog
vif_add_file -translated -verilog mips_sys.vqm
vif_set_top_module -translated -top mips_sys 
# Read FSM encoding
vif_set_fsm -fsm fsm_0
vif_set_fsmreg -original -fsm fsm_0 mips_core/iRF_stage/MIAN_FSM/CurrState_Sreg0[3:0]
vif_set_fsmreg -translated -fsm  fsm_0 mips_core/iRF_stage/MIAN_FSM/CurrState_Sreg0[8:0]
vif_set_state_map -fsm fsm_0 -original "0000" -translated "000000001"
vif_set_state_map -fsm fsm_0 -original "0001" -translated "000000010"
vif_set_state_map -fsm fsm_0 -original "0010" -translated "000000100"
vif_set_state_map -fsm fsm_0 -original "0011" -translated "000001000"
vif_set_state_map -fsm fsm_0 -original "0100" -translated "000010000"
vif_set_state_map -fsm fsm_0 -original "0101" -translated "000100000"
vif_set_state_map -fsm fsm_0 -original "0110" -translated "001000000"
vif_set_state_map -fsm fsm_0 -original "0111" -translated "010000000"
vif_set_state_map -fsm fsm_0 -original "1000" -translated "100000000"
vif_set_fsm -fsm fsm_9
vif_set_fsmreg -original -fsm fsm_9 imips_dvc/iuart0/uart_rd_tak/ua_state[2:0]
vif_set_fsmreg -translated -fsm  fsm_9 imips_dvc/iuart0/uart_rd_tak/ua_state[4:0]
vif_set_state_map -fsm fsm_9 -original "000" -translated "00001"
vif_set_state_map -fsm fsm_9 -original "001" -translated "00010"
vif_set_state_map -fsm fsm_9 -original "010" -translated "00100"
vif_set_state_map -fsm fsm_9 -original "011" -translated "01000"
vif_set_state_map -fsm fsm_9 -original "100" -translated "10000"
vif_set_fsm -fsm fsm_15
vif_set_fsmreg -original -fsm fsm_15 imips_dvc/iuart0/uart_txd/ua_state[2:0]
vif_set_fsmreg -translated -fsm  fsm_15 imips_dvc/iuart0/uart_txd/ua_state[7:0]
vif_set_state_map -fsm fsm_15 -original "000" -translated "00000001"
vif_set_state_map -fsm fsm_15 -original "001" -translated "00000010"
vif_set_state_map -fsm fsm_15 -original "010" -translated "00000100"
vif_set_state_map -fsm fsm_15 -original "011" -translated "00001000"
vif_set_state_map -fsm fsm_15 -original "100" -translated "00010000"
vif_set_state_map -fsm fsm_15 -original "101" -translated "00100000"
vif_set_state_map -fsm fsm_15 -original "110" -translated "01000000"
vif_set_state_map -fsm fsm_15 -original "111" -translated "10000000"

# Memory map points

# SRL map points

# Compiler constant registers

# Compiler constant latches

# Compiler RTL sequential redundancies

# RTL sequential redundancies
vif_set_merge -original  mips_core/MEM_CTL/dmem_ctl_post/byte_addr_o[0] mips_core/alu_pass0/r32_o[0]
vif_set_merge -original  mips_core/MEM_CTL/dmem_ctl_post/byte_addr_o[1] mips_core/alu_pass0/r32_o[1]
vif_set_merge -original  mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_sign_reged mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged[32]

# Technology sequential redundancies

# Inversion map points
vif_set_map_point -register -inverted -original mips_core/iRF_stage/MIAN_FSM/CurrState_Sreg0[0] -translated mips_core/iRF_stage/MIAN_FSM/CurrState_Sreg0_i_0__Z
vif_set_map_point -register -inverted -original imips_dvc/iuart0/uart_rd_tak/ua_state[0] -translated imips_dvc/iuart0/uart_rd_tak/ua_state_i_0__Z
vif_set_map_point -register -inverted -original imips_dvc/iuart0/uart_txd/ua_state[0] -translated imips_dvc/iuart0/uart_txd/ua_state_i_0__Z

# Port mappping and directions

# Black box mapping
vif_set_black_box synplicity_altsyncram4_r_w
vif_set_black_box scfifo

vif_set_map_point -blackbox -original mips_core/iRF_stage/reg_bank/reg_bank/altsyncram -translated mips_core/iRF_stage/reg_bank/reg_bank.I_1
vif_set_map_point -blackbox -original mips_core/iRF_stage/reg_bank/reg_bank_1/altsyncram -translated mips_core/iRF_stage/reg_bank/reg_bank_1.I_1
vif_set_map_point -blackbox -original imips_dvc/iuart0/uart_txd/fifo/scfifo_component -translated imips_dvc/iuart0/uart_txd/fifo/scfifo_component

# Other sequential cells, including multidimensional arrays
vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[7] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_7__Z
vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[6] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_6__Z
vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[5] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_5__Z
vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[4] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_4__Z
vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[3] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_3__Z
vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[2] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_2__Z
vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[1] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_1__Z
vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[0] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_0__Z
vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[15] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_15__Z
vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[14] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_14__Z
vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[13] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_13__Z
vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[12] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_12__Z
vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[11] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_11__Z
vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[10] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_10__Z
vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[9] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_9__Z
vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[8] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_8__Z
vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[31] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_31__Z
vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[30] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_30__Z
vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[29] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_29__Z
vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[28] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_28__Z
vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[27] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_27__Z
vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[26] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_26__Z
vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[25] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_25__Z
vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[24] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_24__Z
vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[23] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_23__Z
vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[22] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_22__Z
vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[21] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_21__Z
vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[20] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_20__Z
vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[19] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_19__Z
vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[18] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_18__Z
vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[17] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_17__Z
vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[16] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_16__Z
vif_set_map_point -latch -original mips_core/decoder_pipe/idecoder/fsm_dly[2] -translated mips_core/decoder_pipe/idecoder/fsm_dly_1_2__Z
vif_set_map_point -latch -original mips_core/decoder_pipe/idecoder/fsm_dly[1] -translated mips_core/decoder_pipe/idecoder/fsm_dly_1_1__Z

# Constant Registers
vif_set_constant -original -1 mips_core/iRF_stage/MIAN_FSM/CurrState_Sreg0[5]
vif_set_transparent -original 1 mips_core/iRF_stage/MIAN_FSM/iack
vif_set_constant -original -1 mips_core/iRF_stage/ins_reg/r32_o[31]
vif_set_constant -original -1 mips_core/iRF_stage/ins_reg/r32_o[30]
vif_set_constant -original -1 mips_core/iRF_stage/ins_reg/r32_o[29]
vif_set_constant -original -1 mips_core/iRF_stage/ins_reg/r32_o[28]
vif_set_constant -original -1 mips_core/iRF_stage/ins_reg/r32_o[27]
vif_set_constant -original -1 mips_core/iRF_stage/ins_reg/r32_o[26]
vif_set_constant -original -1 imips_dvc/key2_addr[31]
vif_set_constant -original -1 imips_dvc/key2_addr[30]
vif_set_constant -original -1 imips_dvc/key2_addr[29]
vif_set_constant -original -1 imips_dvc/key2_addr[28]
vif_set_constant -original -1 imips_dvc/key2_addr[27]
vif_set_constant -original -1 imips_dvc/key2_addr[26]
vif_set_constant -original -1 imips_dvc/key2_addr[25]
vif_set_constant -original -1 imips_dvc/key2_addr[24]
vif_set_constant -original -1 imips_dvc/key2_addr[23]
vif_set_constant -original -1 imips_dvc/key2_addr[22]
vif_set_constant -original -1 imips_dvc/key2_addr[21]
vif_set_constant -original -1 imips_dvc/key2_addr[20]
vif_set_constant -original -1 imips_dvc/key2_addr[19]
vif_set_constant -original -1 imips_dvc/key2_addr[18]
vif_set_constant -original -1 imips_dvc/key2_addr[17]
vif_set_constant -original -1 imips_dvc/key2_addr[16]
vif_set_constant -original -1 imips_dvc/key2_addr[15]
vif_set_constant -original -1 imips_dvc/key2_addr[14]
vif_set_constant -original -1 imips_dvc/key2_addr[13]
vif_set_constant -original -1 imips_dvc/key2_addr[12]
vif_set_constant -original -1 imips_dvc/key2_addr[11]
vif_set_constant -original -1 imips_dvc/key2_addr[10]
vif_set_constant -original -1 imips_dvc/key2_addr[9]
vif_set_constant -original -1 imips_dvc/key2_addr[8]
vif_set_constant -original -1 imips_dvc/key2_addr[7]
vif_set_constant -original -1 imips_dvc/key2_addr[6]
vif_set_constant -original -1 imips_dvc/key2_addr[5]
vif_set_constant -original -1 imips_dvc/key2_addr[4]
vif_set_constant -original -1 imips_dvc/key2_addr[3]
vif_set_constant -original -1 imips_dvc/key2_addr[2]
vif_set_constant -original -1 imips_dvc/key2_addr[1]
vif_set_constant -original -1 imips_dvc/key2_addr[0]
vif_set_constant -original -1 imips_dvc/key1_addr[31]
vif_set_constant -original -1 imips_dvc/key1_addr[30]
vif_set_constant -original -1 imips_dvc/key1_addr[29]
vif_set_constant -original -1 imips_dvc/key1_addr[28]
vif_set_constant -original -1 imips_dvc/key1_addr[27]
vif_set_constant -original -1 imips_dvc/key1_addr[26]
vif_set_constant -original -1 imips_dvc/key1_addr[25]
vif_set_constant -original -1 imips_dvc/key1_addr[24]
vif_set_constant -original -1 imips_dvc/key1_addr[23]
vif_set_constant -original -1 imips_dvc/key1_addr[22]
vif_set_constant -original -1 imips_dvc/key1_addr[21]
vif_set_constant -original -1 imips_dvc/key1_addr[20]
vif_set_constant -original -1 imips_dvc/key1_addr[19]
vif_set_constant -original -1 imips_dvc/key1_addr[18]
vif_set_constant -original -1 imips_dvc/key1_addr[17]
vif_set_constant -original -1 imips_dvc/key1_addr[16]
vif_set_constant -original -1 imips_dvc/key1_addr[15]
vif_set_constant -original -1 imips_dvc/key1_addr[14]
vif_set_constant -original -1 imips_dvc/key1_addr[13]
vif_set_constant -original -1 imips_dvc/key1_addr[12]
vif_set_constant -original -1 imips_dvc/key1_addr[11]
vif_set_constant -original -1 imips_dvc/key1_addr[10]
vif_set_constant -original -1 imips_dvc/key1_addr[9]
vif_set_constant -original -1 imips_dvc/key1_addr[8]
vif_set_constant -original -1 imips_dvc/key1_addr[7]
vif_set_constant -original -1 imips_dvc/key1_addr[6]
vif_set_constant -original -1 imips_dvc/key1_addr[5]
vif_set_constant -original -1 imips_dvc/key1_addr[4]
vif_set_constant -original -1 imips_dvc/key1_addr[3]
vif_set_constant -original -1 imips_dvc/key1_addr[2]
vif_set_constant -original -1 imips_dvc/key1_addr[1]
vif_set_constant -original -1 imips_dvc/key1_addr[0]
vif_set_constant -original -1 imips_dvc/tmr_addr[31]
vif_set_constant -original -1 imips_dvc/tmr_addr[30]
vif_set_constant -original -1 imips_dvc/tmr_addr[29]
vif_set_constant -original -1 imips_dvc/tmr_addr[28]
vif_set_constant -original -1 imips_dvc/tmr_addr[27]
vif_set_constant -original -1 imips_dvc/tmr_addr[26]
vif_set_constant -original -1 imips_dvc/tmr_addr[25]
vif_set_constant -original -1 imips_dvc/tmr_addr[24]
vif_set_constant -original -1 imips_dvc/tmr_addr[23]
vif_set_constant -original -1 imips_dvc/tmr_addr[22]
vif_set_constant -original -1 imips_dvc/tmr_addr[21]
vif_set_constant -original -1 imips_dvc/tmr_addr[20]
vif_set_constant -original -1 imips_dvc/tmr_addr[19]
vif_set_constant -original -1 imips_dvc/tmr_addr[18]
vif_set_constant -original -1 imips_dvc/tmr_addr[17]
vif_set_constant -original -1 imips_dvc/tmr_addr[16]
vif_set_constant -original -1 imips_dvc/tmr_addr[15]
vif_set_constant -original -1 imips_dvc/tmr_addr[14]
vif_set_constant -original -1 imips_dvc/tmr_addr[13]
vif_set_constant -original -1 imips_dvc/tmr_addr[12]
vif_set_constant -original -1 imips_dvc/tmr_addr[11]
vif_set_constant -original -1 imips_dvc/tmr_addr[10]
vif_set_constant -original -1 imips_dvc/tmr_addr[9]
vif_set_constant -original -1 imips_dvc/tmr_addr[8]
vif_set_constant -original -1 imips_dvc/tmr_addr[7]
vif_set_constant -original -1 imips_dvc/tmr_addr[6]
vif_set_constant -original -1 imips_dvc/tmr_addr[5]
vif_set_constant -original -1 imips_dvc/tmr_addr[4]
vif_set_constant -original -1 imips_dvc/tmr_addr[3]
vif_set_constant -original -1 imips_dvc/tmr_addr[2]
vif_set_constant -original -1 imips_dvc/tmr_addr[1]
vif_set_constant -original -1 imips_dvc/tmr_addr[0]

# Retimed Registers
vif_set_sequential_verify -retimed -register -original mips_core/MEM_CTL/dmem_ctl_post/ctl_o[0] -translated mips_core/MEM_CTL/dmem_ctl_post/ctl_o_0__Z
vif_set_sequential_verify -retimed -register -original mips_core/MEM_CTL/dmem_ctl_post/ctl_o[1] -translated mips_core/MEM_CTL/dmem_ctl_post/ctl_o_1__Z
vif_set_sequential_verify -retimed -register -original mips_core/MEM_CTL/dmem_ctl_post/ctl_o[2] -translated mips_core/MEM_CTL/dmem_ctl_post/ctl_o_2__Z
vif_set_sequential_verify -retimed -register -original mips_core/MEM_CTL/dmem_ctl_post/ctl_o[3] -translated mips_core/MEM_CTL/dmem_ctl_post/ctl_o_3__Z
vif_set_sequential_verify -retimed -register -original mips_core/MEM_CTL/dmem_ctl_post/byte_addr_o[0] -translated mips_core/MEM_CTL/dmem_ctl_post/byte_addr_o_0__Z
vif_set_sequential_verify -retimed -register -original mips_core/MEM_CTL/dmem_ctl_post/byte_addr_o[1] -translated mips_core/MEM_CTL/dmem_ctl_post/byte_addr_o_1__Z
vif_set_sequential_verify -retimed -register -original mips_core/iRF_stage/MIAN_FSM/delay_counter_Sreg0[3] -translated mips_core/iRF_stage/MIAN_FSM/delay_counter_Sreg0_3__Z
vif_set_sequential_verify -retimed -register -original mips_core/iRF_stage/MIAN_FSM/delay_counter_Sreg0[5] -translated mips_core/iRF_stage/MIAN_FSM/delay_counter_Sreg0_5__Z
# Retimed registers from FSM not handled in VIF
//vif_set_sequential_verify -retimed -register -original mips_core/iRF_stage/MIAN_FSM/CurrState_Sreg0[0] -translated mips_core/iRF_stage/MIAN_FSM/CurrState_Sreg0_i_0__Z
# Retimed registers from FSM not handled in VIF
//vif_set_sequential_verify -retimed -register -original mips_core/iRF_stage/MIAN_FSM/CurrState_Sreg0[6] -translated mips_core/iRF_stage/MIAN_FSM/CurrState_Sreg0_6__Z
vif_set_sequential_verify -retimed -register -original mips_core/iRF_stage/reg_bank/r_wren -translated mips_core/iRF_stage/reg_bank/r_wren_Z
vif_set_sequential_verify -retimed -register -original mips_core/iRF_stage/reg_bank/r_rdaddress_a[0] -translated mips_core/iRF_stage/reg_bank/r_rdaddress_a_0__Z
vif_set_sequential_verify -retimed -register -original mips_core/iRF_stage/reg_bank/r_rdaddress_a[1] -translated mips_core/iRF_stage/reg_bank/r_rdaddress_a_1__Z
vif_set_sequential_verify -retimed -register -original mips_core/iRF_stage/reg_bank/r_rdaddress_a[2] -translated mips_core/iRF_stage/reg_bank/r_rdaddress_a_2__Z
vif_set_sequential_verify -retimed -register -original mips_core/iRF_stage/reg_bank/r_rdaddress_a[3] -translated mips_core/iRF_stage/reg_bank/r_rdaddress_a_3__Z
vif_set_sequential_verify -retimed -register -original mips_core/iRF_stage/reg_bank/r_rdaddress_a[4] -translated mips_core/iRF_stage/reg_bank/r_rdaddress_a_4__Z
vif_set_sequential_verify -retimed -register -original mips_core/iRF_stage/reg_bank/r_rdaddress_b[0] -translated mips_core/iRF_stage/reg_bank/r_rdaddress_b_0__Z
vif_set_sequential_verify -retimed -register -original mips_core/iRF_stage/reg_bank/r_rdaddress_b[1] -translated mips_core/iRF_stage/reg_bank/r_rdaddress_b_1__Z
vif_set_sequential_verify -retimed -register -original mips_core/iRF_stage/reg_bank/r_rdaddress_b[2] -translated mips_core/iRF_stage/reg_bank/r_rdaddress_b_2__Z
vif_set_sequential_verify -retimed -register -original mips_core/iRF_stage/reg_bank/r_rdaddress_b[3] -translated mips_core/iRF_stage/reg_bank/r_rdaddress_b_3__Z
vif_set_sequential_verify -retimed -register -original mips_core/iRF_stage/reg_bank/r_rdaddress_b[4] -translated mips_core/iRF_stage/reg_bank/r_rdaddress_b_4__Z
vif_set_sequential_verify -retimed -register -original mips_core/iRF_stage/reg_bank/r_data[0] -translated mips_core/iRF_stage/reg_bank/r_data_0__Z
vif_set_sequential_verify -retimed -register -original mips_core/iRF_stage/reg_bank/r_data[1] -translated mips_core/iRF_stage/reg_bank/r_data_1__Z
vif_set_sequential_verify -retimed -register -original mips_core/iRF_stage/reg_bank/r_data[2] -translated mips_core/iRF_stage/reg_bank/r_data_2__Z
vif_set_sequential_verify -retimed -register -original mips_core/iRF_stage/reg_bank/r_data[3] -translated mips_core/iRF_stage/reg_bank/r_data_3__Z
vif_set_sequential_verify -retimed -register -original mips_core/iRF_stage/reg_bank/r_data[4] -translated mips_core/iRF_stage/reg_bank/r_data_4__Z
vif_set_sequential_verify -retimed -register -original mips_core/iRF_stage/reg_bank/r_data[5] -translated mips_core/iRF_stage/reg_bank/r_data_5__Z
vif_set_sequential_verify -retimed -register -original mips_core/iRF_stage/reg_bank/r_data[6] -translated mips_core/iRF_stage/reg_bank/r_data_6__Z
vif_set_sequential_verify -retimed -register -original mips_core/iRF_stage/reg_bank/r_data[7] -translated mips_core/iRF_stage/reg_bank/r_data_7__Z
vif_set_sequential_verify -retimed -register -original mips_core/iRF_stage/reg_bank/r_data[8] -translated mips_core/iRF_stage/reg_bank/r_data_8__Z
vif_set_sequential_verify -retimed -register -original mips_core/iRF_stage/reg_bank/r_data[9] -translated mips_core/iRF_stage/reg_bank/r_data_9__Z
vif_set_sequential_verify -retimed -register -original mips_core/iRF_stage/reg_bank/r_data[10] -translated mips_core/iRF_stage/reg_bank/r_data_10__Z
vif_set_sequential_verify -retimed -register -original mips_core/iRF_stage/reg_bank/r_data[11] -translated mips_core/iRF_stage/reg_bank/r_data_11__Z
vif_set_sequential_verify -retimed -register -original mips_core/iRF_stage/reg_bank/r_data[12] -translated mips_core/iRF_stage/reg_bank/r_data_12__Z
vif_set_sequential_verify -retimed -register -original mips_core/iRF_stage/reg_bank/r_data[13] -translated mips_core/iRF_stage/reg_bank/r_data_13__Z
vif_set_sequential_verify -retimed -register -original mips_core/iRF_stage/reg_bank/r_data[14] -translated mips_core/iRF_stage/reg_bank/r_data_14__Z
vif_set_sequential_verify -retimed -register -original mips_core/iRF_stage/reg_bank/r_data[15] -translated mips_core/iRF_stage/reg_bank/r_data_15__Z
vif_set_sequential_verify -retimed -register -original mips_core/iRF_stage/reg_bank/r_data[16] -translated mips_core/iRF_stage/reg_bank/r_data_16__Z
vif_set_sequential_verify -retimed -register -original mips_core/iRF_stage/reg_bank/r_data[17] -translated mips_core/iRF_stage/reg_bank/r_data_17__Z
vif_set_sequential_verify -retimed -register -original mips_core/iRF_stage/reg_bank/r_data[18] -translated mips_core/iRF_stage/reg_bank/r_data_18__Z
vif_set_sequential_verify -retimed -register -original mips_core/iRF_stage/reg_bank/r_data[19] -translated mips_core/iRF_stage/reg_bank/r_data_19__Z
vif_set_sequential_verify -retimed -register -original mips_core/iRF_stage/reg_bank/r_data[20] -translated mips_core/iRF_stage/reg_bank/r_data_20__Z
vif_set_sequential_verify -retimed -register -original mips_core/iRF_stage/reg_bank/r_data[21] -translated mips_core/iRF_stage/reg_bank/r_data_21__Z
vif_set_sequential_verify -retimed -register -original mips_core/iRF_stage/reg_bank/r_data[22] -translated mips_core/iRF_stage/reg_bank/r_data_22__Z
vif_set_sequential_verify -retimed -register -original mips_core/iRF_stage/reg_bank/r_data[23] -translated mips_core/iRF_stage/reg_bank/r_data_23__Z
vif_set_sequential_verify -retimed -register -original mips_core/iRF_stage/reg_bank/r_data[24] -translated mips_core/iRF_stage/reg_bank/r_data_24__Z
vif_set_sequential_verify -retimed -register -original mips_core/iRF_stage/reg_bank/r_data[25] -translated mips_core/iRF_stage/reg_bank/r_data_25__Z
vif_set_sequential_verify -retimed -register -original mips_core/iRF_stage/reg_bank/r_data[26] -translated mips_core/iRF_stage/reg_bank/r_data_26__Z
vif_set_sequential_verify -retimed -register -original mips_core/iRF_stage/reg_bank/r_data[27] -translated mips_core/iRF_stage/reg_bank/r_data_27__Z
vif_set_sequential_verify -retimed -register -original mips_core/iRF_stage/reg_bank/r_data[28] -translated mips_core/iRF_stage/reg_bank/r_data_28__Z
vif_set_sequential_verify -retimed -register -original mips_core/iRF_stage/reg_bank/r_data[29] -translated mips_core/iRF_stage/reg_bank/r_data_29__Z
vif_set_sequential_verify -retimed -register -original mips_core/iRF_stage/reg_bank/r_data[30] -translated mips_core/iRF_stage/reg_bank/r_data_30__Z
vif_set_sequential_verify -retimed -register -original mips_core/iRF_stage/reg_bank/r_data[31] -translated mips_core/iRF_stage/reg_bank/r_data_31__Z
vif_set_sequential_verify -retimed -register -original mips_core/iRF_stage/reg_bank/r_wraddress[0] -translated mips_core/iRF_stage/reg_bank/r_wraddress_0__Z
vif_set_sequential_verify -retimed -register -original mips_core/iRF_stage/reg_bank/r_wraddress[1] -translated mips_core/iRF_stage/reg_bank/r_wraddress_1__Z
vif_set_sequential_verify -retimed -register -original mips_core/iRF_stage/reg_bank/r_wraddress[2] -translated mips_core/iRF_stage/reg_bank/r_wraddress_2__Z
vif_set_sequential_verify -retimed -register -original mips_core/iRF_stage/reg_bank/r_wraddress[3] -translated mips_core/iRF_stage/reg_bank/r_wraddress_3__Z
vif_set_sequential_verify -retimed -register -original mips_core/iRF_stage/reg_bank/r_wraddress[4] -translated mips_core/iRF_stage/reg_bank/r_wraddress_4__Z
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/MIPS_alu/muldiv_ff/add1 -translated mips_core/iexec_stage/MIPS_alu/muldiv_ff/add1_Z
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/MIPS_alu/muldiv_ff/addop2 -translated mips_core/iexec_stage/MIPS_alu/muldiv_ff/addop2_Z
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/MIPS_alu/muldiv_ff/addnop2 -translated mips_core/iexec_stage/MIPS_alu/muldiv_ff/addnop2_Z
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/MIPS_alu/muldiv_ff/overflow -translated mips_core/iexec_stage/MIPS_alu/muldiv_ff/overflow_Z
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/MIPS_alu/muldiv_ff/sub_or_yn -translated mips_core/iexec_stage/MIPS_alu/muldiv_ff/sub_or_yn_Z
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_sign_reged -translated mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_sign_reged_Z
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/MIPS_alu/muldiv_ff/op1_sign_reged -translated mips_core/iexec_stage/MIPS_alu/muldiv_ff/op1_sign_reged_Z
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/MIPS_alu/muldiv_ff/start -translated mips_core/iexec_stage/MIPS_alu/muldiv_ff/start_Z
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/MIPS_alu/muldiv_ff/sign -translated mips_core/iexec_stage/MIPS_alu/muldiv_ff/sign_Z
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/MIPS_alu/muldiv_ff/mul -translated mips_core/iexec_stage/MIPS_alu/muldiv_ff/mul_Z
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/MIPS_alu/muldiv_ff/rdy -translated mips_core/iexec_stage/MIPS_alu/muldiv_ff/rdy_Z
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged[0] -translated mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged_0__Z
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged[1] -translated mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged_1__Z
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged[2] -translated mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged_2__Z
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged[3] -translated mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged_3__Z
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged[4] -translated mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged_4__Z
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged[5] -translated mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged_5__Z
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged[6] -translated mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged_6__Z
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged[7] -translated mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged_7__Z
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged[8] -translated mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged_8__Z
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged[9] -translated mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged_9__Z
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged[10] -translated mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged_10__Z
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged[11] -translated mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged_11__Z
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged[12] -translated mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged_12__Z
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged[13] -translated mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged_13__Z
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged[14] -translated mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged_14__Z
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged[15] -translated mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged_15__Z
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged[16] -translated mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged_16__Z
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged[17] -translated mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged_17__Z
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged[18] -translated mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged_18__Z
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged[19] -translated mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged_19__Z
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged[20] -translated mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged_20__Z
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged[21] -translated mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged_21__Z
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged[22] -translated mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged_22__Z
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged[23] -translated mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged_23__Z
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged[24] -translated mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged_24__Z
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged[25] -translated mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged_25__Z
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged[26] -translated mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged_26__Z
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged[27] -translated mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged_27__Z
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged[28] -translated mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged_28__Z
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged[29] -translated mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged_29__Z
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged[30] -translated mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged_30__Z
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged[31] -translated mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged_31__Z
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/pc_nxt/r32_o[2] -translated mips_core/iexec_stage/pc_nxt/r32_o_2__Z
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/pc_nxt/r32_o[3] -translated mips_core/iexec_stage/pc_nxt/r32_o_3__Z
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/pc_nxt/r32_o[4] -translated mips_core/iexec_stage/pc_nxt/r32_o_4__Z
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/pc_nxt/r32_o[5] -translated mips_core/iexec_stage/pc_nxt/r32_o_5__Z
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/pc_nxt/r32_o[6] -translated mips_core/iexec_stage/pc_nxt/r32_o_6__Z
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/pc_nxt/r32_o[7] -translated mips_core/iexec_stage/pc_nxt/r32_o_7__Z
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/pc_nxt/r32_o[8] -translated mips_core/iexec_stage/pc_nxt/r32_o_8__Z
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/pc_nxt/r32_o[9] -translated mips_core/iexec_stage/pc_nxt/r32_o_9__Z
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/pc_nxt/r32_o[10] -translated mips_core/iexec_stage/pc_nxt/r32_o_10__Z
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/pc_nxt/r32_o[11] -translated mips_core/iexec_stage/pc_nxt/r32_o_11__Z
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/pc_nxt/r32_o[12] -translated mips_core/iexec_stage/pc_nxt/r32_o_12__Z
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/pc_nxt/r32_o[13] -translated mips_core/iexec_stage/pc_nxt/r32_o_13__Z
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/pc_nxt/r32_o[14] -translated mips_core/iexec_stage/pc_nxt/r32_o_14__Z
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/pc_nxt/r32_o[15] -translated mips_core/iexec_stage/pc_nxt/r32_o_15__Z
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/pc_nxt/r32_o[16] -translated mips_core/iexec_stage/pc_nxt/r32_o_16__Z
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/pc_nxt/r32_o[17] -translated mips_core/iexec_stage/pc_nxt/r32_o_17__Z
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/pc_nxt/r32_o[18] -translated mips_core/iexec_stage/pc_nxt/r32_o_18__Z
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/pc_nxt/r32_o[19] -translated mips_core/iexec_stage/pc_nxt/r32_o_19__Z
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/pc_nxt/r32_o[20] -translated mips_core/iexec_stage/pc_nxt/r32_o_20__Z
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/pc_nxt/r32_o[21] -translated mips_core/iexec_stage/pc_nxt/r32_o_21__Z
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/pc_nxt/r32_o[22] -translated mips_core/iexec_stage/pc_nxt/r32_o_22__Z
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/pc_nxt/r32_o[23] -translated mips_core/iexec_stage/pc_nxt/r32_o_23__Z
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/pc_nxt/r32_o[24] -translated mips_core/iexec_stage/pc_nxt/r32_o_24__Z
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/pc_nxt/r32_o[25] -translated mips_core/iexec_stage/pc_nxt/r32_o_25__Z
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/pc_nxt/r32_o[26] -translated mips_core/iexec_stage/pc_nxt/r32_o_26__Z
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/pc_nxt/r32_o[27] -translated mips_core/iexec_stage/pc_nxt/r32_o_27__Z
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/pc_nxt/r32_o[28] -translated mips_core/iexec_stage/pc_nxt/r32_o_28__Z
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/pc_nxt/r32_o[29] -translated mips_core/iexec_stage/pc_nxt/r32_o_29__Z
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/pc_nxt/r32_o[30] -translated mips_core/iexec_stage/pc_nxt/r32_o_30__Z
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/pc_nxt/r32_o[31] -translated mips_core/iexec_stage/pc_nxt/r32_o_31__Z
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/pc_nxt/r32_o[1] -translated mips_core/iexec_stage/pc_nxt/r32_o_1__Z
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/pc_nxt/r32_o[0] -translated mips_core/iexec_stage/pc_nxt/r32_o_0__Z
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/spc/r32_o[0] -translated mips_core/iexec_stage/spc/r32_o_0__Z
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/spc/r32_o[1] -translated mips_core/iexec_stage/spc/r32_o_1__Z
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/spc/r32_o[2] -translated mips_core/iexec_stage/spc/r32_o_2__Z
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/spc/r32_o[3] -translated mips_core/iexec_stage/spc/r32_o_3__Z
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/spc/r32_o[4] -translated mips_core/iexec_stage/spc/r32_o_4__Z
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/spc/r32_o[5] -translated mips_core/iexec_stage/spc/r32_o_5__Z
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/spc/r32_o[6] -translated mips_core/iexec_stage/spc/r32_o_6__Z
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/spc/r32_o[7] -translated mips_core/iexec_stage/spc/r32_o_7__Z
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/spc/r32_o[8] -translated mips_core/iexec_stage/spc/r32_o_8__Z
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/spc/r32_o[9] -translated mips_core/iexec_stage/spc/r32_o_9__Z
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/spc/r32_o[10] -translated mips_core/iexec_stage/spc/r32_o_10__Z
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/spc/r32_o[11] -translated mips_core/iexec_stage/spc/r32_o_11__Z
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/spc/r32_o[12] -translated mips_core/iexec_stage/spc/r32_o_12__Z
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/spc/r32_o[13] -translated mips_core/iexec_stage/spc/r32_o_13__Z
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/spc/r32_o[14] -translated mips_core/iexec_stage/spc/r32_o_14__Z
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/spc/r32_o[15] -translated mips_core/iexec_stage/spc/r32_o_15__Z
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/spc/r32_o[16] -translated mips_core/iexec_stage/spc/r32_o_16__Z
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/spc/r32_o[17] -translated mips_core/iexec_stage/spc/r32_o_17__Z
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/spc/r32_o[18] -translated mips_core/iexec_stage/spc/r32_o_18__Z
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/spc/r32_o[19] -translated mips_core/iexec_stage/spc/r32_o_19__Z
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/spc/r32_o[20] -translated mips_core/iexec_stage/spc/r32_o_20__Z
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/spc/r32_o[21] -translated mips_core/iexec_stage/spc/r32_o_21__Z
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/spc/r32_o[22] -translated mips_core/iexec_stage/spc/r32_o_22__Z
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/spc/r32_o[23] -translated mips_core/iexec_stage/spc/r32_o_23__Z
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/spc/r32_o[24] -translated mips_core/iexec_stage/spc/r32_o_24__Z
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/spc/r32_o[25] -translated mips_core/iexec_stage/spc/r32_o_25__Z
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/spc/r32_o[26] -translated mips_core/iexec_stage/spc/r32_o_26__Z
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/spc/r32_o[27] -translated mips_core/iexec_stage/spc/r32_o_27__Z
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/spc/r32_o[28] -translated mips_core/iexec_stage/spc/r32_o_28__Z
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/spc/r32_o[29] -translated mips_core/iexec_stage/spc/r32_o_29__Z
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/spc/r32_o[30] -translated mips_core/iexec_stage/spc/r32_o_30__Z
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/spc/r32_o[31] -translated mips_core/iexec_stage/spc/r32_o_31__Z
vif_set_sequential_verify -retimed -register -original mips_core/alu_pass0/r32_o[2] -translated mips_core/alu_pass0/r32_o_2__Z
vif_set_sequential_verify -retimed -register -original mips_core/alu_pass0/r32_o[3] -translated mips_core/alu_pass0/r32_o_3__Z
vif_set_sequential_verify -retimed -register -original mips_core/alu_pass0/r32_o[4] -translated mips_core/alu_pass0/r32_o_4__Z
vif_set_sequential_verify -retimed -register -original mips_core/alu_pass0/r32_o[5] -translated mips_core/alu_pass0/r32_o_5__Z
vif_set_sequential_verify -retimed -register -original mips_core/alu_pass0/r32_o[6] -translated mips_core/alu_pass0/r32_o_6__Z
vif_set_sequential_verify -retimed -register -original mips_core/alu_pass0/r32_o[7] -translated mips_core/alu_pass0/r32_o_7__Z
vif_set_sequential_verify -retimed -register -original mips_core/alu_pass0/r32_o[8] -translated mips_core/alu_pass0/r32_o_8__Z
vif_set_sequential_verify -retimed -register -original mips_core/alu_pass0/r32_o[9] -translated mips_core/alu_pass0/r32_o_9__Z
vif_set_sequential_verify -retimed -register -original mips_core/alu_pass0/r32_o[10] -translated mips_core/alu_pass0/r32_o_10__Z
vif_set_sequential_verify -retimed -register -original mips_core/alu_pass0/r32_o[11] -translated mips_core/alu_pass0/r32_o_11__Z
vif_set_sequential_verify -retimed -register -original mips_core/alu_pass0/r32_o[12] -translated mips_core/alu_pass0/r32_o_12__Z
vif_set_sequential_verify -retimed -register -original mips_core/alu_pass0/r32_o[13] -translated mips_core/alu_pass0/r32_o_13__Z
vif_set_sequential_verify -retimed -register -original mips_core/alu_pass0/r32_o[14] -translated mips_core/alu_pass0/r32_o_14__Z
vif_set_sequential_verify -retimed -register -original mips_core/alu_pass0/r32_o[15] -translated mips_core/alu_pass0/r32_o_15__Z
vif_set_sequential_verify -retimed -register -original mips_core/alu_pass0/r32_o[16] -translated mips_core/alu_pass0/r32_o_16__Z
vif_set_sequential_verify -retimed -register -original mips_core/alu_pass0/r32_o[17] -translated mips_core/alu_pass0/r32_o_17__Z
vif_set_sequential_verify -retimed -register -original mips_core/alu_pass0/r32_o[18] -translated mips_core/alu_pass0/r32_o_18__Z
vif_set_sequential_verify -retimed -register -original mips_core/alu_pass0/r32_o[19] -translated mips_core/alu_pass0/r32_o_19__Z
vif_set_sequential_verify -retimed -register -original mips_core/alu_pass0/r32_o[20] -translated mips_core/alu_pass0/r32_o_20__Z
vif_set_sequential_verify -retimed -register -original mips_core/alu_pass0/r32_o[21] -translated mips_core/alu_pass0/r32_o_21__Z
vif_set_sequential_verify -retimed -register -original mips_core/alu_pass0/r32_o[22] -translated mips_core/alu_pass0/r32_o_22__Z
vif_set_sequential_verify -retimed -register -original mips_core/alu_pass0/r32_o[23] -translated mips_core/alu_pass0/r32_o_23__Z
vif_set_sequential_verify -retimed -register -original mips_core/alu_pass0/r32_o[24] -translated mips_core/alu_pass0/r32_o_24__Z
vif_set_sequential_verify -retimed -register -original mips_core/alu_pass0/r32_o[25] -translated mips_core/alu_pass0/r32_o_25__Z
vif_set_sequential_verify -retimed -register -original mips_core/alu_pass0/r32_o[26] -translated mips_core/alu_pass0/r32_o_26__Z
vif_set_sequential_verify -retimed -register -original mips_core/alu_pass0/r32_o[27] -translated mips_core/alu_pass0/r32_o_27__Z
vif_set_sequential_verify -retimed -register -original mips_core/alu_pass0/r32_o[28] -translated mips_core/alu_pass0/r32_o_28__Z
vif_set_sequential_verify -retimed -register -original mips_core/alu_pass0/r32_o[29] -translated mips_core/alu_pass0/r32_o_29__Z
vif_set_sequential_verify -retimed -register -original mips_core/alu_pass0/r32_o[30] -translated mips_core/alu_pass0/r32_o_30__Z
vif_set_sequential_verify -retimed -register -original mips_core/alu_pass0/r32_o[31] -translated mips_core/alu_pass0/r32_o_31__Z
vif_set_sequential_verify -retimed -register -original mips_core/alu_pass1/r32_o[0] -translated mips_core/alu_pass1/r32_o_0__Z
vif_set_sequential_verify -retimed -register -original mips_core/alu_pass1/r32_o[1] -translated mips_core/alu_pass1/r32_o_1__Z
vif_set_sequential_verify -retimed -register -original mips_core/alu_pass1/r32_o[2] -translated mips_core/alu_pass1/r32_o_2__Z
vif_set_sequential_verify -retimed -register -original mips_core/alu_pass1/r32_o[3] -translated mips_core/alu_pass1/r32_o_3__Z
vif_set_sequential_verify -retimed -register -original mips_core/alu_pass1/r32_o[4] -translated mips_core/alu_pass1/r32_o_4__Z
vif_set_sequential_verify -retimed -register -original mips_core/alu_pass1/r32_o[5] -translated mips_core/alu_pass1/r32_o_5__Z
vif_set_sequential_verify -retimed -register -original mips_core/alu_pass1/r32_o[6] -translated mips_core/alu_pass1/r32_o_6__Z
vif_set_sequential_verify -retimed -register -original mips_core/alu_pass1/r32_o[7] -translated mips_core/alu_pass1/r32_o_7__Z
vif_set_sequential_verify -retimed -register -original mips_core/alu_pass1/r32_o[8] -translated mips_core/alu_pass1/r32_o_8__Z
vif_set_sequential_verify -retimed -register -original mips_core/alu_pass1/r32_o[9] -translated mips_core/alu_pass1/r32_o_9__Z
vif_set_sequential_verify -retimed -register -original mips_core/alu_pass1/r32_o[10] -translated mips_core/alu_pass1/r32_o_10__Z
vif_set_sequential_verify -retimed -register -original mips_core/alu_pass1/r32_o[11] -translated mips_core/alu_pass1/r32_o_11__Z
vif_set_sequential_verify -retimed -register -original mips_core/alu_pass1/r32_o[12] -translated mips_core/alu_pass1/r32_o_12__Z
vif_set_sequential_verify -retimed -register -original mips_core/alu_pass1/r32_o[13] -translated mips_core/alu_pass1/r32_o_13__Z
vif_set_sequential_verify -retimed -register -original mips_core/alu_pass1/r32_o[14] -translated mips_core/alu_pass1/r32_o_14__Z
vif_set_sequential_verify -retimed -register -original mips_core/alu_pass1/r32_o[15] -translated mips_core/alu_pass1/r32_o_15__Z
vif_set_sequential_verify -retimed -register -original mips_core/alu_pass1/r32_o[16] -translated mips_core/alu_pass1/r32_o_16__Z
vif_set_sequential_verify -retimed -register -original mips_core/alu_pass1/r32_o[17] -translated mips_core/alu_pass1/r32_o_17__Z
vif_set_sequential_verify -retimed -register -original mips_core/alu_pass1/r32_o[18] -translated mips_core/alu_pass1/r32_o_18__Z
vif_set_sequential_verify -retimed -register -original mips_core/alu_pass1/r32_o[19] -translated mips_core/alu_pass1/r32_o_19__Z
vif_set_sequential_verify -retimed -register -original mips_core/alu_pass1/r32_o[20] -translated mips_core/alu_pass1/r32_o_20__Z
vif_set_sequential_verify -retimed -register -original mips_core/alu_pass1/r32_o[21] -translated mips_core/alu_pass1/r32_o_21__Z
vif_set_sequential_verify -retimed -register -original mips_core/alu_pass1/r32_o[22] -translated mips_core/alu_pass1/r32_o_22__Z
vif_set_sequential_verify -retimed -register -original mips_core/alu_pass1/r32_o[23] -translated mips_core/alu_pass1/r32_o_23__Z
vif_set_sequential_verify -retimed -register -original mips_core/alu_pass1/r32_o[24] -translated mips_core/alu_pass1/r32_o_24__Z
vif_set_sequential_verify -retimed -register -original mips_core/alu_pass1/r32_o[25] -translated mips_core/alu_pass1/r32_o_25__Z
vif_set_sequential_verify -retimed -register -original mips_core/alu_pass1/r32_o[26] -translated mips_core/alu_pass1/r32_o_26__Z
vif_set_sequential_verify -retimed -register -original mips_core/alu_pass1/r32_o[27] -translated mips_core/alu_pass1/r32_o_27__Z
vif_set_sequential_verify -retimed -register -original mips_core/alu_pass1/r32_o[28] -translated mips_core/alu_pass1/r32_o_28__Z
vif_set_sequential_verify -retimed -register -original mips_core/alu_pass1/r32_o[29] -translated mips_core/alu_pass1/r32_o_29__Z
vif_set_sequential_verify -retimed -register -original mips_core/alu_pass1/r32_o[30] -translated mips_core/alu_pass1/r32_o_30__Z
vif_set_sequential_verify -retimed -register -original mips_core/alu_pass1/r32_o[31] -translated mips_core/alu_pass1/r32_o_31__Z
vif_set_sequential_verify -retimed -register -original mips_core/cop_data_reg/r32_o[0] -translated mips_core/cop_data_reg/r32_o_0__Z
vif_set_sequential_verify -retimed -register -original mips_core/cop_data_reg/r32_o[1] -translated mips_core/cop_data_reg/r32_o_1__Z
vif_set_sequential_verify -retimed -register -original mips_core/cop_data_reg/r32_o[2] -translated mips_core/cop_data_reg/r32_o_2__Z
vif_set_sequential_verify -retimed -register -original mips_core/cop_data_reg/r32_o[3] -translated mips_core/cop_data_reg/r32_o_3__Z
vif_set_sequential_verify -retimed -register -original mips_core/cop_data_reg/r32_o[4] -translated mips_core/cop_data_reg/r32_o_4__Z
vif_set_sequential_verify -retimed -register -original mips_core/cop_data_reg/r32_o[5] -translated mips_core/cop_data_reg/r32_o_5__Z
vif_set_sequential_verify -retimed -register -original mips_core/cop_data_reg/r32_o[6] -translated mips_core/cop_data_reg/r32_o_6__Z
vif_set_sequential_verify -retimed -register -original mips_core/cop_data_reg/r32_o[7] -translated mips_core/cop_data_reg/r32_o_7__Z
vif_set_sequential_verify -retimed -register -original mips_core/cop_data_reg/r32_o[8] -translated mips_core/cop_data_reg/r32_o_8__Z
vif_set_sequential_verify -retimed -register -original mips_core/cop_data_reg/r32_o[9] -translated mips_core/cop_data_reg/r32_o_9__Z
vif_set_sequential_verify -retimed -register -original mips_core/cop_data_reg/r32_o[10] -translated mips_core/cop_data_reg/r32_o_10__Z
vif_set_sequential_verify -retimed -register -original mips_core/cop_data_reg/r32_o[11] -translated mips_core/cop_data_reg/r32_o_11__Z
vif_set_sequential_verify -retimed -register -original mips_core/cop_data_reg/r32_o[12] -translated mips_core/cop_data_reg/r32_o_12__Z
vif_set_sequential_verify -retimed -register -original mips_core/cop_data_reg/r32_o[13] -translated mips_core/cop_data_reg/r32_o_13__Z
vif_set_sequential_verify -retimed -register -original mips_core/cop_data_reg/r32_o[14] -translated mips_core/cop_data_reg/r32_o_14__Z
vif_set_sequential_verify -retimed -register -original mips_core/cop_data_reg/r32_o[15] -translated mips_core/cop_data_reg/r32_o_15__Z
vif_set_sequential_verify -retimed -register -original mips_core/cop_data_reg/r32_o[16] -translated mips_core/cop_data_reg/r32_o_16__Z
vif_set_sequential_verify -retimed -register -original mips_core/cop_data_reg/r32_o[17] -translated mips_core/cop_data_reg/r32_o_17__Z
vif_set_sequential_verify -retimed -register -original mips_core/cop_data_reg/r32_o[18] -translated mips_core/cop_data_reg/r32_o_18__Z
vif_set_sequential_verify -retimed -register -original mips_core/cop_data_reg/r32_o[19] -translated mips_core/cop_data_reg/r32_o_19__Z
vif_set_sequential_verify -retimed -register -original mips_core/cop_data_reg/r32_o[20] -translated mips_core/cop_data_reg/r32_o_20__Z
vif_set_sequential_verify -retimed -register -original mips_core/cop_data_reg/r32_o[21] -translated mips_core/cop_data_reg/r32_o_21__Z
vif_set_sequential_verify -retimed -register -original mips_core/cop_data_reg/r32_o[22] -translated mips_core/cop_data_reg/r32_o_22__Z
vif_set_sequential_verify -retimed -register -original mips_core/cop_data_reg/r32_o[23] -translated mips_core/cop_data_reg/r32_o_23__Z
vif_set_sequential_verify -retimed -register -original mips_core/cop_data_reg/r32_o[24] -translated mips_core/cop_data_reg/r32_o_24__Z
vif_set_sequential_verify -retimed -register -original mips_core/cop_data_reg/r32_o[25] -translated mips_core/cop_data_reg/r32_o_25__Z
vif_set_sequential_verify -retimed -register -original mips_core/cop_data_reg/r32_o[26] -translated mips_core/cop_data_reg/r32_o_26__Z
vif_set_sequential_verify -retimed -register -original mips_core/cop_data_reg/r32_o[27] -translated mips_core/cop_data_reg/r32_o_27__Z
vif_set_sequential_verify -retimed -register -original mips_core/cop_data_reg/r32_o[28] -translated mips_core/cop_data_reg/r32_o_28__Z
vif_set_sequential_verify -retimed -register -original mips_core/cop_data_reg/r32_o[29] -translated mips_core/cop_data_reg/r32_o_29__Z
vif_set_sequential_verify -retimed -register -original mips_core/cop_data_reg/r32_o[30] -translated mips_core/cop_data_reg/r32_o_30__Z
vif_set_sequential_verify -retimed -register -original mips_core/cop_data_reg/r32_o[31] -translated mips_core/cop_data_reg/r32_o_31__Z
vif_set_sequential_verify -retimed -register -original mips_core/cop_dout_reg/r32_o[0] -translated mips_core/cop_dout_reg/r32_o_0__Z
vif_set_sequential_verify -retimed -register -original mips_core/cop_dout_reg/r32_o[1] -translated mips_core/cop_dout_reg/r32_o_1__Z
vif_set_sequential_verify -retimed -register -original mips_core/cop_dout_reg/r32_o[2] -translated mips_core/cop_dout_reg/r32_o_2__Z
vif_set_sequential_verify -retimed -register -original mips_core/cop_dout_reg/r32_o[3] -translated mips_core/cop_dout_reg/r32_o_3__Z
vif_set_sequential_verify -retimed -register -original mips_core/cop_dout_reg/r32_o[4] -translated mips_core/cop_dout_reg/r32_o_4__Z
vif_set_sequential_verify -retimed -register -original mips_core/cop_dout_reg/r32_o[5] -translated mips_core/cop_dout_reg/r32_o_5__Z
vif_set_sequential_verify -retimed -register -original mips_core/cop_dout_reg/r32_o[6] -translated mips_core/cop_dout_reg/r32_o_6__Z
vif_set_sequential_verify -retimed -register -original mips_core/cop_dout_reg/r32_o[7] -translated mips_core/cop_dout_reg/r32_o_7__Z
vif_set_sequential_verify -retimed -register -original mips_core/cop_dout_reg/r32_o[8] -translated mips_core/cop_dout_reg/r32_o_8__Z
vif_set_sequential_verify -retimed -register -original mips_core/cop_dout_reg/r32_o[9] -translated mips_core/cop_dout_reg/r32_o_9__Z
vif_set_sequential_verify -retimed -register -original mips_core/cop_dout_reg/r32_o[10] -translated mips_core/cop_dout_reg/r32_o_10__Z
vif_set_sequential_verify -retimed -register -original mips_core/cop_dout_reg/r32_o[11] -translated mips_core/cop_dout_reg/r32_o_11__Z
vif_set_sequential_verify -retimed -register -original mips_core/cop_dout_reg/r32_o[12] -translated mips_core/cop_dout_reg/r32_o_12__Z
vif_set_sequential_verify -retimed -register -original mips_core/cop_dout_reg/r32_o[13] -translated mips_core/cop_dout_reg/r32_o_13__Z
vif_set_sequential_verify -retimed -register -original mips_core/cop_dout_reg/r32_o[14] -translated mips_core/cop_dout_reg/r32_o_14__Z
vif_set_sequential_verify -retimed -register -original mips_core/cop_dout_reg/r32_o[15] -translated mips_core/cop_dout_reg/r32_o_15__Z
vif_set_sequential_verify -retimed -register -original mips_core/cop_dout_reg/r32_o[16] -translated mips_core/cop_dout_reg/r32_o_16__Z
vif_set_sequential_verify -retimed -register -original mips_core/cop_dout_reg/r32_o[17] -translated mips_core/cop_dout_reg/r32_o_17__Z
vif_set_sequential_verify -retimed -register -original mips_core/cop_dout_reg/r32_o[18] -translated mips_core/cop_dout_reg/r32_o_18__Z
vif_set_sequential_verify -retimed -register -original mips_core/cop_dout_reg/r32_o[19] -translated mips_core/cop_dout_reg/r32_o_19__Z
vif_set_sequential_verify -retimed -register -original mips_core/cop_dout_reg/r32_o[20] -translated mips_core/cop_dout_reg/r32_o_20__Z
vif_set_sequential_verify -retimed -register -original mips_core/cop_dout_reg/r32_o[21] -translated mips_core/cop_dout_reg/r32_o_21__Z
vif_set_sequential_verify -retimed -register -original mips_core/cop_dout_reg/r32_o[22] -translated mips_core/cop_dout_reg/r32_o_22__Z
vif_set_sequential_verify -retimed -register -original mips_core/cop_dout_reg/r32_o[23] -translated mips_core/cop_dout_reg/r32_o_23__Z
vif_set_sequential_verify -retimed -register -original mips_core/cop_dout_reg/r32_o[24] -translated mips_core/cop_dout_reg/r32_o_24__Z
vif_set_sequential_verify -retimed -register -original mips_core/cop_dout_reg/r32_o[25] -translated mips_core/cop_dout_reg/r32_o_25__Z
vif_set_sequential_verify -retimed -register -original mips_core/cop_dout_reg/r32_o[26] -translated mips_core/cop_dout_reg/r32_o_26__Z
vif_set_sequential_verify -retimed -register -original mips_core/cop_dout_reg/r32_o[27] -translated mips_core/cop_dout_reg/r32_o_27__Z
vif_set_sequential_verify -retimed -register -original mips_core/cop_dout_reg/r32_o[28] -translated mips_core/cop_dout_reg/r32_o_28__Z
vif_set_sequential_verify -retimed -register -original mips_core/cop_dout_reg/r32_o[29] -translated mips_core/cop_dout_reg/r32_o_29__Z
vif_set_sequential_verify -retimed -register -original mips_core/cop_dout_reg/r32_o[30] -translated mips_core/cop_dout_reg/r32_o_30__Z
vif_set_sequential_verify -retimed -register -original mips_core/cop_dout_reg/r32_o[31] -translated mips_core/cop_dout_reg/r32_o_31__Z
vif_set_sequential_verify -retimed -register -original mips_core/decoder_pipe/pipereg/U12/wb_we_o[0] -translated mips_core/decoder_pipe/pipereg/U12/wb_we_o_0__Z
vif_set_sequential_verify -retimed -register -original mips_core/decoder_pipe/pipereg/U18/wb_mux_ctl_o[0] -translated mips_core/decoder_pipe/pipereg/U18/wb_mux_ctl_o_0__Z
vif_set_sequential_verify -retimed -register -original mips_core/decoder_pipe/pipereg/U20/wb_we_o[0] -translated mips_core/decoder_pipe/pipereg/U20/wb_we_o_0__Z
vif_set_sequential_verify -retimed -register -original mips_core/decoder_pipe/pipereg/U21/wb_mux_ctl_o[0] -translated mips_core/decoder_pipe/pipereg/U21/wb_mux_ctl_o_0__Z
vif_set_sequential_verify -retimed -register -original mips_core/decoder_pipe/pipereg/U22/wb_we_o[0] -translated mips_core/decoder_pipe/pipereg/U22/wb_we_o_0__Z
vif_set_sequential_verify -retimed -register -original mips_core/decoder_pipe/pipereg/U9/dmem_ctl_o[0] -translated mips_core/decoder_pipe/pipereg/U9/dmem_ctl_o_0__Z
vif_set_sequential_verify -retimed -register -original mips_core/decoder_pipe/pipereg/U9/dmem_ctl_o[1] -translated mips_core/decoder_pipe/pipereg/U9/dmem_ctl_o_1__Z
vif_set_sequential_verify -retimed -register -original mips_core/decoder_pipe/pipereg/U9/dmem_ctl_o[2] -translated mips_core/decoder_pipe/pipereg/U9/dmem_ctl_o_2__Z
vif_set_sequential_verify -retimed -register -original mips_core/decoder_pipe/pipereg/U9/dmem_ctl_o[3] -translated mips_core/decoder_pipe/pipereg/U9/dmem_ctl_o_3__Z
vif_set_sequential_verify -retimed -register -original mips_core/ext_reg/r32_o[0] -translated mips_core/ext_reg/r32_o_0__Z
vif_set_sequential_verify -retimed -register -original mips_core/ext_reg/r32_o[1] -translated mips_core/ext_reg/r32_o_1__Z
vif_set_sequential_verify -retimed -register -original mips_core/ext_reg/r32_o[2] -translated mips_core/ext_reg/r32_o_2__Z
vif_set_sequential_verify -retimed -register -original mips_core/ext_reg/r32_o[3] -translated mips_core/ext_reg/r32_o_3__Z
vif_set_sequential_verify -retimed -register -original mips_core/ext_reg/r32_o[4] -translated mips_core/ext_reg/r32_o_4__Z
vif_set_sequential_verify -retimed -register -original mips_core/ext_reg/r32_o[5] -translated mips_core/ext_reg/r32_o_5__Z
vif_set_sequential_verify -retimed -register -original mips_core/ext_reg/r32_o[6] -translated mips_core/ext_reg/r32_o_6__Z
vif_set_sequential_verify -retimed -register -original mips_core/ext_reg/r32_o[7] -translated mips_core/ext_reg/r32_o_7__Z
vif_set_sequential_verify -retimed -register -original mips_core/ext_reg/r32_o[8] -translated mips_core/ext_reg/r32_o_8__Z
vif_set_sequential_verify -retimed -register -original mips_core/ext_reg/r32_o[9] -translated mips_core/ext_reg/r32_o_9__Z
vif_set_sequential_verify -retimed -register -original mips_core/ext_reg/r32_o[10] -translated mips_core/ext_reg/r32_o_10__Z
vif_set_sequential_verify -retimed -register -original mips_core/ext_reg/r32_o[11] -translated mips_core/ext_reg/r32_o_11__Z
vif_set_sequential_verify -retimed -register -original mips_core/ext_reg/r32_o[12] -translated mips_core/ext_reg/r32_o_12__Z
vif_set_sequential_verify -retimed -register -original mips_core/ext_reg/r32_o[13] -translated mips_core/ext_reg/r32_o_13__Z
vif_set_sequential_verify -retimed -register -original mips_core/ext_reg/r32_o[14] -translated mips_core/ext_reg/r32_o_14__Z
vif_set_sequential_verify -retimed -register -original mips_core/ext_reg/r32_o[15] -translated mips_core/ext_reg/r32_o_15__Z
vif_set_sequential_verify -retimed -register -original mips_core/ext_reg/r32_o[16] -translated mips_core/ext_reg/r32_o_16__Z
vif_set_sequential_verify -retimed -register -original mips_core/ext_reg/r32_o[17] -translated mips_core/ext_reg/r32_o_17__Z
vif_set_sequential_verify -retimed -register -original mips_core/ext_reg/r32_o[18] -translated mips_core/ext_reg/r32_o_18__Z
vif_set_sequential_verify -retimed -register -original mips_core/ext_reg/r32_o[19] -translated mips_core/ext_reg/r32_o_19__Z
vif_set_sequential_verify -retimed -register -original mips_core/ext_reg/r32_o[20] -translated mips_core/ext_reg/r32_o_20__Z
vif_set_sequential_verify -retimed -register -original mips_core/ext_reg/r32_o[21] -translated mips_core/ext_reg/r32_o_21__Z
vif_set_sequential_verify -retimed -register -original mips_core/ext_reg/r32_o[22] -translated mips_core/ext_reg/r32_o_22__Z
vif_set_sequential_verify -retimed -register -original mips_core/ext_reg/r32_o[23] -translated mips_core/ext_reg/r32_o_23__Z
vif_set_sequential_verify -retimed -register -original mips_core/ext_reg/r32_o[24] -translated mips_core/ext_reg/r32_o_24__Z
vif_set_sequential_verify -retimed -register -original mips_core/ext_reg/r32_o[25] -translated mips_core/ext_reg/r32_o_25__Z
vif_set_sequential_verify -retimed -register -original mips_core/ext_reg/r32_o[26] -translated mips_core/ext_reg/r32_o_26__Z
vif_set_sequential_verify -retimed -register -original mips_core/ext_reg/r32_o[27] -translated mips_core/ext_reg/r32_o_27__Z
vif_set_sequential_verify -retimed -register -original mips_core/ext_reg/r32_o[28] -translated mips_core/ext_reg/r32_o_28__Z
vif_set_sequential_verify -retimed -register -original mips_core/ext_reg/r32_o[29] -translated mips_core/ext_reg/r32_o_29__Z
vif_set_sequential_verify -retimed -register -original mips_core/ext_reg/r32_o[30] -translated mips_core/ext_reg/r32_o_30__Z
vif_set_sequential_verify -retimed -register -original mips_core/ext_reg/r32_o[31] -translated mips_core/ext_reg/r32_o_31__Z
vif_set_sequential_verify -retimed -register -original mips_core/iforward/fw_reg_rns/q[0] -translated mips_core/iforward/fw_reg_rns/q_0__Z
vif_set_sequential_verify -retimed -register -original mips_core/iforward/fw_reg_rns/q[1] -translated mips_core/iforward/fw_reg_rns/q_1__Z
vif_set_sequential_verify -retimed -register -original mips_core/iforward/fw_reg_rns/q[2] -translated mips_core/iforward/fw_reg_rns/q_2__Z
vif_set_sequential_verify -retimed -register -original mips_core/iforward/fw_reg_rns/q[3] -translated mips_core/iforward/fw_reg_rns/q_3__Z
vif_set_sequential_verify -retimed -register -original mips_core/iforward/fw_reg_rns/q[4] -translated mips_core/iforward/fw_reg_rns/q_4__Z
vif_set_sequential_verify -retimed -register -original mips_core/iforward/fw_reg_rnt/q[0] -translated mips_core/iforward/fw_reg_rnt/q_0__Z
vif_set_sequential_verify -retimed -register -original mips_core/iforward/fw_reg_rnt/q[1] -translated mips_core/iforward/fw_reg_rnt/q_1__Z
vif_set_sequential_verify -retimed -register -original mips_core/iforward/fw_reg_rnt/q[2] -translated mips_core/iforward/fw_reg_rnt/q_2__Z
vif_set_sequential_verify -retimed -register -original mips_core/iforward/fw_reg_rnt/q[3] -translated mips_core/iforward/fw_reg_rnt/q_3__Z
vif_set_sequential_verify -retimed -register -original mips_core/iforward/fw_reg_rnt/q[4] -translated mips_core/iforward/fw_reg_rnt/q_4__Z
vif_set_sequential_verify -retimed -register -original mips_core/pc/r32_o[0] -translated mips_core/pc/r32_o_0__Z
vif_set_sequential_verify -retimed -register -original mips_core/pc/r32_o[1] -translated mips_core/pc/r32_o_1__Z
vif_set_sequential_verify -retimed -register -original mips_core/pc/r32_o[2] -translated mips_core/pc/r32_o_2__Z
vif_set_sequential_verify -retimed -register -original mips_core/pc/r32_o[3] -translated mips_core/pc/r32_o_3__Z
vif_set_sequential_verify -retimed -register -original mips_core/pc/r32_o[4] -translated mips_core/pc/r32_o_4__Z
vif_set_sequential_verify -retimed -register -original mips_core/pc/r32_o[5] -translated mips_core/pc/r32_o_5__Z
vif_set_sequential_verify -retimed -register -original mips_core/pc/r32_o[6] -translated mips_core/pc/r32_o_6__Z
vif_set_sequential_verify -retimed -register -original mips_core/pc/r32_o[7] -translated mips_core/pc/r32_o_7__Z
vif_set_sequential_verify -retimed -register -original mips_core/pc/r32_o[8] -translated mips_core/pc/r32_o_8__Z
vif_set_sequential_verify -retimed -register -original mips_core/pc/r32_o[9] -translated mips_core/pc/r32_o_9__Z
vif_set_sequential_verify -retimed -register -original mips_core/pc/r32_o[10] -translated mips_core/pc/r32_o_10__Z
vif_set_sequential_verify -retimed -register -original mips_core/pc/r32_o[11] -translated mips_core/pc/r32_o_11__Z
vif_set_sequential_verify -retimed -register -original mips_core/pc/r32_o[12] -translated mips_core/pc/r32_o_12__Z
vif_set_sequential_verify -retimed -register -original mips_core/pc/r32_o[13] -translated mips_core/pc/r32_o_13__Z
vif_set_sequential_verify -retimed -register -original mips_core/pc/r32_o[14] -translated mips_core/pc/r32_o_14__Z
vif_set_sequential_verify -retimed -register -original mips_core/pc/r32_o[15] -translated mips_core/pc/r32_o_15__Z
vif_set_sequential_verify -retimed -register -original mips_core/pc/r32_o[16] -translated mips_core/pc/r32_o_16__Z
vif_set_sequential_verify -retimed -register -original mips_core/pc/r32_o[17] -translated mips_core/pc/r32_o_17__Z
vif_set_sequential_verify -retimed -register -original mips_core/pc/r32_o[18] -translated mips_core/pc/r32_o_18__Z
vif_set_sequential_verify -retimed -register -original mips_core/pc/r32_o[19] -translated mips_core/pc/r32_o_19__Z
vif_set_sequential_verify -retimed -register -original mips_core/pc/r32_o[20] -translated mips_core/pc/r32_o_20__Z
vif_set_sequential_verify -retimed -register -original mips_core/pc/r32_o[21] -translated mips_core/pc/r32_o_21__Z
vif_set_sequential_verify -retimed -register -original mips_core/pc/r32_o[22] -translated mips_core/pc/r32_o_22__Z
vif_set_sequential_verify -retimed -register -original mips_core/pc/r32_o[23] -translated mips_core/pc/r32_o_23__Z
vif_set_sequential_verify -retimed -register -original mips_core/pc/r32_o[24] -translated mips_core/pc/r32_o_24__Z
vif_set_sequential_verify -retimed -register -original mips_core/pc/r32_o[25] -translated mips_core/pc/r32_o_25__Z
vif_set_sequential_verify -retimed -register -original mips_core/pc/r32_o[26] -translated mips_core/pc/r32_o_26__Z
vif_set_sequential_verify -retimed -register -original mips_core/pc/r32_o[27] -translated mips_core/pc/r32_o_27__Z
vif_set_sequential_verify -retimed -register -original mips_core/pc/r32_o[28] -translated mips_core/pc/r32_o_28__Z
vif_set_sequential_verify -retimed -register -original mips_core/pc/r32_o[29] -translated mips_core/pc/r32_o_29__Z
vif_set_sequential_verify -retimed -register -original mips_core/pc/r32_o[30] -translated mips_core/pc/r32_o_30__Z
vif_set_sequential_verify -retimed -register -original mips_core/pc/r32_o[31] -translated mips_core/pc/r32_o_31__Z
vif_set_sequential_verify -retimed -register -original mips_core/rnd_pass0/r5_o[0] -translated mips_core/rnd_pass0/r5_o_0__Z
vif_set_sequential_verify -retimed -register -original mips_core/rnd_pass0/r5_o[1] -translated mips_core/rnd_pass0/r5_o_1__Z
vif_set_sequential_verify -retimed -register -original mips_core/rnd_pass0/r5_o[2] -translated mips_core/rnd_pass0/r5_o_2__Z
vif_set_sequential_verify -retimed -register -original mips_core/rnd_pass0/r5_o[3] -translated mips_core/rnd_pass0/r5_o_3__Z
vif_set_sequential_verify -retimed -register -original mips_core/rnd_pass0/r5_o[4] -translated mips_core/rnd_pass0/r5_o_4__Z
vif_set_sequential_verify -retimed -register -original mips_core/rnd_pass1/r5_o[0] -translated mips_core/rnd_pass1/r5_o_0__Z
vif_set_sequential_verify -retimed -register -original mips_core/rnd_pass1/r5_o[1] -translated mips_core/rnd_pass1/r5_o_1__Z
vif_set_sequential_verify -retimed -register -original mips_core/rnd_pass1/r5_o[2] -translated mips_core/rnd_pass1/r5_o_2__Z
vif_set_sequential_verify -retimed -register -original mips_core/rnd_pass1/r5_o[3] -translated mips_core/rnd_pass1/r5_o_3__Z
vif_set_sequential_verify -retimed -register -original mips_core/rnd_pass1/r5_o[4] -translated mips_core/rnd_pass1/r5_o_4__Z
vif_set_sequential_verify -retimed -register -original mips_core/rnd_pass2/r5_o[0] -translated mips_core/rnd_pass2/r5_o_0__Z
vif_set_sequential_verify -retimed -register -original mips_core/rnd_pass2/r5_o[1] -translated mips_core/rnd_pass2/r5_o_1__Z
vif_set_sequential_verify -retimed -register -original mips_core/rnd_pass2/r5_o[2] -translated mips_core/rnd_pass2/r5_o_2__Z
vif_set_sequential_verify -retimed -register -original mips_core/rnd_pass2/r5_o[3] -translated mips_core/rnd_pass2/r5_o_3__Z
vif_set_sequential_verify -retimed -register -original mips_core/rnd_pass2/r5_o[4] -translated mips_core/rnd_pass2/r5_o_4__Z
vif_set_sequential_verify -retimed -register -original mips_core/rs_reg/r32_o[0] -translated mips_core/rs_reg/r32_o_0__Z
vif_set_sequential_verify -retimed -register -original mips_core/rs_reg/r32_o[1] -translated mips_core/rs_reg/r32_o_1__Z
vif_set_sequential_verify -retimed -register -original mips_core/rs_reg/r32_o[2] -translated mips_core/rs_reg/r32_o_2__Z
vif_set_sequential_verify -retimed -register -original mips_core/rs_reg/r32_o[3] -translated mips_core/rs_reg/r32_o_3__Z
vif_set_sequential_verify -retimed -register -original mips_core/rs_reg/r32_o[4] -translated mips_core/rs_reg/r32_o_4__Z
vif_set_sequential_verify -retimed -register -original mips_core/rs_reg/r32_o[5] -translated mips_core/rs_reg/r32_o_5__Z
vif_set_sequential_verify -retimed -register -original mips_core/rs_reg/r32_o[6] -translated mips_core/rs_reg/r32_o_6__Z
vif_set_sequential_verify -retimed -register -original mips_core/rs_reg/r32_o[7] -translated mips_core/rs_reg/r32_o_7__Z
vif_set_sequential_verify -retimed -register -original mips_core/rs_reg/r32_o[8] -translated mips_core/rs_reg/r32_o_8__Z
vif_set_sequential_verify -retimed -register -original mips_core/rs_reg/r32_o[9] -translated mips_core/rs_reg/r32_o_9__Z
vif_set_sequential_verify -retimed -register -original mips_core/rs_reg/r32_o[10] -translated mips_core/rs_reg/r32_o_10__Z
vif_set_sequential_verify -retimed -register -original mips_core/rs_reg/r32_o[11] -translated mips_core/rs_reg/r32_o_11__Z
vif_set_sequential_verify -retimed -register -original mips_core/rs_reg/r32_o[12] -translated mips_core/rs_reg/r32_o_12__Z
vif_set_sequential_verify -retimed -register -original mips_core/rs_reg/r32_o[13] -translated mips_core/rs_reg/r32_o_13__Z
vif_set_sequential_verify -retimed -register -original mips_core/rs_reg/r32_o[14] -translated mips_core/rs_reg/r32_o_14__Z
vif_set_sequential_verify -retimed -register -original mips_core/rs_reg/r32_o[15] -translated mips_core/rs_reg/r32_o_15__Z
vif_set_sequential_verify -retimed -register -original mips_core/rs_reg/r32_o[16] -translated mips_core/rs_reg/r32_o_16__Z
vif_set_sequential_verify -retimed -register -original mips_core/rs_reg/r32_o[17] -translated mips_core/rs_reg/r32_o_17__Z
vif_set_sequential_verify -retimed -register -original mips_core/rs_reg/r32_o[18] -translated mips_core/rs_reg/r32_o_18__Z
vif_set_sequential_verify -retimed -register -original mips_core/rs_reg/r32_o[19] -translated mips_core/rs_reg/r32_o_19__Z
vif_set_sequential_verify -retimed -register -original mips_core/rs_reg/r32_o[20] -translated mips_core/rs_reg/r32_o_20__Z
vif_set_sequential_verify -retimed -register -original mips_core/rs_reg/r32_o[21] -translated mips_core/rs_reg/r32_o_21__Z
vif_set_sequential_verify -retimed -register -original mips_core/rs_reg/r32_o[22] -translated mips_core/rs_reg/r32_o_22__Z
vif_set_sequential_verify -retimed -register -original mips_core/rs_reg/r32_o[23] -translated mips_core/rs_reg/r32_o_23__Z
vif_set_sequential_verify -retimed -register -original mips_core/rs_reg/r32_o[24] -translated mips_core/rs_reg/r32_o_24__Z
vif_set_sequential_verify -retimed -register -original mips_core/rs_reg/r32_o[25] -translated mips_core/rs_reg/r32_o_25__Z
vif_set_sequential_verify -retimed -register -original mips_core/rs_reg/r32_o[26] -translated mips_core/rs_reg/r32_o_26__Z
vif_set_sequential_verify -retimed -register -original mips_core/rs_reg/r32_o[27] -translated mips_core/rs_reg/r32_o_27__Z
vif_set_sequential_verify -retimed -register -original mips_core/rs_reg/r32_o[28] -translated mips_core/rs_reg/r32_o_28__Z
vif_set_sequential_verify -retimed -register -original mips_core/rs_reg/r32_o[29] -translated mips_core/rs_reg/r32_o_29__Z
vif_set_sequential_verify -retimed -register -original mips_core/rs_reg/r32_o[30] -translated mips_core/rs_reg/r32_o_30__Z
vif_set_sequential_verify -retimed -register -original mips_core/rs_reg/r32_o[31] -translated mips_core/rs_reg/r32_o_31__Z
vif_set_sequential_verify -retimed -register -original mips_core/rt_reg/r32_o[0] -translated mips_core/rt_reg/r32_o_0__Z
vif_set_sequential_verify -retimed -register -original mips_core/rt_reg/r32_o[1] -translated mips_core/rt_reg/r32_o_1__Z
vif_set_sequential_verify -retimed -register -original mips_core/rt_reg/r32_o[2] -translated mips_core/rt_reg/r32_o_2__Z
vif_set_sequential_verify -retimed -register -original mips_core/rt_reg/r32_o[3] -translated mips_core/rt_reg/r32_o_3__Z
vif_set_sequential_verify -retimed -register -original mips_core/rt_reg/r32_o[4] -translated mips_core/rt_reg/r32_o_4__Z
vif_set_sequential_verify -retimed -register -original mips_core/rt_reg/r32_o[5] -translated mips_core/rt_reg/r32_o_5__Z
vif_set_sequential_verify -retimed -register -original mips_core/rt_reg/r32_o[6] -translated mips_core/rt_reg/r32_o_6__Z
vif_set_sequential_verify -retimed -register -original mips_core/rt_reg/r32_o[7] -translated mips_core/rt_reg/r32_o_7__Z
vif_set_sequential_verify -retimed -register -original mips_core/rt_reg/r32_o[8] -translated mips_core/rt_reg/r32_o_8__Z
vif_set_sequential_verify -retimed -register -original mips_core/rt_reg/r32_o[9] -translated mips_core/rt_reg/r32_o_9__Z
vif_set_sequential_verify -retimed -register -original mips_core/rt_reg/r32_o[10] -translated mips_core/rt_reg/r32_o_10__Z
vif_set_sequential_verify -retimed -register -original mips_core/rt_reg/r32_o[11] -translated mips_core/rt_reg/r32_o_11__Z
vif_set_sequential_verify -retimed -register -original mips_core/rt_reg/r32_o[12] -translated mips_core/rt_reg/r32_o_12__Z
vif_set_sequential_verify -retimed -register -original mips_core/rt_reg/r32_o[13] -translated mips_core/rt_reg/r32_o_13__Z
vif_set_sequential_verify -retimed -register -original mips_core/rt_reg/r32_o[14] -translated mips_core/rt_reg/r32_o_14__Z
vif_set_sequential_verify -retimed -register -original mips_core/rt_reg/r32_o[15] -translated mips_core/rt_reg/r32_o_15__Z
vif_set_sequential_verify -retimed -register -original mips_core/rt_reg/r32_o[16] -translated mips_core/rt_reg/r32_o_16__Z
vif_set_sequential_verify -retimed -register -original mips_core/rt_reg/r32_o[17] -translated mips_core/rt_reg/r32_o_17__Z
vif_set_sequential_verify -retimed -register -original mips_core/rt_reg/r32_o[18] -translated mips_core/rt_reg/r32_o_18__Z
vif_set_sequential_verify -retimed -register -original mips_core/rt_reg/r32_o[19] -translated mips_core/rt_reg/r32_o_19__Z
vif_set_sequential_verify -retimed -register -original mips_core/rt_reg/r32_o[20] -translated mips_core/rt_reg/r32_o_20__Z
vif_set_sequential_verify -retimed -register -original mips_core/rt_reg/r32_o[21] -translated mips_core/rt_reg/r32_o_21__Z
vif_set_sequential_verify -retimed -register -original mips_core/rt_reg/r32_o[22] -translated mips_core/rt_reg/r32_o_22__Z
vif_set_sequential_verify -retimed -register -original mips_core/rt_reg/r32_o[23] -translated mips_core/rt_reg/r32_o_23__Z
vif_set_sequential_verify -retimed -register -original mips_core/rt_reg/r32_o[24] -translated mips_core/rt_reg/r32_o_24__Z
vif_set_sequential_verify -retimed -register -original mips_core/rt_reg/r32_o[25] -translated mips_core/rt_reg/r32_o_25__Z
vif_set_sequential_verify -retimed -register -original mips_core/rt_reg/r32_o[26] -translated mips_core/rt_reg/r32_o_26__Z
vif_set_sequential_verify -retimed -register -original mips_core/rt_reg/r32_o[27] -translated mips_core/rt_reg/r32_o_27__Z
vif_set_sequential_verify -retimed -register -original mips_core/rt_reg/r32_o[28] -translated mips_core/rt_reg/r32_o_28__Z
vif_set_sequential_verify -retimed -register -original mips_core/rt_reg/r32_o[29] -translated mips_core/rt_reg/r32_o_29__Z
vif_set_sequential_verify -retimed -register -original mips_core/rt_reg/r32_o[30] -translated mips_core/rt_reg/r32_o_30__Z
vif_set_sequential_verify -retimed -register -original mips_core/rt_reg/r32_o[31] -translated mips_core/rt_reg/r32_o_31__Z
vif_set_sequential_verify -retimed -register -original imips_dvc/iuart0/uart_rd_tak/rxq1 -translated imips_dvc/iuart0/uart_rd_tak/rxq1_Z
vif_set_sequential_verify -retimed -register -original imips_dvc/iuart0/rxd_rdy_hold_lw/q -translated imips_dvc/iuart0/rxd_rdy_hold_lw/q_Z
vif_set_sequential_verify -retimed -register -original imips_dvc/iuart0/uart_txd/txd -translated imips_dvc/iuart0/uart_txd/txd_Z
vif_set_sequential_verify -retimed -register -original imips_dvc/mips_tmr0/s_cntr[31] -translated imips_dvc/mips_tmr0/s_cntr_31__Z
vif_set_sequential_verify -retimed -register -original imips_dvc/mips_tmr0/s_cntr[30] -translated imips_dvc/mips_tmr0/s_cntr_30__Z
vif_set_sequential_verify -retimed -register -original imips_dvc/mips_tmr0/s_cntr[29] -translated imips_dvc/mips_tmr0/s_cntr_29__Z
vif_set_sequential_verify -retimed -register -original imips_dvc/mips_tmr0/s_cntr[28] -translated imips_dvc/mips_tmr0/s_cntr_28__Z
vif_set_sequential_verify -retimed -register -original imips_dvc/mips_tmr0/s_cntr[27] -translated imips_dvc/mips_tmr0/s_cntr_27__Z
vif_set_sequential_verify -retimed -register -original imips_dvc/mips_tmr0/s_cntr[26] -translated imips_dvc/mips_tmr0/s_cntr_26__Z
vif_set_sequential_verify -retimed -register -original imips_dvc/mips_tmr0/s_cntr[25] -translated imips_dvc/mips_tmr0/s_cntr_25__Z
vif_set_sequential_verify -retimed -register -original imips_dvc/mips_tmr0/s_cntr[24] -translated imips_dvc/mips_tmr0/s_cntr_24__Z
vif_set_sequential_verify -retimed -register -original imips_dvc/mips_tmr0/s_cntr[23] -translated imips_dvc/mips_tmr0/s_cntr_23__Z
vif_set_sequential_verify -retimed -register -original imips_dvc/mips_tmr0/s_cntr[22] -translated imips_dvc/mips_tmr0/s_cntr_22__Z
vif_set_sequential_verify -retimed -register -original imips_dvc/mips_tmr0/s_cntr[21] -translated imips_dvc/mips_tmr0/s_cntr_21__Z
vif_set_sequential_verify -retimed -register -original imips_dvc/mips_tmr0/s_cntr[20] -translated imips_dvc/mips_tmr0/s_cntr_20__Z
vif_set_sequential_verify -retimed -register -original imips_dvc/mips_tmr0/s_cntr[19] -translated imips_dvc/mips_tmr0/s_cntr_19__Z
vif_set_sequential_verify -retimed -register -original imips_dvc/mips_tmr0/s_cntr[18] -translated imips_dvc/mips_tmr0/s_cntr_18__Z
vif_set_sequential_verify -retimed -register -original imips_dvc/mips_tmr0/s_cntr[17] -translated imips_dvc/mips_tmr0/s_cntr_17__Z
vif_set_sequential_verify -retimed -register -original imips_dvc/mips_tmr0/s_cntr[16] -translated imips_dvc/mips_tmr0/s_cntr_16__Z
vif_set_sequential_verify -retimed -register -original imips_dvc/mips_tmr0/s_cntr[15] -translated imips_dvc/mips_tmr0/s_cntr_15__Z
vif_set_sequential_verify -retimed -register -original imips_dvc/mips_tmr0/s_cntr[14] -translated imips_dvc/mips_tmr0/s_cntr_14__Z
vif_set_sequential_verify -retimed -register -original imips_dvc/mips_tmr0/s_cntr[13] -translated imips_dvc/mips_tmr0/s_cntr_13__Z
vif_set_sequential_verify -retimed -register -original imips_dvc/mips_tmr0/s_cntr[12] -translated imips_dvc/mips_tmr0/s_cntr_12__Z
vif_set_sequential_verify -retimed -register -original imips_dvc/mips_tmr0/s_cntr[11] -translated imips_dvc/mips_tmr0/s_cntr_11__Z
vif_set_sequential_verify -retimed -register -original imips_dvc/mips_tmr0/s_cntr[10] -translated imips_dvc/mips_tmr0/s_cntr_10__Z
vif_set_sequential_verify -retimed -register -original imips_dvc/mips_tmr0/s_cntr[9] -translated imips_dvc/mips_tmr0/s_cntr_9__Z
vif_set_sequential_verify -retimed -register -original imips_dvc/mips_tmr0/s_cntr[8] -translated imips_dvc/mips_tmr0/s_cntr_8__Z
vif_set_sequential_verify -retimed -register -original imips_dvc/mips_tmr0/s_cntr[7] -translated imips_dvc/mips_tmr0/s_cntr_7__Z
vif_set_sequential_verify -retimed -register -original imips_dvc/mips_tmr0/s_cntr[6] -translated imips_dvc/mips_tmr0/s_cntr_6__Z
vif_set_sequential_verify -retimed -register -original imips_dvc/mips_tmr0/s_cntr[5] -translated imips_dvc/mips_tmr0/s_cntr_5__Z
vif_set_sequential_verify -retimed -register -original imips_dvc/mips_tmr0/s_cntr[4] -translated imips_dvc/mips_tmr0/s_cntr_4__Z
vif_set_sequential_verify -retimed -register -original imips_dvc/mips_tmr0/s_cntr[3] -translated imips_dvc/mips_tmr0/s_cntr_3__Z
vif_set_sequential_verify -retimed -register -original imips_dvc/mips_tmr0/s_cntr[2] -translated imips_dvc/mips_tmr0/s_cntr_2__Z
vif_set_sequential_verify -retimed -register -original imips_dvc/mips_tmr0/s_cntr[1] -translated imips_dvc/mips_tmr0/s_cntr_1__Z
vif_set_sequential_verify -retimed -register -original imips_dvc/mips_tmr0/s_cntr[0] -translated imips_dvc/mips_tmr0/s_cntr_0__Z
vif_set_sequential_verify -retimed -register -original imips_dvc/r_key1 -translated imips_dvc/r_key1_Z
vif_set_sequential_verify -retimed -register -original imips_dvc/r_key2 -translated imips_dvc/r_key2_Z
vif_set_sequential_verify -retimed -register -original imips_dvc/dout[0] -translated imips_dvc/dout_0__Z
vif_set_sequential_verify -retimed -register -original imips_dvc/dout[1] -translated imips_dvc/dout_1__Z
vif_set_sequential_verify -retimed -register -original imips_dvc/dout[2] -translated imips_dvc/dout_2__Z
vif_set_sequential_verify -retimed -register -original imips_dvc/dout[3] -translated imips_dvc/dout_3__Z
vif_set_sequential_verify -retimed -register -original imips_dvc/dout[4] -translated imips_dvc/dout_4__Z
vif_set_sequential_verify -retimed -register -original imips_dvc/dout[5] -translated imips_dvc/dout_5__Z
vif_set_sequential_verify -retimed -register -original imips_dvc/dout[6] -translated imips_dvc/dout_6__Z
vif_set_sequential_verify -retimed -register -original imips_dvc/dout[7] -translated imips_dvc/dout_7__Z
vif_set_sequential_verify -retimed -register -original imips_dvc/dout[8] -translated imips_dvc/dout_8__Z
vif_set_sequential_verify -retimed -register -original imips_dvc/dout[9] -translated imips_dvc/dout_9__Z
vif_set_sequential_verify -retimed -register -original imips_dvc/dout[10] -translated imips_dvc/dout_10__Z
vif_set_sequential_verify -retimed -register -original imips_dvc/dout[11] -translated imips_dvc/dout_11__Z
vif_set_sequential_verify -retimed -register -original imips_dvc/dout[12] -translated imips_dvc/dout_12__Z
vif_set_sequential_verify -retimed -register -original imips_dvc/dout[13] -translated imips_dvc/dout_13__Z
vif_set_sequential_verify -retimed -register -original imips_dvc/dout[14] -translated imips_dvc/dout_14__Z
vif_set_sequential_verify -retimed -register -original imips_dvc/dout[15] -translated imips_dvc/dout_15__Z
vif_set_sequential_verify -retimed -register -original imips_dvc/dout[16] -translated imips_dvc/dout_16__Z
vif_set_sequential_verify -retimed -register -original imips_dvc/dout[17] -translated imips_dvc/dout_17__Z
vif_set_sequential_verify -retimed -register -original imips_dvc/dout[18] -translated imips_dvc/dout_18__Z
vif_set_sequential_verify -retimed -register -original imips_dvc/dout[19] -translated imips_dvc/dout_19__Z
vif_set_sequential_verify -retimed -register -original imips_dvc/dout[20] -translated imips_dvc/dout_20__Z
vif_set_sequential_verify -retimed -register -original imips_dvc/dout[21] -translated imips_dvc/dout_21__Z
vif_set_sequential_verify -retimed -register -original imips_dvc/dout[22] -translated imips_dvc/dout_22__Z
vif_set_sequential_verify -retimed -register -original imips_dvc/dout[23] -translated imips_dvc/dout_23__Z
vif_set_sequential_verify -retimed -register -original imips_dvc/dout[24] -translated imips_dvc/dout_24__Z
vif_set_sequential_verify -retimed -register -original imips_dvc/dout[25] -translated imips_dvc/dout_25__Z
vif_set_sequential_verify -retimed -register -original imips_dvc/dout[26] -translated imips_dvc/dout_26__Z
vif_set_sequential_verify -retimed -register -original imips_dvc/dout[27] -translated imips_dvc/dout_27__Z
vif_set_sequential_verify -retimed -register -original imips_dvc/dout[28] -translated imips_dvc/dout_28__Z
vif_set_sequential_verify -retimed -register -original imips_dvc/dout[29] -translated imips_dvc/dout_29__Z
vif_set_sequential_verify -retimed -register -original imips_dvc/dout[30] -translated imips_dvc/dout_30__Z
vif_set_sequential_verify -retimed -register -original imips_dvc/dout[31] -translated imips_dvc/dout_31__Z
vif_set_sequential_verify -retimed -register -original imips_dvc/lcd_data[0] -translated imips_dvc/lcd_data_0__Z
vif_set_sequential_verify -retimed -register -original imips_dvc/lcd_data[1] -translated imips_dvc/lcd_data_1__Z
vif_set_sequential_verify -retimed -register -original imips_dvc/lcd_data[2] -translated imips_dvc/lcd_data_2__Z
vif_set_sequential_verify -retimed -register -original imips_dvc/lcd_data[3] -translated imips_dvc/lcd_data_3__Z
vif_set_sequential_verify -retimed -register -original imips_dvc/lcd_data[4] -translated imips_dvc/lcd_data_4__Z
vif_set_sequential_verify -retimed -register -original imips_dvc/lcd_data[5] -translated imips_dvc/lcd_data_5__Z
vif_set_sequential_verify -retimed -register -original imips_dvc/lcd_data[6] -translated imips_dvc/lcd_data_6__Z
vif_set_sequential_verify -retimed -register -original imips_dvc/lcd_data[7] -translated imips_dvc/lcd_data_7__Z
vif_set_sequential_verify -retimed -register -original imips_dvc/rr_key2 -translated imips_dvc/rr_key2_Z
vif_set_sequential_verify -retimed -register -original imips_dvc/rr_key1 -translated imips_dvc/rr_key1_Z

# Altera MAC annotations