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https://opencores.org/ocsvn/mips_16/mips_16/trunk
Subversion Repositories mips_16
[/] [mips_16/] [trunk/] [bench/] [ID_stage/] [ID_stage_tb_0.do] - Rev 2
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vlib work
vlog +incdir+../rtl ../rtl/ID_stage.v
vlog +incdir+../rtl ../bench/ID_stage/ID_stage_tb_0.v
vsim -t 1ps -novopt -lib work ID_stage_tb_0_v
view wave
add wave *
add wave /ID_stage_tb_0_v/uut/instruction_reg
view structure
view signals
run -all