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# Synplicity, Inc. constraint file

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# Clocks
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define_clock -name {clk}      -freq 40.000 -clockgroup clk_clkgroup
define_clock -name {pci_clk}  -freq 40.000 -clockgroup pci_clkgroup
define_clock -name {spw_clk}  -freq 100.000 -clockgroup spw_clkgroup
define_clock -name {spwclk}   -freq 100.000 -clockgroup spwclkgroup

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# Inputs/Outputs
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define_output_delay -disable     -default  14.00 -improve 0.00 -route 0.00 -ref clk:r
define_input_delay -disable      -default  20.00 -improve 0.00 -route 0.00 -ref clk:r
define_output_delay              -default  8.00 -improve 0.00 -route 0.00 -ref pci_clk:r
define_input_delay               -default  15.00 -improve 0.00 -route 0.00 -ref pci_clk:r
define_input_delay               {pci_rst}  0.00 -improve 0.00 -route 0.00 -ref pci_clk:r

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# Registers
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# Multicycle Path
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# False Path
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# Attributes
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define_global_attribute          syn_useioff {1}
define_attribute          {cpu.0.l3ft.u0.holdn} syn_maxfan {10000}
define_attribute          {spw.spwloop.0.sw0.rxclko} syn_maxfan {10000}
define_attribute          {spw.spwloop.0.sw0.txclko} syn_maxfan {10000}
define_attribute          {cpu.0.l3ft.u0} syn_hier {flatten}
define_global_attribute -disable syn_netlist_hierarchy {1}

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# Other Constraints
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#  Order of waveforms
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