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[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [boards/] [memec-v2-mb1000/] [v2mb1000.ucf] - Rev 2
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# User constrains file for the "Virtex-II V2MB1000 Development kit",
# the "P160 Communications module" and the "P160 Prototype module".
# There are described all of FPGA used pins. Some of nets are
# duplicated in many groups with different net names. If you need,
# you can change name of the nets.
#
# Roman Bartosinski <bartosr@centrum.cz>
# Revision 1.1, 2003-07-29
###################################################
# Main board - Virtex-II V2MB1000 Development kit #
###################################################
# DDR Memory 32MB - Address[12:0],Data[15:0],BS[1:0],LDM,UDM,LDQS,UDQS,CSn,RASn,CASn,WEn,CLKE,CLKn,CLK
NET "ddr_addr<0>" LOC = B18; # Address 0
NET "ddr_addr<1>" LOC = A18; # Address 1
NET "ddr_addr<2>" LOC = B17; # Address 2
NET "ddr_addr<3>" LOC = A17; # Address 3
NET "ddr_addr<4>" LOC = N17; # Address 4
NET "ddr_addr<5>" LOC = P18; # Address 5
NET "ddr_addr<6>" LOC = P17; # Address 6
NET "ddr_addr<7>" LOC = M18; # Address 7
NET "ddr_addr<8>" LOC = M19; # Address 8
NET "ddr_addr<9>" LOC = M20; # Address 9
NET "ddr_addr<10>" LOC = A19; # Address 10
NET "ddr_addr<11>" LOC = N18; # Address 11
NET "ddr_addr<12>" LOC = N20; # Address 12
NET "ddr_data<0>" LOC = Y21; # Data 0
NET "ddr_data<1>" LOC = Y22; # Data 1
NET "ddr_data<2>" LOC = W21; # Data 2
NET "ddr_data<3>" LOC = V21; # Data 3
NET "ddr_data<4>" LOC = V22; # Data 4
NET "ddr_data<5>" LOC = U21; # Data 5
NET "ddr_data<6>" LOC = U22; # Data 6
NET "ddr_data<7>" LOC = T21; # Data 7
NET "ddr_data<8>" LOC = R20; # Data 8
NET "ddr_data<9>" LOC = R19; # Data 9
NET "ddr_data<10>" LOC = T20; # Data 10
NET "ddr_data<11>" LOC = T19; # Data 11
NET "ddr_data<12>" LOC = U19; # Data 12
NET "ddr_data<13>" LOC = V20; # Data 13
NET "ddr_data<14>" LOC = V19; # Data 14
NET "ddr_data<15>" LOC = W20; # Data 15
NET "ddr_bs<0>" LOC = M21; # Bank Select 0
NET "ddr_bs<1>" LOC = B19; # Bank Select 1
NET "ddr_ldm" LOC = R21; # Low Write Mask
NET "ddr_udm" LOC = T22; # High Write Mask
NET "ddr_ldqs" LOC = P20; # Low Write/Read Data Strobe
NET "ddr_udqs" LOC = P19; # High Write/Read Data Strobe
NET "ddr_cs" LOC = N22; # Chip Select
NET "ddr_ras" LOC = N21; # Row Address Strobe
NET "ddr_cas" LOC = P21; # Column Adress Strobe
NET "ddr_we" LOC = R22; # Write Enable
NET "ddr_clk" LOC = D12; # Clock
NET "ddr_clkn" LOC = E12; # Clock
NET "ddr_cke" LOC = N19; # Clock Enable
NET "ddr_clk_fb LOC = F13; # Clock feed-back
# Clock generation - on-board oscillators 100Mhz and 24MHz
NET "clk_100" LOC = B11; # On-board 100 MHz Oscillator
NET "clk_24" LOC = A11; # On-board 24 MHz Oscillator
# Reset circuit - RESETn
NET "reset" LOC = B6 ; # FPGA_RESETn (push-button switch SW3)
# User 7-segment display (common cathode - active high)
# - A2 - - A1 -
# | | | |
# F2 B2 F2 B1
# | | | |
# - G2 - - G1 -
# | | | |
# E2 C2 E1 C1
# | | | |
# - D2 - - D1 -
NET "segm_lo<0>" LOC = D9 ; # 7-segment LED display1, Segment A
NET "segm_lo<1>" LOC = C9 ; # 7-segment LED display1, Segment B
NET "segm_lo<2>" LOC = F11; # 7-segment LED display1, Segment C
NET "segm_lo<3>" LOC = F9 ; # 7-segment LED display1, Segment D
NET "segm_lo<4>" LOC = F10; # 7-segment LED display1, Segment E
NET "segm_lo<5>" LOC = D10; # 7-segment LED display1, Segment F
NET "segm_lo<6>" LOC = C10; # 7-segment LED display1, Segment G
NET "segm_hi<0>" LOC = B9 ; # 7-segment LED display2, Segment A
NET "segm_hi<1>" LOC = A8 ; # 7-segment LED display2, Segment B
NET "segm_hi<2>" LOC = B8 ; # 7-segment LED display2, Segment C
NET "segm_hi<3>" LOC = E7 ; # 7-segment LED display2, Segment D
NET "segm_hi<4>" LOC = E8 ; # 7-segment LED display2, Segment E
NET "segm_hi<5>" LOC = E10; # 7-segment LED display2, Segment F
NET "segm_hi<6>" LOC = E9 ; # 7-segment LED display2, Segment G
# User LED (active high)
NET "led" LOC = A9 ; # User LED
# User push button switches (SW5, SW6)
NET "btn_1" LOC = D7 ; # User Push Button Switch Input 1 (SW5)
NET "btn_2" LOC = A6 ; # User Push Button Switch Input 2 (SW6)
# User DIP switch (SW2)
# They are sorted from left to right as DIP<0>..DIP<7>
NET "dip<0>" LOC = B4 ; # User Switch Input 1
NET "dip<1>" LOC = A4 ; # User Switch Input 2
NET "dip<2>" LOC = C4 ; # User Switch Input 3
NET "dip<3>" LOC = C5 ; # User Switch Input 4
NET "dip<4>" LOC = B5 ; # User Switch Input 5
NET "dip<5>" LOC = A5 ; # User Switch Input 6
NET "dip<6>" LOC = D6 ; # User Switch Input 7
NET "dip<7>" LOC = C6 ; # User Switch Input 8
# RS232 Port
NET "rs232_rxd" LOC = A7 ; # Received Data, RD to DB9 (pin 2) - From the PC side ( send data from FPGA )
NET "rs232_txd" LOC = B7 ; # Transmit Data, TD from DB9 (pin 3) -
# Virtex-II VBAT
NET "vbat" LOC = A21; # VBAT input pin - connected to 3.3V through the JP15
# LVDS Port Signals
# - Transmit port
NET "lvds_out_1n" LOC = H2 ; # Negative Data Transmit Bit 1 (J4 - pin 1)
NET "lvds_out_1p" LOC = H1 ; # Positive Data Transmit Bit 1 (J4 - pin 2)
NET "lvds_out_2n" LOC = J2 ; # Negative Data Transmit Bit 2 (J4 - pin 3)
NET "lvds_out_2p" LOC = J1 ; # Positive Data Transmit Bit 2 (J4 - pin 4)
NET "lvds_out_3n" LOC = K2 ; # Negative Data Transmit Bit 3 (J4 - pin 5)
NET "lvds_out_3p" LOC = K1 ; # Positive Data Transmit Bit 3 (J4 - pin 6)
NET "lvds_out_4n" LOC = E4 ; # Negative Data Transmit Bit 4 (J4 - pin 7)
NET "lvds_out_4p" LOC = E3 ; # Positive Data Transmit Bit 4 (J4 - pin 8)
NET "lvds_out_5n" LOC = F4 ; # Negative Data Transmit Bit 5 (J4 - pin 11)
NET "lvds_out_5p" LOC = F3 ; # Positive Data Transmit Bit 5 (J4 - pin 12)
NET "lvds_out_6n" LOC = G4 ; # Negative Data Transmit Bit 6 (J4 - pin 13)
NET "lvds_out_6p" LOC = G3 ; # Positive Data Transmit Bit 6 (J4 - pin 14)
NET "lvds_out_7n" LOC = H4 ; # Negative Data Transmit Bit 7 (J4 - pin 15)
NET "lvds_out_7p" LOC = H3 ; # Positive Data Transmit Bit 7 (J4 - pin 16)
NET "lvds_out_8n" LOC = J4 ; # Negative Data Transmit Bit 8 (J4 - pin 17)
NET "lvds_out_8p" LOC = J3 ; # Positive Data Transmit Bit 8 (J4 - pin 18)
NET "lvds_out_9n" LOC = K4 ; # Negative Data Transmit Bit 9 (J4 - pin 21)
NET "lvds_out_9p" LOC = K3 ; # Positive Data Transmit Bit 9 (J4 - pin 22)
NET "lvds_out_10n" LOC = L3 ; # Negative Data Transmit Bit 10 (J4 - pin 23)
NET "lvds_out_10p" LOC = L2 ; # Positive Data Transmit Bit 10 (J4 - pin 24)
NET "lvds_out_11n" LOC = L5 ; # Negative Data Transmit Bit 11 (J4 - pin 25)
NET "lvds_out_11p" LOC = L4 ; # Positive Data Transmit Bit 11 (J4 - pin 26)
NET "lvds_out_12n" LOC = E6 ; # Negative Data Transmit Bit 12 (J4 - pin 27)
NET "lvds_out_12p" LOC = E5 ; # Positive Data Transmit Bit 12 (J4 - pin 28)
NET "lvds_out_13n" LOC = F5 ; # Negative Data Transmit Bit 13 (J4 - pin 31)
NET "lvds_out_13p" LOC = G5 ; # Positive Data Transmit Bit 13 (J4 - pin 32)
NET "lvds_out_14n" LOC = H5 ; # Negative Data Transmit Bit 14 (J4 - pin 33)
NET "lvds_out_14p" LOC = J6 ; # Positive Data Transmit Bit 14 (J4 - pin 34)
NET "lvds_out_15n" LOC = J5 ; # Negative Data Transmit Bit 15 (J4 - pin 35)
NET "lvds_out_15p" LOC = K5 ; # Positive Data Transmit Bit 15 (J4 - pin 36)
NET "lvds_out_16n" LOC = K6 ; # Negative Data Transmit Bit 16 (J4 - pin 37)
NET "lvds_out_16p" LOC = L6 ; # Positive Data Transmit Bit 16 (J4 - pin 38)
# - Receive port
NET "lvds_in_1p" LOC = M2 ; # Positive Data Receive Bit 1 (J6 - pin 3)
NET "lvds_in_1n" LOC = M1 ; # Negative Data Receive Bit 1 (J6 - pin 4)
NET "lvds_in_2p" LOC = N2 ; # Positive Data Receive Bit 2 (J6 - pin 5)
NET "lvds_in_2n" LOC = N1 ; # Negative Data Receive Bit 2 (J6 - pin 6)
NET "lvds_in_3p" LOC = P2 ; # Positive Data Receive Bit 3 (J6 - pin 7)
NET "lvds_in_3n" LOC = P1 ; # Negative Data Receive Bit 3 (J6 - pin 8)
NET "lvds_in_4p" LOC = R2 ; # Positive Data Receive Bit 4 (J6 - pin 9)
NET "lvds_in_4n" LOC = R1 ; # Negative Data Receive Bit 4 (J6 - pin 10)
NET "lvds_in_5p" LOC = T2 ; # Positive Data Receive Bit 5 (J6 - pin 13)
NET "lvds_in_5n" LOC = T1 ; # Negative Data Receive Bit 5 (J6 - pin 14)
NET "lvds_in_6p" LOC = U2 ; # Positive Data Receive Bit 6 (J6 - pin 15)
NET "lvds_in_6n" LOC = U1 ; # Negative Data Receive Bit 6 (J6 - pin 16)
NET "lvds_in_7p" LOC = V2 ; # Positive Data Receive Bit 7 (J6 - pin 17)
NET "lvds_in_7n" LOC = V1 ; # Negative Data Receive Bit 7 (J6 - pin 18)
NET "lvds_in_8p" LOC = W2 ; # Positive Data Receive Bit 8 (J6 - pin 19)
NET "lvds_in_8n" LOC = W1 ; # Negative Data Receive Bit 8 (J6 - pin 20)
NET "lvds_in_9p" LOC = Y2 ; # Positive Data Receive Bit 9 (J6 - pin 23)
NET "lvds_in_9n" LOC = Y1 ; # Negative Data Receive Bit 9 (J6 - pin 24)
NET "lvds_in_10p" LOC = M6 ; # Positive Data Receive Bit 10 (J6 - pin 25)
NET "lvds_in_10n" LOC = M5 ; # Negative Data Receive Bit 10 (J6 - pin 26)
NET "lvds_in_11p" LOC = M4 ; # Positive Data Receive Bit 11 (J6 - pin 27)
NET "lvds_in_11n" LOC = M3 ; # Negative Data Receive Bit 11 (J6 - pin 28)
NET "lvds_in_12p" LOC = N4 ; # Positive Data Receive Bit 12 (J6 - pin 29)
NET "lvds_in_12n" LOC = N3 ; # Negative Data Receive Bit 12 (J6 - pin 30)
NET "lvds_in_13p" LOC = P4 ; # Positive Data Receive Bit 13 (J6 - pin 33)
NET "lvds_in_13n" LOC = P3 ; # Negative Data Receive Bit 13 (J6 - pin 34)
NET "lvds_in_14p" LOC = R4 ; # Positive Data Receive Bit 14 (J6 - pin 35)
NET "lvds_in_14n" LOC = R3 ; # Negative Data Receive Bit 14 (J6 - pin 36)
NET "lvds_in_15p" LOC = T4 ; # Positive Data Receive Bit 15 (J6 - pin 37)
NET "lvds_in_15n" LOC = T3 ; # Negative Data Receive Bit 15 (J6 - pin 38)
NET "lvds_in_16p" LOC = U4 ; # Positive Data Receive Bit 16 (J6 - pin 39)
NET "lvds_in_16n" LOC = U3 ; # Negative Data Receive Bit 16 (J6 - pin 40)
# - Transmit control port
NET "lvds_out_clkp" LOC = C1 ; # Positive Transmit Clock (J7 - pin 1)
NET "lvds_out_clkn" LOC = C2 ; # Negative Transmit Clock (J7 - pin 2)
NET "lvds_out_sclkp" LOC = D1 ; # Positive Transmit Status Clock (J7 - pin 5)
NET "lvds_out_sclkn" LOC = D2 ; # Negative Transmit Status Clock (J7 - pin 6)
NET "lvds_out_st_1p" LOC = E1 ; # Positive Transmit Status 1 (J7 - pin 9)
NET "lvds_out_st_1n" LOC = E2 ; # Negative Transmit Status 1 (J7 - pin 10)
NET "lvds_out_st_2p" LOC = F1 ; # Positive Transmit Status 2 (J7 - pin 11)
NET "lvds_out_st_2n" LOC = F2 ; # Negative Transmit Status 2 (J7 - pin 12)
NET "lvds_out_ctrlp" LOC = G1 ; # Positive Transmit Control (J7 - pin 13)
NET "lvds_out_ctrln" LOC = G2 ; # Negative Transmit Control (J7 - pin 14)
# - Receive control port
NET "lvds_in_ctrln" LOC = V3 ; # Negative Receive Control (J8 - pin 1)
NET "lvds_in_ctrlp" LOC = V4 ; # Positive Receive Control (J8 - pin 2)
NET "lvds_in_st_2n" LOC = N5 ; # Negative Receive Status 2 (J8 - pin 3)
NET "lvds_in_st_2p" LOC = N6 ; # Positive Receive Status 2 (J8 - pin 4)
NET "lvds_in_st_1n" LOC = P5 ; # Negative Receive Status 1 (J8 - pin 5)
NET "lvds_in_st_1p" LOC = P6 ; # Positive Receive Status 1 (J8 - pin 6)
NET "lvds_in_sclkn" LOC = W11; # Negative Receive Status Clock (J8 - pin 9)
NET "lvds_in_sclkp" LOC = V11; # Positive Receive Status Clock (J8 - pin 10)
NET "lvds_in_clkn" LOC = AA11; # Negative Receive Clock (J8 - pin 13)
NET "lvds_in_clkp" LOC = Y11; # Positive Receive Clock (J8 - pin 14)
# P160 Expansion Module Connectors
# JX1 User I/O Connector
NET "jx1_a1" LOC = C19; # JX1 pin A1 - TCK
NET "jx1_a3" LOC = B20; # JX1 pin A3 - TMS
NET "jx1_a9" LOC = K22; # JX1 pin A9 - LIOA9
NET "jx1_a11" LOC = J21; # JX1 pin A11 - LIOA11
NET "jx1_a13" LOC = G22; # JX1 pin A13 - LIOA13
NET "jx1_a15" LOC = F21; # JX1 pin A15 - LIOA15
NET "jx1_a17" LOC = D22; # JX1 pin A17 - LIOA17
NET "jx1_a19" LOC = C21; # JX1 pin A19 - LIOA19
NET "jx1_a21" LOC = L20; # JX1 pin A21 - LIOA21
NET "jx1_a23" LOC = K19; # JX1 pin A23 - LIOA23
NET "jx1_a25" LOC = H20; # JX1 pin A25 - LIOA25
NET "jx1_a27" LOC = G19; # JX1 pin A27 - LIOA27
NET "jx1_a29" LOC = F20; # JX1 pin A29 - LIOA29
NET "jx1_a31" LOC = F19; # JX1 pin A31 - LIOA31
NET "jx1_a33" LOC = D11; # JX1 pin A33 - LIOA33
NET "jx1_a35" LOC = C11; # JX1 pin A35 - LIOA35
NET "jx1_a37" LOC = C8 ; # JX1 pin A37 - LIOA37
NET "jx1_a39" LOC = D8 ; # JX1 pin A39 - LIOA39
NET "jx1_b1" LOC = V18; # JX1 pin B1 - FPGA.BITSTREAM
NET "jx1_b2" LOC = AB19; # JX1 pin B2 - SM.DOUT/BUSY
NET "jx1_b3" LOC = Y19; # JX1 pin B3 - FPGA.CCLK
NET "jx1_b4" LOC = AB20; # JX1 pin B4 - DONE
NET "jx1_b5" LOC = AA19; # JX1 pin B5 - INITn
NET "jx1_b6" LOC = A2 ; # JX1 pin B6 - PROGRAMn
NET "jx1_b8" LOC = L22; # JX1 pin B8 - LIOB8
NET "jx1_b9" LOC = L21; # JX1 pin B9 - LIOB9
NET "jx1_b10" LOC = K21; # JX1 pin B10 - LIOB10
NET "jx1_b11" LOC = J22; # JX1 pin B11 - LIOB11
NET "jx1_b12" LOC = H22; # JX1 pin B12 - LIOB12
NET "jx1_b13" LOC = H21; # JX1 pin B13 - LIOB13
NET "jx1_b14" LOC = G21; # JX1 pin B14 - LIOB14
NET "jx1_b15" LOC = F22; # JX1 pin B15 - LIOB15
NET "jx1_b16" LOC = E22; # JX1 pin B16 - LIOB16
NET "jx1_b17" LOC = E21; # JX1 pin B17 - LIOB17
NET "jx1_b18" LOC = D21; # JX1 pin B18 - LIOB18
NET "jx1_b19" LOC = C22; # JX1 pin B19 - LIOB19
NET "jx1_b20" LOC = L18; # JX1 pin B20 - LIOB20
NET "jx1_b21" LOC = L19; # JX1 pin B21 - LIOB21
NET "jx1_b22" LOC = K18; # JX1 pin B22 - LIOB22
NET "jx1_b23" LOC = K20; # JX1 pin B23 - LIOB23
NET "jx1_b24" LOC = J20; # JX1 pin B24 - LIOB24
NET "jx1_b25" LOC = J19; # JX1 pin B25 - LIOB25
NET "jx1_b26" LOC = H19; # JX1 pin B26 - LIOB26
NET "jx1_b27" LOC = G20; # JX1 pin B27 - LIOB27
NET "jx1_b28" LOC = E19; # JX1 pin B28 - LIOB28
NET "jx1_b29" LOC = E20; # JX1 pin B29 - LIOB29
NET "jx1_b30" LOC = L17; # JX1 pin B30 - LIOB30
NET "jx1_b31" LOC = K17; # JX1 pin B31 - LIOB31
NET "jx1_b32" LOC = J17; # JX1 pin B32 - LIOB32
NET "jx1_b33" LOC = J18; # JX1 pin B33 - LIOB33
NET "jx1_b34" LOC = H18; # JX1 pin B34 - LIOB34
NET "jx1_b35" LOC = G18; # JX1 pin B35 - LIOB35
NET "jx1_b36" LOC = F18; # JX1 pin B36 - LIOB36
NET "jx1_b37" LOC = E18; # JX1 pin B37 - LIOB37
NET "jx1_b38" LOC = E11; # JX1 pin B38 - LIOB38
NET "jx1_b39" LOC = A10; # JX1 pin B39 - LIOB39
NET "jx1_b40" LOC = B10; # JX1 pin B40 - LIOB40
# JX2 User I/O Connector
NET "jx2_a1" LOC = AB10; # JX2 pin A1 - RIOA1
NET "jx2_a2" LOC = AA16; # JX2 pin A2 - RIOA2
NET "jx2_a3" LOC = AA17; # JX2 pin A3 - RIOA3
NET "jx2_a4" LOC = AB16; # JX2 pin A4 - RIOA4
NET "jx2_a5" LOC = AB17; # JX2 pin A5 - RIOA5
NET "jx2_a6" LOC = AA15; # JX2 pin A6 - RIOA6
NET "jx2_a7" LOC = W17; # JX2 pin A7 - RIOA7
NET "jx2_a8" LOC = AB15; # JX2 pin A8 - RIOA8
NET "jx2_a9" LOC = Y17; # JX2 pin A9 - RIOA9
NET "jx2_a10" LOC = AA14; # JX2 pin A10 - RIOA10
NET "jx2_a11" LOC = W16; # JX2 pin A11 - RIOA11
NET "jx2_a12" LOC = AB14; # JX2 pin A12 - RIOA12
NET "jx2_a13" LOC = Y16; # JX2 pin A13 - RIOA13
NET "jx2_a14" LOC = AA13; # JX2 pin A14 - RIOA14
NET "jx2_a15" LOC = V16; # JX2 pin A15 - RIOA15
NET "jx2_a16" LOC = AB13; # JX2 pin A16 - RIOA16
NET "jx2_a17" LOC = W15; # JX2 pin A17 - RIOA17
NET "jx2_a18" LOC = AA12; # JX2 pin A18 - RIOA18
NET "jx2_a19" LOC = V14; # JX2 pin A19 - RIOA19
NET "jx2_a20" LOC = AB12; # JX2 pin A20 - RIOA20
NET "jx2_a21" LOC = U14; # JX2 pin A21 - RIOA21
NET "jx2_a22" LOC = AB9 ; # JX2 pin A22 - RIOA22
NET "jx2_a23" LOC = U13; # JX2 pin A23 - RIOA23
NET "jx2_a24" LOC = AA9 ; # JX2 pin A24 - RIOA24
NET "jx2_a25" LOC = U12; # JX2 pin A25 - RIOA25
NET "jx2_a26" LOC = AB8 ; # JX2 pin A26 - RIOA26
NET "jx2_a27" LOC = U11; # JX2 pin A27 - RIOA27
NET "jx2_a28" LOC = AA8 ; # JX2 pin A28 - RIOA28
NET "jx2_a29" LOC = U10; # JX2 pin A29 - RIOA29
NET "jx2_a30" LOC = AB7 ; # JX2 pin A30 - RIOA30
NET "jx2_a31" LOC = U9 ; # JX2 pin A31 - RIOA31
NET "jx2_a32" LOC = AA7 ; # JX2 pin A32 - RIOA32
NET "jx2_a33" LOC = V9 ; # JX2 pin A33 - RIOA33
NET "jx2_a34" LOC = AB6 ; # JX2 pin A34 - RIOA34
NET "jx2_a35" LOC = V8 ; # JX2 pin A35 - RIOA35
NET "jx2_a36" LOC = AA6 ; # JX2 pin A36 - RIOA36
NET "jx2_a37" LOC = V7 ; # JX2 pin A37 - RIOA37
NET "jx2_a38" LOC = AB5 ; # JX2 pin A38 - RIOA38
NET "jx2_a39" LOC = V6 ; # JX2 pin A39 - RIOA39
NET "jx2_a40" LOC = AA5 ; # JX2 pin A40 - RIOA40
NET "jx2_b2" LOC = Y15; # JX2 pin B2 - RIOB2
NET "jx2_b4" LOC = W14; # JX2 pin B4 - RIOB4
NET "jx2_b6" LOC = Y14; # JX2 pin B6 - RIOB6
NET "jx2_b8" LOC = W13; # JX2 pin B8 - RIOB8
NET "jx2_b10" LOC = Y13; # JX2 pin B10 - RIOB10
NET "jx2_b12" LOC = V13; # JX2 pin B12 - RIOB12
NET "jx2_b14" LOC = Y12; # JX2 pin B14 - RIOB14
NET "jx2_b16" LOC = W12; # JX2 pin B16 - RIOB16
NET "jx2_b18" LOC = V12; # JX2 pin B18 - RIOB18
NET "jx2_b20" LOC = V10; # JX2 pin B20 - RIOB20
NET "jx2_b22" LOC = Y10; # JX2 pin B22 - RIOB22
NET "jx2_b24" LOC = W10; # JX2 pin B24 - RIOB24
NET "jx2_b26" LOC = Y9 ; # JX2 pin B26 - RIOB26
NET "jx2_b28" LOC = W9 ; # JX2 pin B28 - RIOB28
NET "jx2_b30" LOC = Y8 ; # JX2 pin B30 - RIOB30
NET "jx2_b32" LOC = W8 ; # JX2 pin B32 - RIOB32
NET "jx2_b34" LOC = Y7 ; # JX2 pin B34 - RIOB34
NET "jx2_b36" LOC = W7 ; # JX2 pin B36 - RIOB36
NET "jx2_b38" LOC = Y6 ; # JX2 pin B38 - RIOB38
NET "jx2_b40" LOC = W6 ; # JX2 pin B40 - RIOB40
##############################################################
# P160 Prototype module - Virtex-II V2MB1000 Development kit #
##############################################################
# J3 Connector
#"j3_1" - Vin
#"j3_2" - 3.3V
#"j3_3" - 2.5V
#"j3_4" - GND
NET "j3_5" LOC = AB10; # J3 pin 5 - RIOA1
#"j3_6" - NC
NET "j3_7" LOC = AA16; # J3 pin 7 - RIOA2
NET "j3_8" LOC = L22; # J3 pin 8 - LIOB8
NET "j3_9" LOC = L21; # J3 pin 9 - LIOB9
NET "j3_10" LOC = K21; # J3 pin 10 - LIOB10
NET "j3_11" LOC = J22; # J3 pin 11 - LIOB11
NET "j3_12" LOC = H22; # J3 pin 12 - LIOB12
NET "j3_13" LOC = H21; # J3 pin 13 - LIOB13
NET "j3_14" LOC = G21; # J3 pin 14 - LIOB14
NET "j3_15" LOC = F22; # J3 pin 15 - LIOB15
NET "j3_16" LOC = E22; # J3 pin 16 - LIOB16
NET "j3_17" LOC = E21; # J3 pin 17 - LIOB17
NET "j3_18" LOC = D21; # J3 pin 18 - LIOB18
NET "j3_19" LOC = C22; # J3 pin 19 - LIOB19
NET "j3_20" LOC = L18; # J3 pin 20 - LIOB20
NET "j3_21" LOC = L19; # J3 pin 21 - LIOB21
NET "j3_22" LOC = K18; # J3 pin 22 - LIOB22
NET "j3_23" LOC = K20; # J3 pin 23 - LIOB23
NET "j3_24" LOC = J20; # J3 pin 24 - LIOB24
NET "j3_25" LOC = J19; # J3 pin 25 - LIOB25
NET "j3_26" LOC = H19; # J3 pin 26 - LIOB26
NET "j3_27" LOC = G20; # J3 pin 27 - LIOB27
NET "j3_28" LOC = E19; # J3 pin 28 - LIOB28
NET "j3_29" LOC = E20; # J3 pin 29 - LIOB29
NET "j3_30" LOC = L17; # J3 pin 30 - LIOB30
NET "j3_31" LOC = K17; # J3 pin 31 - LIOB31
NET "j3_32" LOC = J17; # J3 pin 32 - LIOB32
NET "j3_33" LOC = J18; # J3 pin 33 - LIOB33
NET "j3_34" LOC = H18; # J3 pin 34 - LIOB34
NET "j3_35" LOC = G18; # J3 pin 35 - LIOB35
NET "j3_36" LOC = F18; # J3 pin 36 - LIOB36
NET "j3_37" LOC = E18; # J3 pin 37 - LIOB37
NET "j3_38" LOC = E11; # J3 pin 38 - LIOB38
NET "j3_39" LOC = A10; # J3 pin 39 - LIOB39
NET "j3_40" LOC = B10; # J3 pin 40 - LIOB40
# J4 Connector
#"j4_1" - Vin
#"j4_2" - 3.3V
#"j4_3" - 2.5V
NET "j4_4" LOC = Y15; # J4 pin 4 - RIOB2
NET "j4_5" LOC = C19; # J4 pin 5 - TCK
NET "j4_6" LOC = K22; # J4 pin 6 - LIOA9
#"j4_7" - TDO
NET "j4_8" LOC = J21; # J4 pin 8 - LIOA11
#"j4_9" - TDI
NET "j4_10" LOC = G22; # J4 pin 10 - LIOA13
NET "j4_11" LOC = B20; # J4 pin 11 - TMS
NET "j4_12" LOC = F21; # J4 pin 12 - LIOA15
NET "j4_13" LOC = V18; # J4 pin 13 - FPGA.BITSTREAM
NET "j4_14" LOC = D22; # J4 pin 14 - LIOA17
NET "j4_15" LOC = AB19; # J4 pin 15 - SM.DOUT/BUSY
NET "j4_16" LOC = C21; # J4 pin 16 - LIOA19
NET "j4_17" LOC = Y19; # J4 pin 17 - FPGA.CCLK
NET "j4_18" LOC = L20; # J4 pin 18 - LIOA21
NET "j4_19" LOC = AB20; # J4 pin 19 - DONE
NET "j4_20" LOC = K19; # J4 pin 20 - LIOA23
NET "j4_21" LOC = AA19; # J4 pin 21 - INITn
NET "j4_22" LOC = H20; # J4 pin 22 - LIOA25
NET "j4_23" LOC = A2 ; # J4 pin 23 - PROGRAMn
NET "j4_24" LOC = G19; # J4 pin 24 - LIOA27
#"j4_25" - GND
NET "j4_26" LOC = F20; # J4 pin 26 - LIOA29
#"j4_27" - GND
NET "j4_28" LOC = F19; # J4 pin 28 - LIOA31
#"j4_29" - GND
NET "j4_30" LOC = D11; # J4 pin 30 - LIOA33
#"j4_31" - GND
NET "j4_32" LOC = C11; # J4 pin 32 - LIOA35
#"j4_33" - GND
NET "j4_34" LOC = C8 ; # J4 pin 34 - LIOA37
#"j4_35" - GND
NET "j4_36" LOC = D8 ; # J4 pin 36 - LIOA39
#"j4_37" - GND
NET "j4_38" LOC = V6 ; # J4 pin 38 - RIOA39
#"j4_39" - GND
NET "j4_40" LOC = AA5 ; # J4 pin 40 - RIOA40
# J5 Connector
#"j5_1" - Vin
#"j5_2" - 3.3V
#"j5_3" - 2.5V
NET "j5_4" LOC = W14; # J5 pin 4 - RIOB4
#"j5_5" - NC
NET "j5_6" LOC = Y14; # J5 pin 6 - RIOB6
#"j5_7" - JTAG_LOOPBACK
NET "j5_8" LOC = W13; # J5 pin 8 - RIOB8
#"j5_9" - JTAG_LOOPBACK
NET "j5_10" LOC = Y13; # J5 pin 10 - RIOB10
#"j5_11" - NC
NET "j5_12" LOC = V13; # J5 pin 12 - RIOB12
#"j5_13" - NC
NET "j5_14" LOC = Y12; # J5 pin 14 - RIOB14
#"j5_15" - NC
NET "j5_16" LOC = W12; # J5 pin 16 - RIOB16
#"j5_17" - NC
NET "j5_18" LOC = V12; # J5 pin 18 - RIOB18
#"j5_19" - NC
NET "j5_20" LOC = V10; # J5 pin 20 - RIOB20
#"j5_21" - NC
NET "j5_22" LOC = Y10; # J5 pin 22 - RIOB22
#"j5_23" - NC
NET "j5_24" LOC = W10; # J5 pin 24 - RIOB24
#"j5_25" - GND
NET "j5_26" LOC = Y9 ; # J5 pin 26 - RIOB26
#"j5_27" - GND
NET "j5_28" LOC = W9 ; # J5 pin 28 - RIOB28
#"j5_29" - GND
NET "j5_30" LOC = Y8 ; # J5 pin 30 - RIOB30
#"j5_31" - GND
NET "j5_32" LOC = W8 ; # J5 pin 32 - RIOB32
#"j5_33" - GND
NET "j5_34" LOC = Y7 ; # J5 pin 34 - RIOB34
#"j5_35" - GND
NET "j5_36" LOC = W7 ; # J5 pin 36 - RIOB36
#"j5_37" - GND
NET "j5_38" LOC = Y6 ; # J5 pin 38 - RIOB38
#"j5_39" - GND
NET "j5_40" LOC = W6 ; # J5 pin 40 - RIOB40
# J6 Connector
#"j6_1" - Vin
#"j6_2" - 3.3V
#"j6_3" - 2.5V
#"j6_4" - GND
NET "j6_5" LOC = AB16; # J6 pin 5 - RIOA4
NET "j6_6" LOC = AA17; # J6 pin 6 - RIOA3 - User LED
NET "j6_7" LOC = AA15; # J6 pin 7 - RIOA6
NET "j6_8" LOC = AB17; # J6 pin 8 - RIOA5
NET "j6_9" LOC = AB15; # J6 pin 9 - RIOA8
NET "j6_10" LOC = W17; # J6 pin 10 - RIOA7
NET "j6_11" LOC = AA14; # J6 pin 11 - RIOA10
NET "j6_12" LOC = Y17; # J6 pin 12 - RIOA9
NET "j6_13" LOC = AB14; # J6 pin 13 - RIOA12
NET "j6_14" LOC = W16; # J6 pin 14 - RIOA11
NET "j6_15" LOC = AA13; # J6 pin 15 - RIOA14
NET "j6_16" LOC = Y16; # J6 pin 16 - RIOA13
NET "j6_17" LOC = AB13; # J6 pin 17 - RIOA16
NET "j6_18" LOC = V16; # J6 pin 18 - RIOA15
NET "j6_19" LOC = AA12; # J6 pin 19 - RIOA18
NET "j6_20" LOC = W15; # J6 pin 20 - RIOA17
NET "j6_21" LOC = AB12; # J6 pin 21 - RIOA20
NET "j6_22" LOC = V14; # J6 pin 22 - RIOA19
NET "j6_23" LOC = AB9 ; # J6 pin 23 - RIOA22
NET "j6_24" LOC = U14; # J6 pin 24 - RIOA21
NET "j6_25" LOC = AA9 ; # J6 pin 25 - RIOA24
NET "j6_26" LOC = U13; # J6 pin 26 - RIOA23
NET "j6_27" LOC = AB8 ; # J6 pin 27 - RIOA26
NET "j6_28" LOC = U12; # J6 pin 28 - RIOA25
NET "j6_29" LOC = AA8 ; # J6 pin 29 - RIOA28
NET "j6_30" LOC = U11; # J6 pin 30 - RIOA27
NET "j6_31" LOC = AB7 ; # J6 pin 31 - RIOA30
NET "j6_32" LOC = U10; # J6 pin 32 - RIOA29
NET "j6_33" LOC = AA7 ; # J6 pin 33 - RIOA32
NET "j6_34" LOC = U9 ; # J6 pin 34 - RIOA31
NET "j6_35" LOC = AB6 ; # J6 pin 35 - RIOA34
NET "j6_36" LOC = V9 ; # J6 pin 36 - RIOA33
NET "j6_37" LOC = AA6 ; # J6 pin 37 - RIOA36
NET "j6_38" LOC = V8 ; # J6 pin 38 - RIOA35
NET "j6_39" LOC = AB5 ; # J6 pin 39 - RIOA38
NET "j6_40" LOC = V7 ; # J6 pin 40 - RIOA37
###################################################################
# P160 Communications module - Virtex-II V2MB1000 Development kit #
###################################################################
# 10/100 Ethernet
NET "eth_rst" LOC = K17; # JX1 pin B31 - LIOB31 - ETH_PHY_RESETn
NET "eth_mdio" LOC = G22; # JX1 pin A13 - LIOA13 - ETH_MDIO
NET "eth_mdc" LOC = G21; # JX1 pin B14 - LIOB14 - ETH_MDC
NET "eth_col" LOC = J20; # JX1 pin B24 - LIOB24 - ETH_COL
NET "eth_crs" LOC = J19; # JX1 pin B25 - LIOB25 - ETH_CRS
NET "eth_txd<0>" LOC = L20; # JX1 pin A21 - LIOA21 - ETH_TXD0
NET "eth_txd<1>" LOC = K18; # JX1 pin B22 - LIOB22 - ETH_TXD1
NET "eth_txd<2>" LOC = K20; # JX1 pin B23 - LIOB23 - ETH_TXD2
NET "eth_txd<3>" LOC = K19; # JX1 pin A23 - LIOA23 - ETH_TDX3
NET "eth_txc" LOC = C11; # JX1 pin A35 - LIOA35 - ETH_TXC
NET "eth_txer" LOC = C21; # JX1 pin A19 - LIOA19 - ETH_TXER
NET "eth_txen" LOC = L19; # JX1 pin B21 - LIOB21 - ETH_TXEN
NET "eth_rxd<0>" LOC = E21; # JX1 pin B17 - LIOB17 - ETH_RXD0
NET "eth_rxd<1>" LOC = E22; # JX1 pin B16 - LIOB16 - ETH_RXD1
NET "eth_rxd<2>" LOC = F21; # JX1 pin A15 - LIOA15 - ETH_RXD2
NET "eth_rxd<3>" LOC = F22; # JX1 pin B15 - LIOB15 - ETH_RXD3
NET "eth_rxc" LOC = D11; # JX1 pin A33 - LIOA33 - ETH_RXC
NET "eth_rxer" LOC = C22; # JX1 pin B19 - LIOB19 - ETH_RXER
NET "eth_rxdv" LOC = D22; # JX1 pin A17 - LIOA17 - ETH_RXDV
# USB Port
NET "usb_vpo" LOC = L22; # JX1 pin B8 - LIOB8 - USB_VPO
NET "usb_vmo" LOC = L21; # JX1 pin B9 - LIOB9 - USB_VMO
NET "usb_oe" LOC = J21; # JX1 pin A11 - LIOA11 - USB_OEn
NET "usb_rcv" LOC = J22; # JX1 pin B11 - LIOB11 - USB_RCV
NET "usb_vp" LOC = K21; # JX1 pin B10 - LIOB10 - USB_VP
NET "usb_vm" LOC = K22; # JX1 pin A9 - LIOA9 - USB_VM
# RS232 Port
NET "rs232_2_rx" LOC = H21; # JX1 pin B13 - LIOB13 - RS232_RX (to JP5 pin 2)
NET "rs232_2_tx" LOC = H22; # JX1 pin B12 - LIOB12 - RS232_TX (from JP5 pin 3)
# I2C Port
NET "i2c_data" LOC = J17; # JX1 pin B32 - LIOB32 - I2C_DATA (JP6 pin 1)
NET "i2c_clk" LOC = J18; # JX1 pin B33 - LIOB33 - I2C_CLK (JP6 pin 2)
# SPI Port
NET "spi_clk" LOC = F18; # JX1 pin B36 - LIOB36 - SPI_CLK (JP4 pin 1)
NET "spi_out" LOC = H18; # JX1 pin B34 - LIOB34 - SPI_OUT (JP4 pin 2)
NET "spi_in" LOC = G18; # JX1 pin B35 - LIOB35 - SPI_IN (JP4 pin 3)
# FLASH and SRAM
NET "addr<0>" LOC = W8 ; # JX2 pin B32 - RIOB32 - A0
NET "addr<1>" LOC = AB6 ; # JX2 pin A34 - RIOA34 - A1
NET "addr<2>" LOC = V8 ; # JX2 pin A35 - RIOA35 - A2
NET "addr<3>" LOC = W7 ; # JX2 pin B36 - RIOB36 - A3
NET "addr<4>" LOC = V9 ; # JX2 pin A33 - RIOA33 - A4
NET "addr<5>" LOC = AA6 ; # JX2 pin A36 - RIOA36 - A5
NET "addr<6>" LOC = V7 ; # JX2 pin A37 - RIOA37 - A6
NET "addr<7>" LOC = AB5 ; # JX2 pin A38 - RIOA38 - A7
NET "addr<8>" LOC = AB10; # JX2 pin A1 - RIOA1 - A8
NET "addr<9>" LOC = AA17; # JX2 pin A3 - RIOA3 - A9
NET "addr<10>" LOC = Y14; # JX2 pin B6 - RIOB6 - A10
NET "addr<11>" LOC = Y15; # JX2 pin B2 - RIOB2 - A11
NET "addr<12>" LOC = AB16; # JX2 pin A4 - RIOA4 - A12
NET "addr<13>" LOC = AB17; # JX2 pin A5 - RIOA5 - A13
NET "addr<14>" LOC = AB15; # JX2 pin A8 - RIOA8 - A14
NET "addr<15>" LOC = W14; # JX2 pin B4 - RIOB4 - A15
NET "addr<16>" LOC = W13; # JX2 pin B8 - RIOB8 - A16
NET "addr<17>" LOC = Y7 ; # JX2 pin B34 - RIOB34 - A17
NET "addr<18>" LOC = Y6 ; # JX2 pin B38 - RIOB38 - A18
NET "addr<19>" LOC = AA16; # JX2 pin A2 - RIOA2 - A19
NET "addr<20>" LOC = W6 ; # JX2 pin B40 - RIOB40 - A20
NET "addr<21>" LOC = AA15; # JX2 pin A6 - RIOA6 - A21
NET "addr<22>" LOC = W17; # JX2 pin A7 - RIOA7 - A22
NET "data<0>" LOC = AA12; # JX2 pin A18 - RIOA18 - D0
NET "data<1>" LOC = U14; # JX2 pin A21 - RIOA21 - D1
NET "data<2>" LOC = W15; # JX2 pin A17 - RIOA17 - D2
NET "data<3>" LOC = Y12; # JX2 pin B14 - RIOB14 - D3
NET "data<4>" LOC = Y16; # JX2 pin A13 - RIOA13 - D4
NET "data<5>" LOC = AA13; # JX2 pin A14 - RIOA14 - D5
NET "data<6>" LOC = Y17; # JX2 pin A9 - RIOA9 - D6
NET "data<7>" LOC = W16; # JX2 pin A11 - RIOA11 - D7
NET "data<8>" LOC = V12; # JX2 pin B18 - RIOB18 - D8
NET "data<9>" LOC = AB13; # JX2 pin A16 - RIOA16 - D9
NET "data<10>" LOC = W12; # JX2 pin B16 - RIOB16 - D10
NET "data<11>" LOC = V16; # JX2 pin A15 - RIOA15 - D11
NET "data<12>" LOC = AB14; # JX2 pin A12 - RIOA12 - D12
NET "data<13>" LOC = Y13; # JX2 pin B10 - RIOB10 - D13
NET "data<14>" LOC = V13; # JX2 pin B12 - RIOB12 - D14
NET "data<15>" LOC = AA14; # JX2 pin A10 - RIOA10 - D15
NET "data<16>" LOC = Y8 ; # JX2 pin B30 - RIOB30 - D16
NET "data<17>" LOC = AA7 ; # JX2 pin A32 - RIOA32 - D17
NET "data<18>" LOC = W9 ; # JX2 pin B28 - RIOB28 - D18
NET "data<19>" LOC = U11; # JX2 pin A27 - RIOA27 - D19
NET "data<20>" LOC = Y9 ; # JX2 pin B26 - RIOB26 - D20
NET "data<21>" LOC = AB8 ; # JX2 pin A26 - RIOA26 - D21
NET "data<22>" LOC = AB9 ; # JX2 pin A22 - RIOA22 - D22
NET "data<23>" LOC = U13; # JX2 pin A23 - RIOA23 - D23
NET "data<24>" LOC = AB7 ; # JX2 pin A30 - RIOA30 - D24
NET "data<25>" LOC = U9 ; # JX2 pin A31 - RIOA31 - D25
NET "data<26>" LOC = U10; # JX2 pin A29 - RIOA29 - D26
NET "data<27>" LOC = AA8 ; # JX2 pin A28 - RIOA28 - D27
NET "data<28>" LOC = U12; # JX2 pin A25 - RIOA25 - D28
NET "data<29>" LOC = AA9 ; # JX2 pin A24 - RIOA24 - D29
NET "data<30>" LOC = W10; # JX2 pin B24 - RIOB24 - D30
NET "data<31>" LOC = Y10; # JX2 pin B22 - RIOB22 - D31
NET "mem_ce1s" LOC = AB12; # JX2 pin A20 - RIOA20 - MEM.CE1Sn
NET "mem_cef" LOC = V10; # JX2 pin B20 - RIOB20 - MEM.CEFn
NET "mem_oe" LOC = V14; # JX2 pin A19 - RIOA19 - MEM.OEn
NET "mem_we" LOC = AA5 ; # JX2 pin A40 - RIOA40 - MEM.WEn
NET "mem_rdy" LOC = V6 ; # JX2 pin A39 - RIOA39 - MEM.RY/BY ???
NET "mem_rst" LOC = E18; # JX1 pin B37 - LIOB37 - MEM_RESETn
NET "mem_blb" LOC = H19; # JX1 pin B26 - LIOB26 - MEM.BLBn
NET "mem_bub" LOC = G20; # JX1 pin B27 - LIOB27 - MEM.BUBn
NET "mem_alb" LOC = H20; # JX1 pin A25 - LIOA25 - MEM.ALBn
NET "mem_aub" LOC = G19; # JX1 pin A27 - LIOA27 - MEM.AUBn
# PS/2 Keybord Interface
NET "ps2_data" LOC = F20; # JX1 pin A29 - LIOA29 - PLD_KB_DATA (JP3 pin 1)
NET "ps2_clk" LOC = F19; # JX1 pin A31 - LIOA31 - PLD_KB_CLK (JP3 pin 5)
# LCD Interface
NET "data<0>" LOC = AA12; # JX2 pin A18 - RIOA18 - D0 (JP12 pin 8)
NET "data<1>" LOC = U14; # JX2 pin A21 - RIOA21 - D1 (JP12 pin 7)
NET "data<2>" LOC = W15; # JX2 pin A17 - RIOA17 - D2 (JP12 pin 6)
NET "data<3>" LOC = Y12; # JX2 pin B14 - RIOB14 - D3 (JP12 pin 5)
NET "data<4>" LOC = Y16; # JX2 pin A13 - RIOA13 - D4 (JP12 pin 4)
NET "data<5>" LOC = AA13; # JX2 pin A14 - RIOA14 - D5 (JP12 pin 3)
NET "data<6>" LOC = Y17; # JX2 pin A9 - RIOA9 - D6 (JP12 pin 2)
NET "data<7>" LOC = W16; # JX2 pin A11 - RIOA11 - D7 (JP12 pin 1)
NET "lcd_en" LOC = E19; # JX1 pin B28 - LIOB28 - PLD_LCD_EN (JP12 pin 9)
NET "lcd_rs" LOC = E20; # JX1 pin B29 - LIOB29 - PLD_LCD_RS (JP12 pin 11)
NET "lcd_rw" LOC = L17; # JX1 pin B30 - LIOB30 - PLD_LCD_R/Wn (JP12 pin 10)
# ??? CoolRunner CPLD ???
NET "pld_clk0" LOC = A10; # JX1 pin B39 - LIOB39 - PLD_CLK2
NET "pld_clk2" LOC = B10; # JX1 pin B40 - LIOB40 - PLD_CLK0