OpenCores
URL https://opencores.org/ocsvn/mips_enhanced/mips_enhanced/trunk

Subversion Repositories mips_enhanced

[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [designs/] [leon3-asic/] [Makefile] - Rev 2

Compare with Previous | Blame | View Log

GRLIB=../..
TOP=leon3mp
BOARD=gr-cpci-xc4v
include $(GRLIB)/boards/$(BOARD)/Makefile.inc
DEVICE=$(PART)-$(PACKAGE)$(SPEED)
UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf
QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
EFFORT=std
XSTOPT=
VHDLSYNFILES=config.vhd ahbrom.vhd \
        leon3core.vhd core.vhd pads.vhd leon3mp.vhd

VHDLSIMFILES=testbench.vhd
SIMTOP=testbench
SDCFILE=$(GRLIB)/boards/$(BOARD)/default.sdc
BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut
CLEAN=soft-clean
DCSCRIPT=ut025crh.tcl

TECHLIBS = nextreme virage atc18 artisan virage90 tsmc90 umc18 cust1
LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
        openchip gleichmann gsi spansion
DIRSKIP = b1553 pcif leon2 leon2ft 
        
FILESKIP =


include $(GRLIB)/bin/Makefile
include $(GRLIB)/software/leon3/Makefile


##################  project specific targets ##########################

Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.