Subversion Repositories mips_enhanced

# ==== Clock inputs (CLK) ====
NET "clk_50mhz" LOC = "C9" | IOSTANDARD = LVCMOS33 ;
#NET "clk_67mhz" LOC = "B8" | IOSTANDARD = LVCMOS33 ;
NET "clk_50mhz" PERIOD = 20ns HIGH 40%;

NET erx_clk PERIOD = 40.000 ;
OFFSET = IN : 10.000 : BEFORE erx_clk ;
NET etx_clk PERIOD = 40.000 ;
OFFSET = OUT : 20.000 : AFTER etx_clk ;
OFFSET = IN : 8.000 : BEFORE etx_clk ;

NET "clkm"              TNM_NET = "clkm";
NET "clkml"             TNM_NET = "clkml";
TIMESPEC "TS_clkm_clkml" = FROM "clkm" TO "clkml" TIG;
TIMESPEC "TS_clkml_clkm" = FROM "clkml" TO "clkm" TIG;
NET "lock"  TIG;

#NET "ddr_clk_fb" TNM_NET = "ddr_clk_fb";
#TIMESPEC "TS_ddr_clk_fb" = PERIOD "ddr_clk_fb" 10.00 ns HIGH 50 %;


INST "ddrsp0.ddrc/ddr_phy0/ddr_phy0/xc3se.ddr_phy0/nops.read_dll" LOC = DCM_X1Y3;
INST "ddrsp0.ddrc/ddr_phy0/ddr_phy0/xc3se.ddr_phy0/ps.read_dll" LOC = DCM_X1Y3;
INST "ddrsp0.ddrc/ddr_phy0/ddr_phy0/xc3se.ddr_phy0/dll" LOC = DCM_X0Y2;

# Enable this for ISE-10
#PIN  "ddrsp0.ddrc/ddr_phy0/ddr_phy0/xc3se.ddr_phy0/dll.CLK270" CLOCK_DEDICATED_ROUTE = FALSE;
#NET etx_clk CLOCK_DEDICATED_ROUTE = FALSE;
#NET erx_clk CLOCK_DEDICATED_ROUTE = FALSE;
 
NET "ddrsp0.ddrc/ddr_phy0/ddr_phy0/xc3se.ddr_phy0/rclk90b" TNM_NET = "rclk90b"; 
TIMEGRP "rclk270b_rise" = FALLING "rclk90b";
TIMEGRP "clkml_rise" = RISING "clkml";
TIMESPEC "TS_rclk270b_clkml_rise" = FROM "rclk270b_rise" TO "clkml_rise" 4.500;

# ==== Pushbuttons (BTN) ====
#NET "BTN_EAST" LOC = "H13" |  IOSTANDARD = LVTTL | PULLDOWN ;
NET "dsubre" LOC = "H13" |  IOSTANDARD = LVTTL | PULLDOWN ;
#NET "BTN_NORTH" LOC = "V4" |  IOSTANDARD = LVTTL | PULLDOWN ;
#NET "BTN_SOUTH" LOC = "K17" | IOSTANDARD = LVTTL | PULLDOWN ;
NET "reset" LOC = "K17" | IOSTANDARD = LVTTL | PULLDOWN ;
#NET "BTN_WEST" LOC = "D18" | IOSTANDARD = LVTTL | PULLDOWN ;
#NET "btn0"     LOC = "H13" | IOSTANDARD = LVTTL | PULLDOWN ;
#NET "btn1"     LOC = "V4"  | IOSTANDARD = LVTTL | PULLDOWN ;
#NET "btn2"     LOC = "K17" | IOSTANDARD = LVTTL | PULLDOWN ;


# ==== Discrete LEDs (LED) ====
# These are shared connections with the FX2 connector
NET "led(0)" LOC = "R14" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "led(1)" LOC = "C3" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "led(2)" LOC = "E6" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "led(3)" LOC = "D6" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "led(4)" LOC = "D13" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "led(5)" LOC = "A7" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
#NET "led(6)" LOC = "G9"  | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
#NET "dsuact" LOC = "G9"  | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
#NET "led(7)" LOC = "A8"  | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "errorn" LOC = "A8"  | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;

# ==== Rotary Encoder ====
#NET "rotary(0)" LOC = "K18" | IOSTANDARD = LVTTL | PULLUP ;
#NET "rotary(1)" LOC = "G18" | IOSTANDARD = LVTTL | PULLUP ;
#NET "rotary(2)" LOC = "V16" | IOSTANDARD = LVTTL | PULLDOWN ;

# ==== Slide Switches (SW) ====
#NET "sw(0)"  LOC = "L13" | IOSTANDARD = LVTTL | PULLUP ;
#NET "sw(1)"  LOC = "L14" | IOSTANDARD = LVTTL | PULLUP ;
#NET "sw(2)"  LOC = "H18" | IOSTANDARD = LVTTL | PULLUP ;
#NET "sw(3)"  LOC = "N17" | IOSTANDARD = LVTTL | PULLUP ;

# ==== RS-232 Serial Ports (RS232) ====
NET "urxd1"  LOC = "U8" |  IOSTANDARD = LVTTL ;
NET "dsurx"  LOC = "R7" |  IOSTANDARD = LVTTL ;
NET "utxd1"  LOC = "M13" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
NET "dsutx"  LOC = "M14" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;


# ==== DDR SDRAM (SD) ====   (I/O Bank 3, VCCO=2.5V)
NET "ddr_ad(0)"         LOC = "T1" | IOSTANDARD = SSTL2_I ;
NET "ddr_ad(1)"         LOC = "R3" | IOSTANDARD = SSTL2_I ;
NET "ddr_ad(2)"         LOC = "R2" | IOSTANDARD = SSTL2_I ;
NET "ddr_ad(3)"         LOC = "P1" | IOSTANDARD = SSTL2_I ;
NET "ddr_ad(4)"         LOC = "E4" | IOSTANDARD = SSTL2_I ;
NET "ddr_ad(5)"         LOC = "H4" | IOSTANDARD = SSTL2_I ;
NET "ddr_ad(6)"         LOC = "H3" | IOSTANDARD = SSTL2_I ;
NET "ddr_ad(7)"         LOC = "H1" | IOSTANDARD = SSTL2_I ;
NET "ddr_ad(8)"         LOC = "H2" | IOSTANDARD = SSTL2_I ;
NET "ddr_ad(9)"         LOC = "N4" | IOSTANDARD = SSTL2_I ;
NET "ddr_ad(10)"        LOC = "T2" | IOSTANDARD = SSTL2_I ;
NET "ddr_ad(11)"        LOC = "N5" | IOSTANDARD = SSTL2_I ;
NET "ddr_ad(12)"        LOC = "P2" | IOSTANDARD = SSTL2_I ;
NET "ddr_ba(0)"                 LOC = "K5" | IOSTANDARD = SSTL2_I ;
NET "ddr_ba(1)"         LOC = "K6" | IOSTANDARD = SSTL2_I ;
NET "ddr_casb"          LOC = "C2" | IOSTANDARD = SSTL2_I ;
NET "ddr_clk0b"         LOC = "J4" | IOSTANDARD = SSTL2_I ;
NET "ddr_clk0"                  LOC = "J5" | IOSTANDARD = SSTL2_I ;
NET "ddr_cke0"                  LOC = "K3" | IOSTANDARD = SSTL2_I ;
NET "ddr_cs0b"                  LOC = "K4" | IOSTANDARD = SSTL2_I ;
NET "ddr_dq(0)"         LOC = "L2" | IOSTANDARD = SSTL2_I ;
NET "ddr_dq(1)"         LOC = "L1" | IOSTANDARD = SSTL2_I ;
NET "ddr_dq(2)"         LOC = "L3" | IOSTANDARD = SSTL2_I ;
NET "ddr_dq(3)"         LOC = "L4" | IOSTANDARD = SSTL2_I ;
NET "ddr_dq(4)"         LOC = "M3" | IOSTANDARD = SSTL2_I ;
NET "ddr_dq(5)"         LOC = "M4" | IOSTANDARD = SSTL2_I ;
NET "ddr_dq(6)"         LOC = "M5" | IOSTANDARD = SSTL2_I ;
NET "ddr_dq(7)"         LOC = "M6" | IOSTANDARD = SSTL2_I ;
NET "ddr_dq(8)"         LOC = "E2" | IOSTANDARD = SSTL2_I ;
NET "ddr_dq(9)"         LOC = "E1" | IOSTANDARD = SSTL2_I ;
NET "ddr_dq(10)"                LOC = "F1" | IOSTANDARD = SSTL2_I ;
NET "ddr_dq(11)"                LOC = "F2" | IOSTANDARD = SSTL2_I ;
NET "ddr_dq(12)"                LOC = "G6" | IOSTANDARD = SSTL2_I ;
NET "ddr_dq(13)"                LOC = "G5" | IOSTANDARD = SSTL2_I ;
NET "ddr_dq(14)"                LOC = "H6" | IOSTANDARD = SSTL2_I ;
NET "ddr_dq(15)"                LOC = "H5" | IOSTANDARD = SSTL2_I ;
NET "ddr_dm(0)"         LOC = "J2" | IOSTANDARD = SSTL2_I ;
NET "ddr_dqs(0)"        LOC = "L6" | IOSTANDARD = SSTL2_I ;
NET "ddr_rasb"          LOC = "C1" | IOSTANDARD = SSTL2_I ;
NET "ddr_dm(1)"         LOC = "J1" | IOSTANDARD = SSTL2_I ;
NET "ddr_dqs(1)"        LOC = "G3" | IOSTANDARD = SSTL2_I ;
NET "ddr_web"           LOC = "D1" | IOSTANDARD = SSTL2_I ;

Net ddr_clk_fb LOC=B9 | IOSTANDARD = LVCMOS33;

Net etx_clk LOC=T7;
Net etx_clk IOSTANDARD = LVCMOS33;
Net erx_clk LOC=V3 ;
Net erx_clk IOSTANDARD = LVCMOS33;
Net erx_crs LOC=U13;
Net erx_crs IOSTANDARD = LVCMOS33;
Net erx_dv LOC=V2;
Net erx_dv IOSTANDARD = LVCMOS33;
Net erxd(0) LOC=V8;
Net erxd(0) IOSTANDARD = LVCMOS33;
Net erxd(1) LOC=T11;
Net erxd(1) IOSTANDARD = LVCMOS33;
Net erxd(2) LOC=U11;
Net erxd(2) IOSTANDARD = LVCMOS33;
Net erxd(3) LOC=V14;
Net erxd(3) IOSTANDARD = LVCMOS33;
Net erx_col LOC=U6;
Net erx_col IOSTANDARD = LVCMOS33;
Net erx_er LOC=U14;
Net erx_er IOSTANDARD = LVCMOS33;
Net etx_en LOC=P16;
Net etx_en IOSTANDARD = LVCMOS33;
Net etxd(0) LOC=R11;
Net etxd(0) IOSTANDARD = LVCMOS33;
Net etxd(1) LOC=T15;
Net etxd(1) IOSTANDARD = LVCMOS33;
Net etxd(2) LOC=R5;
Net etxd(2) IOSTANDARD = LVCMOS33;
Net etxd(3) LOC=T5;
Net etxd(3) IOSTANDARD = LVCMOS33;
Net etx_er LOC=R6 | IOSTANDARD = LVCMOS33;
Net emdc LOC=P9;
Net emdc IOSTANDARD = LVCMOS33;
Net emdio LOC=U5;
Net emdio IOSTANDARD = LVCMOS33;

Net address(23) LOC=N11 | IOSTANDARD = LVCMOS33;
Net address(22) LOC=V12 | IOSTANDARD = LVCMOS33;
Net address(21) LOC=V13 | IOSTANDARD = LVCMOS33;
Net address(20) LOC=T12 | IOSTANDARD = LVCMOS33;
Net address(19) LOC=V15 | IOSTANDARD = LVCMOS33;
Net address(18) LOC=U15 | IOSTANDARD = LVCMOS33;
Net address(17) LOC=T16 | IOSTANDARD = LVCMOS33;
Net address(16) LOC=U18 | IOSTANDARD = LVCMOS33;
Net address(15) LOC=T17 | IOSTANDARD = LVCMOS33;
Net address(14) LOC=R18 | IOSTANDARD = LVCMOS33;
Net address(13) LOC=T18 | IOSTANDARD = LVCMOS33;
Net address(12) LOC=L16 | IOSTANDARD = LVCMOS33;
Net address(11) LOC=L15 | IOSTANDARD = LVCMOS33;
Net address(10) LOC=K13 | IOSTANDARD = LVCMOS33;
Net address(9) LOC=K12 | IOSTANDARD = LVCMOS33;
Net address(8) LOC=K15 | IOSTANDARD = LVCMOS33;
Net address(7) LOC=K14 | IOSTANDARD = LVCMOS33;
Net address(6) LOC=J17 | IOSTANDARD = LVCMOS33;
Net address(5) LOC=J16 | IOSTANDARD = LVCMOS33;
Net address(4) LOC=J15 | IOSTANDARD = LVCMOS33;
Net address(3) LOC=J14 | IOSTANDARD = LVCMOS33;
Net address(2) LOC=J12 | IOSTANDARD = LVCMOS33;
Net address(1) LOC=J13 | IOSTANDARD = LVCMOS33;
Net address(0) LOC=H17 | IOSTANDARD = LVCMOS33;

Net data(15) LOC=T8 | IOSTANDARD = LVCMOS33;
Net data(14) LOC=R8 | IOSTANDARD = LVCMOS33;
Net data(13) LOC=P6 | IOSTANDARD = LVCMOS33;
Net data(12) LOC=M16 | IOSTANDARD = LVCMOS33;
Net data(11) LOC=M15 | IOSTANDARD = LVCMOS33;
Net data(10) LOC=P17 | IOSTANDARD = LVCMOS33;
Net data(9) LOC=R16 | IOSTANDARD = LVCMOS33;
Net data(8) LOC=R15 | IOSTANDARD = LVCMOS33;
Net data(7) LOC=N9 | IOSTANDARD = LVCMOS33;
Net data(6) LOC=M9 | IOSTANDARD = LVCMOS33;
Net data(5) LOC=R9 | IOSTANDARD = LVCMOS33;
Net data(4) LOC=U9 | IOSTANDARD = LVCMOS33;
Net data(3) LOC=V9 | IOSTANDARD = LVCMOS33;
Net data(2) LOC=R10 | IOSTANDARD = LVCMOS33;
Net data(1) LOC=P10 | IOSTANDARD = LVCMOS33;
Net data(0) LOC=N10 | IOSTANDARD = LVCMOS33;
Net oen LOC=C18  | IOSTANDARD = LVCMOS33;
Net writen LOC=D17 | IOSTANDARD = LVCMOS33;
Net romsn LOC=D16 | IOSTANDARD = LVCMOS33;
Net byten LOC=C17 | IOSTANDARD = LVCMOS33;
Net sts LOC=B18 ;

NET ps2data LOC = G13 | IOSTANDARD = LVCMOS33;
NET ps2clk  LOC = G14 | IOSTANDARD = LVCMOS33;

NET vid_r  LOC = H14 | IOSTANDARD = LVCMOS33;
NET vid_g  LOC = H15 | IOSTANDARD = LVCMOS33;
NET vid_b  LOC = G15 | IOSTANDARD = LVCMOS33;
NET vid_hsync  LOC = F15 | IOSTANDARD = LVCMOS33;
NET vid_vsync  LOC = F14 | IOSTANDARD = LVCMOS33;

NET spi LOC=U3 | PULLUP;  ## This is to force the SPI ROM to not be selected(drive high)
Net spi IOSTANDARD = LVCMOS33;


# Prohibit VREF pins
CONFIG PROHIBIT = D2;
CONFIG PROHIBIT = G4;
CONFIG PROHIBIT = J6;
CONFIG PROHIBIT = L5;
CONFIG PROHIBIT = R4;