Subversion Repositories mips_enhanced

sh mkdir synopsys
sh mkdir synopsys/grlib 
define_design_lib grlib -path synopsys/grlib 
analyze -f VHDL -library grlib ../../lib/grlib/stdlib/version.vhd
analyze -f VHDL -library grlib ../../lib/grlib/stdlib/stdlib.vhd
analyze -f VHDL -library grlib ../../lib/grlib/sparc/sparc.vhd
analyze -f VHDL -library grlib ../../lib/grlib/modgen/multlib.vhd
analyze -f VHDL -library grlib ../../lib/grlib/modgen/leaves.vhd
analyze -f VHDL -library grlib ../../lib/grlib/amba/amba.vhd
analyze -f VHDL -library grlib ../../lib/grlib/amba/devices.vhd
analyze -f VHDL -library grlib ../../lib/grlib/amba/defmst.vhd
analyze -f VHDL -library grlib ../../lib/grlib/amba/apbctrl.vhd
analyze -f VHDL -library grlib ../../lib/grlib/amba/ahbctrl.vhd
analyze -f VHDL -library grlib ../../lib/grlib/amba/dma2ahb_pkg.vhd
analyze -f VHDL -library grlib ../../lib/grlib/amba/dma2ahb.vhd
sh mkdir synopsys/unisim 
define_design_lib unisim -path synopsys/unisim 
sh mkdir synopsys/synplify 
define_design_lib synplify -path synopsys/synplify 
sh mkdir synopsys/techmap 
define_design_lib techmap -path synopsys/techmap 
analyze -f VHDL -library techmap ../../lib/techmap/gencomp/gencomp.vhd
analyze -f VHDL -library techmap ../../lib/techmap/gencomp/netcomp.vhd
analyze -f VHDL -library techmap ../../lib/techmap/inferred/memory_inferred.vhd
analyze -f VHDL -library techmap ../../lib/techmap/inferred/ddr_inferred.vhd
analyze -f VHDL -library techmap ../../lib/techmap/inferred/mul_inferred.vhd
analyze -f VHDL -library techmap ../../lib/techmap/inferred/ddr_phy_inferred.vhd
analyze -f VHDL -library techmap ../../lib/techmap/dw02/mul_dw_gen.vhd
analyze -f VHDL -library techmap ../../lib/techmap/maps/allclkgen.vhd
analyze -f VHDL -library techmap ../../lib/techmap/maps/allddr.vhd
analyze -f VHDL -library techmap ../../lib/techmap/maps/allmem.vhd
analyze -f VHDL -library techmap ../../lib/techmap/maps/allpads.vhd
analyze -f VHDL -library techmap ../../lib/techmap/maps/alltap.vhd
analyze -f VHDL -library techmap ../../lib/techmap/maps/clkgen.vhd
analyze -f VHDL -library techmap ../../lib/techmap/maps/clkmux.vhd
analyze -f VHDL -library techmap ../../lib/techmap/maps/clkand.vhd
analyze -f VHDL -library techmap ../../lib/techmap/maps/ddr_ireg.vhd
analyze -f VHDL -library techmap ../../lib/techmap/maps/ddr_oreg.vhd
analyze -f VHDL -library techmap ../../lib/techmap/maps/ddrphy.vhd
analyze -f VHDL -library techmap ../../lib/techmap/maps/syncram.vhd
analyze -f VHDL -library techmap ../../lib/techmap/maps/syncram64.vhd
analyze -f VHDL -library techmap ../../lib/techmap/maps/syncram_2p.vhd
analyze -f VHDL -library techmap ../../lib/techmap/maps/syncram_dp.vhd
analyze -f VHDL -library techmap ../../lib/techmap/maps/syncfifo.vhd
analyze -f VHDL -library techmap ../../lib/techmap/maps/regfile_3p.vhd
analyze -f VHDL -library techmap ../../lib/techmap/maps/tap.vhd
analyze -f VHDL -library techmap ../../lib/techmap/maps/techbuf.vhd
analyze -f VHDL -library techmap ../../lib/techmap/maps/clkpad.vhd
analyze -f VHDL -library techmap ../../lib/techmap/maps/clkpad_ds.vhd
analyze -f VHDL -library techmap ../../lib/techmap/maps/inpad.vhd
analyze -f VHDL -library techmap ../../lib/techmap/maps/inpad_ds.vhd
analyze -f VHDL -library techmap ../../lib/techmap/maps/iodpad.vhd
analyze -f VHDL -library techmap ../../lib/techmap/maps/iopad.vhd
analyze -f VHDL -library techmap ../../lib/techmap/maps/iopad_ds.vhd
analyze -f VHDL -library techmap ../../lib/techmap/maps/lvds_combo.vhd
analyze -f VHDL -library techmap ../../lib/techmap/maps/odpad.vhd
analyze -f VHDL -library techmap ../../lib/techmap/maps/outpad.vhd
analyze -f VHDL -library techmap ../../lib/techmap/maps/outpad_ds.vhd
analyze -f VHDL -library techmap ../../lib/techmap/maps/toutpad.vhd
analyze -f VHDL -library techmap ../../lib/techmap/maps/skew_outpad.vhd
analyze -f VHDL -library techmap ../../lib/techmap/maps/grspwc_net.vhd
analyze -f VHDL -library techmap ../../lib/techmap/maps/grlfpw_net.vhd
analyze -f VHDL -library techmap ../../lib/techmap/maps/grfpw_net.vhd
analyze -f VHDL -library techmap ../../lib/techmap/maps/mul_61x61.vhd
analyze -f VHDL -library techmap ../../lib/techmap/maps/cpu_disas_net.vhd
analyze -f VHDL -library techmap ../../lib/techmap/maps/grusbhc_net.vhd
analyze -f VHDL -library techmap ../../lib/techmap/maps/ringosc.vhd
analyze -f VHDL -library techmap ../../lib/techmap/maps/ssrctrl_net.vhd
sh mkdir synopsys/spw 
define_design_lib spw -path synopsys/spw 
analyze -f VHDL -library spw ../../lib/spw/comp/spwcomp.vhd
analyze -f VHDL -library spw ../../lib/spw/wrapper/grspw_gen.vhd
sh mkdir synopsys/eth 
define_design_lib eth -path synopsys/eth 
analyze -f VHDL -library eth ../../lib/eth/comp/ethcomp.vhd
analyze -f VHDL -library eth ../../lib/eth/core/greth_pkg.vhd
analyze -f VHDL -library eth ../../lib/eth/core/eth_rstgen.vhd
analyze -f VHDL -library eth ../../lib/eth/core/eth_ahb_mst.vhd
analyze -f VHDL -library eth ../../lib/eth/core/greth_tx.vhd
analyze -f VHDL -library eth ../../lib/eth/core/greth_rx.vhd
analyze -f VHDL -library eth ../../lib/eth/core/grethc.vhd
analyze -f VHDL -library eth ../../lib/eth/wrapper/greth_gen.vhd
analyze -f VHDL -library eth ../../lib/eth/wrapper/greth_gbit_gen.vhd
sh mkdir synopsys/opencores 
define_design_lib opencores -path synopsys/opencores 
analyze -f VHDL -library opencores ../../lib/opencores/occomp/occomp.vhd
analyze -f VHDL -library opencores ../../lib/opencores/can/cancomp.vhd
analyze -f VHDL -library opencores ../../lib/opencores/can/can_top.vhd
analyze -f VHDL -library opencores ../../lib/opencores/can/can_top_core_sync.vhd
analyze -f VHDL -library opencores ../../lib/opencores/i2c/i2c_master_bit_ctrl.vhd
analyze -f VHDL -library opencores ../../lib/opencores/i2c/i2c_master_byte_ctrl.vhd
analyze -f VHDL -library opencores ../../lib/opencores/i2c/i2coc.vhd
analyze -f VERILOG -library opencores ../../lib/opencores/spi/simple_spi_top.v
analyze -f VHDL -library opencores ../../lib/opencores/ata/ud_cnt.vhd
analyze -f VHDL -library opencores ../../lib/opencores/ata/ro_cnt.vhd
analyze -f VHDL -library opencores ../../lib/opencores/ata/atahost_dma_fifo.vhd
analyze -f VHDL -library opencores ../../lib/opencores/ata/atahost_dma_actrl.vhd
analyze -f VHDL -library opencores ../../lib/opencores/ata/atahost_dma_tctrl.vhd
analyze -f VHDL -library opencores ../../lib/opencores/ata/atahost_pio_tctrl.vhd
analyze -f VHDL -library opencores ../../lib/opencores/ata/atahost_pio_actrl.vhd
analyze -f VHDL -library opencores ../../lib/opencores/ata/atahost_controller.vhd
analyze -f VHDL -library opencores ../../lib/opencores/ata/atahost_pio_controller.vhd
analyze -f VHDL -library opencores ../../lib/opencores/ata/ocidec2_controller.vhd
analyze -f VERILOG -library opencores ../../lib/opencores/ac97/ac97_top.v
sh mkdir synopsys/gaisler 
define_design_lib gaisler -path synopsys/gaisler 
analyze -f VHDL -library gaisler ../../lib/gaisler/arith/arith.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/arith/mul32.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/arith/div32.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/memctrl/memctrl.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/memctrl/sdctrl.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/memctrl/sdmctrl.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/memctrl/srctrl.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/memctrl/spimctrl.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/leon3/leon3.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/leon3/reg_zero.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/leon3/mmuconfig.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/leon3/mmuiface.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/leon3/libmmu.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/leon3/libiu.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/leon3/libcache.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/leon3/libproc3.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/leon3/cachemem.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/leon3/mmu_icache.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/leon3/mmu_dcache.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/leon3/mmu_acache.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/leon3/mmutlbcam.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/leon3/mmulrue.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/leon3/mmulru.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/leon3/mmutlb.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/leon3/mmutw.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/leon3/mmu.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/leon3/mmu_cache.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/leon3/acache.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/leon3/dcache.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/leon3/icache.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/leon3/cache.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/leon3/cpu_disasx.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/leon3/grfpwx.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/leon3/mfpwx.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/leon3/grlfpwx.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/leon3/tbufmem.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/leon3/dsu3x.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/leon3/dsu3.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/leon3/proc3.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/leon3/leon3s.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/leon3/leon3cg.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/leon3/irqmp.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/leon3/grfpwxsh.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/leon3/grfpushwx.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/leon3/leon3sh.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/leon3/my_mux.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/leon3/top.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/can/can.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/can/can_mod.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/can/can_oc.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/can/can_mc.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/can/canmux.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/can/can_rd.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/misc/misc.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/misc/rstgen.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/misc/gptimer.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/misc/ahbram.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/misc/ahbtrace.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/misc/ahbmst.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/misc/grgpio.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/misc/ahbstat.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/misc/logan.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/misc/apbps2.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/misc/charrom_package.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/misc/charrom.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/misc/apbvga.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/misc/ahbdma.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/misc/svgactrl.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/misc/i2cmst.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/misc/spictrl.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/misc/i2cslv.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/misc/wild.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/misc/wild2ahb.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/net/net.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/uart/uart.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/uart/libdcom.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/uart/apbuart.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/uart/dcom.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/uart/dcom_uart.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/uart/ahbuart.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/jtag/jtag.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/jtag/libjtagcom.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/jtag/jtagcom.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/jtag/ahbjtag.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/jtag/ahbjtag_bsd.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/greth/ethernet_mac.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/greth/greth.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/greth/greth_gbit.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/greth/grethm.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/spacewire/spacewire.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/spacewire/grspw.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/spacewire/grspw2.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/spacewire/grspwm.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/usb/grusb.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/ata/ata.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/ata/ata_inf.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/ata/atahost_amba_slave.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/ata/atahost_ahbmst.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/ata/ocidec2_amba_slave.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/ata/atactrl_nodma.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/ata/atactrl_dma.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/ata/atactrl.vhd
analyze -f VERILOG -library gaisler ../../lib/gaisler/vlog/decode_pipe1.v
analyze -f VERILOG -library gaisler ../../lib/gaisler/vlog/EXEC_stage.v
analyze -f VERILOG -library gaisler ../../lib/gaisler/vlog/ulit.v
analyze -f VERILOG -library gaisler ../../lib/gaisler/vlog/ctl_fsm1.v
analyze -f VERILOG -library gaisler ../../lib/gaisler/vlog/RF_stage1.v
analyze -f VERILOG -library gaisler ../../lib/gaisler/vlog/RF_components1.v
analyze -f VERILOG -library gaisler ../../lib/gaisler/vlog/forward.v
analyze -f VERILOG -library gaisler ../../lib/gaisler/vlog/mips789_defs.v
analyze -f VERILOG -library gaisler ../../lib/gaisler/vlog/hazard_unit.v
analyze -f VERILOG -library gaisler ../../lib/gaisler/vlog/forward.v
analyze -f VERILOG -library gaisler ../../lib/gaisler/vlog/core1.v
sh mkdir synopsys/esa 
define_design_lib esa -path synopsys/esa 
analyze -f VHDL -library esa ../../lib/esa/memoryctrl/memoryctrl.vhd
analyze -f VHDL -library esa ../../lib/esa/memoryctrl/mctrl.vhd
sh mkdir synopsys/micron 
define_design_lib micron -path synopsys/micron 
sh mkdir synopsys/work 
define_design_lib work -path synopsys/work