Subversion Repositories mips_enhanced

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      <association xil_pn:name="Implementation"/>
      <library xil_pn:name="gaisler"/>
    </file>
    <file xil_pn:name="../../lib/gaisler/misc/spictrl.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation"/>
      <association xil_pn:name="Implementation"/>
      <library xil_pn:name="gaisler"/>
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    <file xil_pn:name="../../lib/gaisler/misc/i2cslv.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation"/>
      <association xil_pn:name="Implementation"/>
      <library xil_pn:name="gaisler"/>
    </file>
    <file xil_pn:name="../../lib/gaisler/misc/wild.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation"/>
      <association xil_pn:name="Implementation"/>
      <library xil_pn:name="gaisler"/>
    </file>
    <file xil_pn:name="../../lib/gaisler/misc/wild2ahb.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation"/>
      <association xil_pn:name="Implementation"/>
      <library xil_pn:name="gaisler"/>
    </file>
    <file xil_pn:name="../../lib/gaisler/net/net.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation"/>
      <association xil_pn:name="Implementation"/>
      <library xil_pn:name="gaisler"/>
    </file>
    <file xil_pn:name="../../lib/gaisler/uart/uart.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation"/>
      <association xil_pn:name="Implementation"/>
      <library xil_pn:name="gaisler"/>
    </file>
    <file xil_pn:name="../../lib/gaisler/uart/libdcom.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation"/>
      <association xil_pn:name="Implementation"/>
      <library xil_pn:name="gaisler"/>
    </file>
    <file xil_pn:name="../../lib/gaisler/uart/apbuart.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation"/>
      <association xil_pn:name="Implementation"/>
      <library xil_pn:name="gaisler"/>
    </file>
    <file xil_pn:name="../../lib/gaisler/uart/dcom.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation"/>
      <association xil_pn:name="Implementation"/>
      <library xil_pn:name="gaisler"/>
    </file>
    <file xil_pn:name="../../lib/gaisler/uart/dcom_uart.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation"/>
      <association xil_pn:name="Implementation"/>
      <library xil_pn:name="gaisler"/>
    </file>
    <file xil_pn:name="../../lib/gaisler/uart/ahbuart.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation"/>
      <association xil_pn:name="Implementation"/>
      <library xil_pn:name="gaisler"/>
    </file>
    <file xil_pn:name="../../lib/gaisler/jtag/jtag.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation"/>
      <association xil_pn:name="Implementation"/>
      <library xil_pn:name="gaisler"/>
    </file>
    <file xil_pn:name="../../lib/gaisler/jtag/libjtagcom.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation"/>
      <association xil_pn:name="Implementation"/>
      <library xil_pn:name="gaisler"/>
    </file>
    <file xil_pn:name="../../lib/gaisler/jtag/jtagcom.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation"/>
      <association xil_pn:name="Implementation"/>
      <library xil_pn:name="gaisler"/>
    </file>
    <file xil_pn:name="../../lib/gaisler/jtag/ahbjtag.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation"/>
      <association xil_pn:name="Implementation"/>
      <library xil_pn:name="gaisler"/>
    </file>
    <file xil_pn:name="../../lib/gaisler/jtag/ahbjtag_bsd.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation"/>
      <association xil_pn:name="Implementation"/>
      <library xil_pn:name="gaisler"/>
    </file>
    <file xil_pn:name="../../lib/gaisler/greth/ethernet_mac.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation"/>
      <association xil_pn:name="Implementation"/>
      <library xil_pn:name="gaisler"/>
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    <file xil_pn:name="../../lib/gaisler/greth/greth.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation"/>
      <association xil_pn:name="Implementation"/>
      <library xil_pn:name="gaisler"/>
    </file>
    <file xil_pn:name="../../lib/gaisler/greth/greth_gbit.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation"/>
      <association xil_pn:name="Implementation"/>
      <library xil_pn:name="gaisler"/>
    </file>
    <file xil_pn:name="../../lib/gaisler/greth/grethm.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation"/>
      <association xil_pn:name="Implementation"/>
      <library xil_pn:name="gaisler"/>
    </file>
    <file xil_pn:name="../../lib/gaisler/spacewire/spacewire.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation"/>
      <association xil_pn:name="Implementation"/>
      <library xil_pn:name="gaisler"/>
    </file>
    <file xil_pn:name="../../lib/gaisler/spacewire/grspw.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation"/>
      <association xil_pn:name="Implementation"/>
      <library xil_pn:name="gaisler"/>
    </file>
    <file xil_pn:name="../../lib/gaisler/spacewire/grspw2.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation"/>
      <association xil_pn:name="Implementation"/>
      <library xil_pn:name="gaisler"/>
    </file>
    <file xil_pn:name="../../lib/gaisler/spacewire/grspwm.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation"/>
      <association xil_pn:name="Implementation"/>
      <library xil_pn:name="gaisler"/>
    </file>
    <file xil_pn:name="../../lib/gaisler/usb/grusb.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation"/>
      <association xil_pn:name="Implementation"/>
      <library xil_pn:name="gaisler"/>
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    <file xil_pn:name="../../lib/gaisler/ata/ata.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation"/>
      <association xil_pn:name="Implementation"/>
      <library xil_pn:name="gaisler"/>
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    <file xil_pn:name="../../lib/gaisler/ata/ata_inf.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation"/>
      <association xil_pn:name="Implementation"/>
      <library xil_pn:name="gaisler"/>
    </file>
    <file xil_pn:name="../../lib/gaisler/ata/atahost_amba_slave.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation"/>
      <association xil_pn:name="Implementation"/>
      <library xil_pn:name="gaisler"/>
    </file>
    <file xil_pn:name="../../lib/gaisler/ata/atahost_ahbmst.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation"/>
      <association xil_pn:name="Implementation"/>
      <library xil_pn:name="gaisler"/>
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    <file xil_pn:name="../../lib/gaisler/ata/ocidec2_amba_slave.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation"/>
      <association xil_pn:name="Implementation"/>
      <library xil_pn:name="gaisler"/>
    </file>
    <file xil_pn:name="../../lib/gaisler/ata/atactrl_nodma.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation"/>
      <association xil_pn:name="Implementation"/>
      <library xil_pn:name="gaisler"/>
    </file>
    <file xil_pn:name="../../lib/gaisler/ata/atactrl_dma.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation"/>
      <association xil_pn:name="Implementation"/>
      <library xil_pn:name="gaisler"/>
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    <file xil_pn:name="../../lib/gaisler/ata/atactrl.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation"/>
      <association xil_pn:name="Implementation"/>
      <library xil_pn:name="gaisler"/>
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    <file xil_pn:name="../../lib/esa/memoryctrl/memoryctrl.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation"/>
      <association xil_pn:name="Implementation"/>
      <library xil_pn:name="esa"/>
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    <file xil_pn:name="../../lib/esa/memoryctrl/mctrl.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation"/>
      <association xil_pn:name="Implementation"/>
      <library xil_pn:name="esa"/>
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    <file xil_pn:name="../../lib/gaisler/vlog/core1.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation"/>
      <association xil_pn:name="Implementation"/>
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    <file xil_pn:name="../../lib/gaisler/vlog/ctl_fsm1.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation"/>
      <association xil_pn:name="Implementation"/>
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    <file xil_pn:name="../../lib/gaisler/vlog/decode_pipe1.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation"/>
      <association xil_pn:name="Implementation"/>
    </file>
    <file xil_pn:name="../../lib/gaisler/vlog/EXEC_stage.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation"/>
      <association xil_pn:name="Implementation"/>
    </file>
    <file xil_pn:name="../../lib/gaisler/vlog/forward.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation"/>
      <association xil_pn:name="Implementation"/>
    </file>
    <file xil_pn:name="../../lib/gaisler/vlog/hazard_unit.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation"/>
      <association xil_pn:name="Implementation"/>
    </file>
    <file xil_pn:name="../../lib/gaisler/vlog/mem_module.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation"/>
      <association xil_pn:name="Implementation"/>
    </file>
    <file xil_pn:name="../../lib/gaisler/vlog/mips789_defs.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation"/>
      <association xil_pn:name="Implementation"/>
    </file>
    <file xil_pn:name="../../lib/gaisler/vlog/RF_components1.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation"/>
      <association xil_pn:name="Implementation"/>
    </file>
    <file xil_pn:name="../../lib/gaisler/vlog/RF_stage1.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation"/>
      <association xil_pn:name="Implementation"/>
    </file>
    <file xil_pn:name="../../lib/gaisler/vlog/ulit.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation"/>
      <association xil_pn:name="Implementation"/>
    </file>
    <file xil_pn:name="../../lib/gaisler/vlog/vlogsyn.txt" xil_pn:type="FILE_USERDOC"/>
  </files>

  <properties>
    <property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="true"/>
    <property xil_pn:name="Bus Delimiter" xil_pn:value="()"/>
    <property xil_pn:name="Constraints Entry" xil_pn:value="Constraints Editor"/>
    <property xil_pn:name="Device" xil_pn:value="xc3s1500"/>
    <property xil_pn:name="Device Family" xil_pn:value="Spartan3"/>
    <property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="None"/>
    <property xil_pn:name="Fitter Report Format" xil_pn:value="HTML"/>
    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|leon3mp|rtl"/>
    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/leon3mp"/>
    <property xil_pn:name="Macro Search Path" xil_pn:value="../../netlists/xilinx/spartan3"/>
    <property xil_pn:name="Other Map Command Line Options" xil_pn:value="-timing"/>
    <property xil_pn:name="PROP_DesignName" xil_pn:value="leon3mp"/>
    <property xil_pn:name="PROP_xilxBitgCfg_GenOpt_MaskFile_virtex2" xil_pn:value="true"/>
    <property xil_pn:name="PROP_xilxBitgCfg_GenOpt_ReadBack_virtex2" xil_pn:value="true"/>
    <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Yes"/>
    <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="For Inputs and Outputs"/>
    <property xil_pn:name="Package" xil_pn:value="fg456"/>
    <property xil_pn:name="Preferred Language" xil_pn:value="Verilog"/>
    <property xil_pn:name="Simulator" xil_pn:value="Modelsim-SE Mixed"/>
    <property xil_pn:name="Speed Grade" xil_pn:value="-4"/>
    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)"/>
    <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL"/>
    <property xil_pn:name="Verbose Property Persistence" xil_pn:value="false"/>
  </properties>

  <bindings/>

  <libraries>
    <library xil_pn:name="esa"/>
    <library xil_pn:name="eth"/>
    <library xil_pn:name="gaisler"/>
    <library xil_pn:name="grlib"/>
    <library xil_pn:name="opencores"/>
    <library xil_pn:name="spw"/>
    <library xil_pn:name="synplify"/>
    <library xil_pn:name="techmap"/>
    <library xil_pn:name="unisim"/>
  </libraries>

  <partitions>
    <partition xil_pn:name="/leon3mp"/>
  </partitions>

</project>