OpenCores
URL https://opencores.org/ocsvn/mips_enhanced/mips_enhanced/trunk

Subversion Repositories mips_enhanced

[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [designs/] [leon3-gr-xc3s-1500/] [libero_sim_files] - Rev 2

Compare with Previous | Blame | View Log

LIST ExcludePackageForSynthesis
LIST leon3mp
VALUE "<project>/../../lib/grlib/stdlib/stdio.vhd,hdl"
VALUE "<project>/../../lib/grlib/util/util.vhd,hdl"
VALUE "<project>/../../lib/grlib/sparc/sparc_disas.vhd,hdl"
VALUE "<project>/../../lib/grlib/sparc/cpu_disas.vhd,hdl"
VALUE "<project>/../../lib/grlib/amba/dma2ahb_tp.vhd,hdl"
VALUE "<project>/../../lib/synplify/sim/synplify.vhd,hdl"
VALUE "<project>/../../lib/synplify/sim/synattr.vhd,hdl"
VALUE "<project>/../../lib/opencores/ata/ata_device_oc.v,hdl"
VALUE "<project>/../../lib/gaisler/sim/i2c_slave_model.v,hdl"
VALUE "<project>/../../lib/gaisler/sim/sim.vhd,hdl"
VALUE "<project>/../../lib/gaisler/sim/sram.vhd,hdl"
VALUE "<project>/../../lib/gaisler/sim/ata_device.vhd,hdl"
VALUE "<project>/../../lib/gaisler/sim/sram16.vhd,hdl"
VALUE "<project>/../../lib/gaisler/sim/phy.vhd,hdl"
VALUE "<project>/../../lib/gaisler/sim/ahbrep.vhd,hdl"
VALUE "<project>/../../lib/gaisler/jtag/jtagtst.vhd,hdl"
VALUE "<project>/../../lib/micron/sdram/mobile_sdr.v,hdl"
VALUE "<project>/../../lib/micron/sdram/components.vhd,hdl"
VALUE "<project>/../../lib/micron/sdram/mt48lc16m16a2.vhd,hdl"
VALUE "<project>/../../lib/work/debug/debug.vhd,hdl"
VALUE "<project>/../../lib/work/debug/grtestmod.vhd,hdl"
VALUE "<project>/../../lib/work/debug/cpu_disas.vhd,hdl"
VALUE "<project>/config.vhd,hdl"
VALUE "<project>/ahbrom.vhd,hdl"
VALUE "<project>/vga_clkgen.vhd,hdl"
VALUE "<project>/leon3mp.vhd,hdl"
VALUE "<project>/testbench.vhd,hdl"
VALUE "<project>/testbench.vhd,hdl"

Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.