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Subversion Repositories mips_enhanced
[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [designs/] [leon3-gr-xc3s-1500/] [modelsim/] [gaisler/] [alu_we_reg/] [_primary.vhd] - Rev 2
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library verilog; use verilog.vl_types.all; entity alu_we_reg is port( alu_we_i : in vl_logic_vector(0 downto 0); alu_we_o : out vl_logic_vector(0 downto 0); clk : in vl_logic; hold : in vl_logic ); end alu_we_reg;