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[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [designs/] [leon3-gr-xc3s-1500/] [modelsim/] [gaisler/] [dmem_ctl_reg_cls/] [_primary.vhd] - Rev 2
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library verilog; use verilog.vl_types.all; entity dmem_ctl_reg_cls is port( dmem_ctl_i : in vl_logic_vector(4 downto 0); dmem_ctl_o : out vl_logic_vector(4 downto 0); clk : in vl_logic; cls : in vl_logic; hold : in vl_logic ); end dmem_ctl_reg_cls;