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https://opencores.org/ocsvn/mips_enhanced/mips_enhanced/trunk
Subversion Repositories mips_enhanced
[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [designs/] [leon3-gr-xc3s-1500/] [modelsim/] [gaisler/] [ext/] [_primary.vhd] - Rev 2
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library verilog; use verilog.vl_types.all; entity ext is port( ins_i : in vl_logic_vector(31 downto 0); res : out vl_logic_vector(31 downto 0); ctl : in vl_logic_vector(2 downto 0) ); end ext;