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https://opencores.org/ocsvn/mips_enhanced/mips_enhanced/trunk
Subversion Repositories mips_enhanced
[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [designs/] [leon3-gr-xc3s-1500/] [modelsim/] [opencores/] [ac97_dma_if/] [_primary.vhd] - Rev 2
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library verilog; use verilog.vl_types.all; entity ac97_dma_if is port( clk : in vl_logic; rst : in vl_logic; o3_status : in vl_logic_vector(1 downto 0); o4_status : in vl_logic_vector(1 downto 0); o6_status : in vl_logic_vector(1 downto 0); o7_status : in vl_logic_vector(1 downto 0); o8_status : in vl_logic_vector(1 downto 0); o9_status : in vl_logic_vector(1 downto 0); o3_empty : in vl_logic; o4_empty : in vl_logic; o6_empty : in vl_logic; o7_empty : in vl_logic; o8_empty : in vl_logic; o9_empty : in vl_logic; i3_status : in vl_logic_vector(1 downto 0); i4_status : in vl_logic_vector(1 downto 0); i6_status : in vl_logic_vector(1 downto 0); i3_full : in vl_logic; i4_full : in vl_logic; i6_full : in vl_logic; oc0_cfg : in vl_logic_vector(7 downto 0); oc1_cfg : in vl_logic_vector(7 downto 0); oc2_cfg : in vl_logic_vector(7 downto 0); oc3_cfg : in vl_logic_vector(7 downto 0); oc4_cfg : in vl_logic_vector(7 downto 0); oc5_cfg : in vl_logic_vector(7 downto 0); ic0_cfg : in vl_logic_vector(7 downto 0); ic1_cfg : in vl_logic_vector(7 downto 0); ic2_cfg : in vl_logic_vector(7 downto 0); dma_req : out vl_logic_vector(8 downto 0); dma_ack : in vl_logic_vector(8 downto 0) ); end ac97_dma_if;