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Subversion Repositories mips_enhanced
[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [designs/] [leon3-gr-xc3s-1500/] [modelsim/] [opencores/] [ac97_soc/] [_primary.vhd] - Rev 2
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library verilog; use verilog.vl_types.all; entity ac97_soc is port( clk : in vl_logic; wclk : in vl_logic; rst : in vl_logic; ps_ce : in vl_logic; resume : in vl_logic; suspended : out vl_logic; sync : out vl_logic; out_le : out vl_logic_vector(5 downto 0); in_valid : out vl_logic_vector(2 downto 0); ld : out vl_logic; valid : out vl_logic ); end ac97_soc;