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Subversion Repositories mips_enhanced
[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [designs/] [leon3-gr-xc3s-1500/] [modelsim/] [opencores/] [simple_spi_top/] [_primary.vhd] - Rev 2
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library verilog; use verilog.vl_types.all; entity simple_spi_top is port( prdata_o : out vl_logic_vector(7 downto 0); pirq_o : out vl_logic; sck_o : out vl_logic; mosi_o : out vl_logic; ssn_o : out vl_logic_vector(7 downto 0); pclk_i : in vl_logic; prst_i : in vl_logic; psel_i : in vl_logic; penable_i : in vl_logic; paddr_i : in vl_logic_vector(2 downto 0); pwrite_i : in vl_logic; pwdata_i : in vl_logic_vector(7 downto 0); miso_i : in vl_logic ); end simple_spi_top;