URL
https://opencores.org/ocsvn/mips_enhanced/mips_enhanced/trunk
Subversion Repositories mips_enhanced
[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [designs/] [leon3-xilinx-ml501/] [leon3mp.xcf] - Rev 2
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NET sram_clk FEEDBACK = 1.0 NET sram_clk_fb;
NET "clkm" TNM_NET = "clkm";
NET "clkml" TNM_NET = "clkml";
TIMESPEC "TS_clkm_clkml" = FROM "clkm" TO "clkml" TIG;
TIMESPEC "TS_clkml_clkm" = FROM "clkml" TO "clkm" TIG;
#NET "lock" TIG;
NET phy_tx_data(*) TNM = gtxphypads;
NET "egtx_clk" TNM_NET = "egtx_clk";
TIMESPEC "TS_clkm_egtx_clk" = FROM "clkm" TO "egtx_clk" TIG;
TIMESPEC "TS_egtx_clk_clkm" = FROM "egtx_clk" TO "clkm" TIG;
#TIMESPEC "TSGTXOUT" = FROM "egtx_clk" TO "gtxphypads" 4.3 ns;
#TIMESPEC "TSGRXIN" = FROM "gtxphypads" TO "eth1_e1_m1000_u0_rxclk" 10 ns;
NET clk_100 period = 10.000 ;
NET clk_200 period = 5.000;
INST "ddrsp0.ddrc0/ddr_phy0/ddr_phy0/xc4v.ddr_phy0/idelctrl[0].u" LOC = "IDELAYCTRL_X2Y4";
INST "ddrsp0.ddrc0/ddr_phy0/ddr_phy0/xc4v.ddr_phy0/idelctrl[1].u" LOC = "IDELAYCTRL_X2Y3";
INST "ddrsp0.ddrc0/ddr_phy0/ddr_phy0/xc4v.ddr_phy0/idelctrl[2].u" LOC = "IDELAYCTRL_X2Y2";
INST "ddrsp0.ddrc0/ddr_phy0/ddr_phy0/xc4v.ddr_phy0/idelctrl[3].u" LOC = "IDELAYCTRL_X0Y0";
NET sys_rst_in PULLUP;
NET sys_rst_in TIG;