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[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [designs/] [leon3-xilinx-xc3sd-1800/] [ahbrom.vhd] - Rev 2
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---------------------------------------------------------------------------- -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2004 GAISLER RESEARCH -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- See the file COPYING for the full details of the license. -- ----------------------------------------------------------------------------- -- Entity: ahbrom -- File: ahbrom.vhd -- Author: Jiri Gaisler - Gaisler Research -- Description: AHB rom. 0/1-waitstate read ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.amba.all; use grlib.stdlib.all; use grlib.devices.all; entity ahbrom is generic ( hindex : integer := 0; haddr : integer := 0; hmask : integer := 16#fff#; pipe : integer := 0; tech : integer := 0; kbytes : integer := 1); port ( rst : in std_ulogic; clk : in std_ulogic; ahbsi : in ahb_slv_in_type; ahbso : out ahb_slv_out_type ); end; architecture rtl of ahbrom is constant abits : integer := 17; constant bytes : integer := 89996; constant hconfig : ahb_config_type := ( 0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0), 4 => ahb_membar(haddr, '1', '1', hmask), others => zero32); signal romdata : std_logic_vector(31 downto 0); signal addr : std_logic_vector(abits-1 downto 2); signal hsel, hready : std_ulogic; begin ahbso.hresp <= "00"; ahbso.hsplit <= (others => '0'); ahbso.hirq <= (others => '0'); ahbso.hcache <= '1'; ahbso.hconfig <= hconfig; ahbso.hindex <= hindex; reg : process (clk) begin if rising_edge(clk) then addr <= ahbsi.haddr(abits-1 downto 2); end if; end process; p0 : if pipe = 0 generate ahbso.hrdata <= romdata; ahbso.hready <= '1'; end generate; p1 : if pipe = 1 generate reg2 : process (clk) begin if rising_edge(clk) then hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1); hready <= ahbsi.hready; ahbso.hready <= (not rst) or (hsel and hready) or (ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready); ahbso.hrdata <= romdata; end if; end process; end generate; comb : process (addr) begin case conv_integer(addr) is when 16#00000# => romdata <= X"88100000"; when 16#00001# => romdata <= X"09100031"; when 16#00002# => romdata <= X"81C12314"; when 16#00003# => romdata <= X"01000000"; when 16#00004# => romdata <= X"A1480000"; when 16#00005# => romdata <= X"A7500000"; when 16#00006# => romdata <= X"10800836"; when others => romdata <= (others => '-'); end case; end process; -- pragma translate_off bootmsg : report_version generic map ("ahbrom" & tost(hindex) & ": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" ); -- pragma translate_on end;