Subversion Repositories mips_enhanced

set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[0] -to do[0]
set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[1] -to do[1]
set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[2] -to do[2]
set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[3] -to do[3]
set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[4] -to do[4]
set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[5] -to do[5]
set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[6] -to do[6]
set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[7] -to do[7]
set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[8] -to do[8]
set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[9] -to do[9]
set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[10] -to do[10]
set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[11] -to do[11]
set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[12] -to do[12]
set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[13] -to do[13]
set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[14] -to do[14]
set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[15] -to do[15]
set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[16] -to do[16]
set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[17] -to do[17]
set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[18] -to do[18]
set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[19] -to do[19]
set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[20] -to do[20]
set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[21] -to do[21]
set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[22] -to do[22]
set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[23] -to do[23]
set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[24] -to do[24]
set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[25] -to do[25]
set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[26] -to do[26]
set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[27] -to do[27]
set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[28] -to do[28]
set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[29] -to do[29]
set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[30] -to do[30]
set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[31] -to do[31]

set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[0] -to do[0]
set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[1] -to do[1]
set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[2] -to do[2]
set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[3] -to do[3]
set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[4] -to do[4]
set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[5] -to do[5]
set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[6] -to do[6]
set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[7] -to do[7]
set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[8] -to do[8]
set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[9] -to do[9]
set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[10] -to do[10]
set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[11] -to do[11]
set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[12] -to do[12]
set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[13] -to do[13]
set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[14] -to do[14]
set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[15] -to do[15]
set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[16] -to do[16]
set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[17] -to do[17]
set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[18] -to do[18]
set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[19] -to do[19]
set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[20] -to do[20]
set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[21] -to do[21]
set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[22] -to do[22]
set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[23] -to do[23]
set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[24] -to do[24]
set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[25] -to do[25]
set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[26] -to do[26]
set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[27] -to do[27]
set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[28] -to do[28]
set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[29] -to do[29]
set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[30] -to do[30]
set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[31] -to do[31]

set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[0] -to do[0]
set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[1] -to do[1]
set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[2] -to do[2]
set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[3] -to do[3]
set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[4] -to do[4]
set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[5] -to do[5]
set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[6] -to do[6]
set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[7] -to do[7]
set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[8] -to do[8]
set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[9] -to do[9]
set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[10] -to do[10]
set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[11] -to do[11]
set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[12] -to do[12]
set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[13] -to do[13]
set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[14] -to do[14]
set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[15] -to do[15]
set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[16] -to do[16]
set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[17] -to do[17]
set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[18] -to do[18]
set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[19] -to do[19]
set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[20] -to do[20]
set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[21] -to do[21]
set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[22] -to do[22]
set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[23] -to do[23]
set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[24] -to do[24]
set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[25] -to do[25]
set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[26] -to do[26]
set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[27] -to do[27]
set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[28] -to do[28]
set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[29] -to do[29]
set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[30] -to do[30]
set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[31] -to do[31]

set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[0] -to do[0]
set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[1] -to do[1]
set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[2] -to do[2]
set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[3] -to do[3]
set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[4] -to do[4]
set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[5] -to do[5]
set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[6] -to do[6]
set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[7] -to do[7]
set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[8] -to do[8]
set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[9] -to do[9]
set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[10] -to do[10]
set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[11] -to do[11]
set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[12] -to do[12]
set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[13] -to do[13]
set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[14] -to do[14]
set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[15] -to do[15]
set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[16] -to do[16]
set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[17] -to do[17]
set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[18] -to do[18]
set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[19] -to do[19]
set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[20] -to do[20]
set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[21] -to do[21]
set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[22] -to do[22]
set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[23] -to do[23]
set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[24] -to do[24]
set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[25] -to do[25]
set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[26] -to do[26]
set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[27] -to do[27]
set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[28] -to do[28]
set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[29] -to do[29]
set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[30] -to do[30]
set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[31] -to do[31]

set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[0] -to do[0]
set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[1] -to do[1]
set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[2] -to do[2]
set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[3] -to do[3]
set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[4] -to do[4]
set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[5] -to do[5]
set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[6] -to do[6]
set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[7] -to do[7]
set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[8] -to do[8]
set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[9] -to do[9]
set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[10] -to do[10]
set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[11] -to do[11]
set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[12] -to do[12]
set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[13] -to do[13]
set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[14] -to do[14]
set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[15] -to do[15]
set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[16] -to do[16]
set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[17] -to do[17]
set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[18] -to do[18]
set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[19] -to do[19]
set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[20] -to do[20]
set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[21] -to do[21]
set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[22] -to do[22]
set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[23] -to do[23]
set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[24] -to do[24]
set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[25] -to do[25]
set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[26] -to do[26]
set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[27] -to do[27]
set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[28] -to do[28]
set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[29] -to do[29]
set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[30] -to do[30]
set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[31] -to do[31]

set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[0] -to do[0]
set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[1] -to do[1]
set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[2] -to do[2]
set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[3] -to do[3]
set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[4] -to do[4]
set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[5] -to do[5]
set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[6] -to do[6]
set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[7] -to do[7]
set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[8] -to do[8]
set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[9] -to do[9]
set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[10] -to do[10]
set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[11] -to do[11]
set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[12] -to do[12]
set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[13] -to do[13]
set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[14] -to do[14]
set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[15] -to do[15]
set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[16] -to do[16]
set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[17] -to do[17]
set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[18] -to do[18]
set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[19] -to do[19]
set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[20] -to do[20]
set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[21] -to do[21]
set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[22] -to do[22]
set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[23] -to do[23]
set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[24] -to do[24]
set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[25] -to do[25]
set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[26] -to do[26]
set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[27] -to do[27]
set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[28] -to do[28]
set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[29] -to do[29]
set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[30] -to do[30]
set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[31] -to do[31]

set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[0] -to doa[0]
set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[1] -to doa[1]
set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[2] -to doa[2]
set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[3] -to doa[3]
set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[4] -to doa[4]
set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[5] -to doa[5]
set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[6] -to doa[6]
set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[7] -to doa[7]
set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[8] -to doa[8]
set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[9] -to doa[9]
set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[10] -to doa[10]
set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[11] -to doa[11]
set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[12] -to doa[12]
set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[13] -to doa[13]
set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[14] -to doa[14]
set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[15] -to doa[15]
set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[16] -to doa[16]
set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[17] -to doa[17]
set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[18] -to doa[18]
set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[19] -to doa[19]
set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[20] -to doa[20]
set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[21] -to doa[21]
set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[22] -to doa[22]
set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[23] -to doa[23]
set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[24] -to doa[24]
set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[25] -to doa[25]
set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[26] -to doa[26]
set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[27] -to doa[27]
set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[28] -to doa[28]
set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[29] -to doa[29]
set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[30] -to doa[30]
set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[31] -to doa[31]
set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[0] -to dob[0]
set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[1] -to dob[1]
set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[2] -to dob[2]
set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[3] -to dob[3]
set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[4] -to dob[4]
set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[5] -to dob[5]
set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[6] -to dob[6]
set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[7] -to dob[7]
set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[8] -to dob[8]
set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[9] -to dob[9]
set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[10] -to dob[10]
set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[11] -to dob[11]
set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[12] -to dob[12]
set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[13] -to dob[13]
set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[14] -to dob[14]
set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[15] -to dob[15]
set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[16] -to dob[16]
set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[17] -to dob[17]
set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[18] -to dob[18]
set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[19] -to dob[19]
set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[20] -to dob[20]
set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[21] -to dob[21]
set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[22] -to dob[22]
set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[23] -to dob[23]
set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[24] -to dob[24]
set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[25] -to dob[25]
set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[26] -to dob[26]
set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[27] -to dob[27]
set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[28] -to dob[28]
set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[29] -to dob[29]
set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[30] -to dob[30]
set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[31] -to dob[31]

set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[0] -to doa[0]
set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[1] -to doa[1]
set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[2] -to doa[2]
set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[3] -to doa[3]
set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[4] -to doa[4]
set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[5] -to doa[5]
set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[6] -to doa[6]
set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[7] -to doa[7]
set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[8] -to doa[8]
set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[9] -to doa[9]
set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[10] -to doa[10]
set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[11] -to doa[11]
set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[12] -to doa[12]
set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[13] -to doa[13]
set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[14] -to doa[14]
set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[15] -to doa[15]
set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[16] -to doa[16]
set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[17] -to doa[17]
set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[18] -to doa[18]
set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[19] -to doa[19]
set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[20] -to doa[20]
set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[21] -to doa[21]
set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[22] -to doa[22]
set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[23] -to doa[23]
set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[24] -to doa[24]
set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[25] -to doa[25]
set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[26] -to doa[26]
set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[27] -to doa[27]
set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[28] -to doa[28]
set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[29] -to doa[29]
set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[30] -to doa[30]
set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[31] -to doa[31]
set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[0] -to dob[0]
set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[1] -to dob[1]
set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[2] -to dob[2]
set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[3] -to dob[3]
set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[4] -to dob[4]
set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[5] -to dob[5]
set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[6] -to dob[6]
set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[7] -to dob[7]
set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[8] -to dob[8]
set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[9] -to dob[9]
set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[10] -to dob[10]
set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[11] -to dob[11]
set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[12] -to dob[12]
set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[13] -to dob[13]
set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[14] -to dob[14]
set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[15] -to dob[15]
set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[16] -to dob[16]
set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[17] -to dob[17]
set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[18] -to dob[18]
set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[19] -to dob[19]
set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[20] -to dob[20]
set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[21] -to dob[21]
set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[22] -to dob[22]
set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[23] -to dob[23]
set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[24] -to dob[24]
set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[25] -to dob[25]
set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[26] -to dob[26]
set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[27] -to dob[27]
set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[28] -to dob[28]
set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[29] -to dob[29]
set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[30] -to dob[30]
set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[31] -to dob[31]

set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[0] -to doa[0]
set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[1] -to doa[1]
set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[2] -to doa[2]
set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[3] -to doa[3]
set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[4] -to doa[4]
set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[5] -to doa[5]
set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[6] -to doa[6]
set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[7] -to doa[7]
set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[8] -to doa[8]
set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[9] -to doa[9]
set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[10] -to doa[10]
set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[11] -to doa[11]
set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[12] -to doa[12]
set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[13] -to doa[13]
set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[14] -to doa[14]
set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[15] -to doa[15]
set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[16] -to doa[16]
set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[17] -to doa[17]
set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[18] -to doa[18]
set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[19] -to doa[19]
set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[20] -to doa[20]
set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[21] -to doa[21]
set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[22] -to doa[22]
set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[23] -to doa[23]
set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[24] -to doa[24]
set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[25] -to doa[25]
set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[26] -to doa[26]
set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[27] -to doa[27]
set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[28] -to doa[28]
set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[29] -to doa[29]
set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[30] -to doa[30]
set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[31] -to doa[31]
set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[0] -to dob[0]
set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[1] -to dob[1]
set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[2] -to dob[2]
set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[3] -to dob[3]
set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[4] -to dob[4]
set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[5] -to dob[5]
set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[6] -to dob[6]
set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[7] -to dob[7]
set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[8] -to dob[8]
set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[9] -to dob[9]
set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[10] -to dob[10]
set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[11] -to dob[11]
set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[12] -to dob[12]
set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[13] -to dob[13]
set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[14] -to dob[14]
set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[15] -to dob[15]
set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[16] -to dob[16]
set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[17] -to dob[17]
set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[18] -to dob[18]
set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[19] -to dob[19]
set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[20] -to dob[20]
set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[21] -to dob[21]
set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[22] -to dob[22]
set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[23] -to dob[23]
set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[24] -to dob[24]
set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[25] -to dob[25]
set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[26] -to dob[26]
set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[27] -to dob[27]
set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[28] -to dob[28]
set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[29] -to dob[29]
set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[30] -to dob[30]
set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[31] -to dob[31]

set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[0] -to doa[0]
set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[1] -to doa[1]
set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[2] -to doa[2]
set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[3] -to doa[3]
set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[4] -to doa[4]
set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[5] -to doa[5]
set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[6] -to doa[6]
set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[7] -to doa[7]
set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[8] -to doa[8]
set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[9] -to doa[9]
set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[10] -to doa[10]
set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[11] -to doa[11]
set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[12] -to doa[12]
set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[13] -to doa[13]
set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[14] -to doa[14]
set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[15] -to doa[15]
set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[16] -to doa[16]
set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[17] -to doa[17]
set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[18] -to doa[18]
set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[19] -to doa[19]
set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[20] -to doa[20]
set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[21] -to doa[21]
set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[22] -to doa[22]
set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[23] -to doa[23]
set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[24] -to doa[24]
set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[25] -to doa[25]
set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[26] -to doa[26]
set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[27] -to doa[27]
set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[28] -to doa[28]
set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[29] -to doa[29]
set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[30] -to doa[30]
set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[31] -to doa[31]
set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[0] -to dob[0]
set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[1] -to dob[1]
set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[2] -to dob[2]
set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[3] -to dob[3]
set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[4] -to dob[4]
set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[5] -to dob[5]
set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[6] -to dob[6]
set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[7] -to dob[7]
set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[8] -to dob[8]
set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[9] -to dob[9]
set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[10] -to dob[10]
set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[11] -to dob[11]
set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[12] -to dob[12]
set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[13] -to dob[13]
set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[14] -to dob[14]
set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[15] -to dob[15]
set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[16] -to dob[16]
set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[17] -to dob[17]
set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[18] -to dob[18]
set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[19] -to dob[19]
set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[20] -to dob[20]
set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[21] -to dob[21]
set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[22] -to dob[22]
set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[23] -to dob[23]
set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[24] -to dob[24]
set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[25] -to dob[25]
set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[26] -to dob[26]
set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[27] -to dob[27]
set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[28] -to dob[28]
set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[29] -to dob[29]
set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[30] -to dob[30]
set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[31] -to dob[31]

set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[0] -to do[0]
set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[1] -to do[1]
set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[2] -to do[2]
set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[3] -to do[3]
set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[4] -to do[4]
set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[5] -to do[5]
set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[6] -to do[6]
set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[7] -to do[7]
set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[8] -to do[8]
set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[9] -to do[9]
set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[10] -to do[10]
set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[11] -to do[11]
set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[12] -to do[12]
set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[13] -to do[13]
set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[14] -to do[14]
set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[15] -to do[15]
set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[16] -to do[16]
set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[17] -to do[17]
set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[18] -to do[18]
set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[19] -to do[19]
set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[20] -to do[20]
set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[21] -to do[21]
set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[22] -to do[22]
set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[23] -to do[23]
set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[24] -to do[24]
set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[25] -to do[25]
set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[26] -to do[26]
set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[27] -to do[27]
set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[28] -to do[28]
set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[29] -to do[29]
set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[30] -to do[30]
set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[31] -to do[31]
set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[32] -to do[32]
set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[33] -to do[33]

set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[0] -to do[0]
set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[1] -to do[1]
set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[2] -to do[2]
set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[3] -to do[3]
set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[4] -to do[4]
set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[5] -to do[5]
set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[6] -to do[6]
set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[7] -to do[7]
set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[8] -to do[8]
set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[9] -to do[9]
set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[10] -to do[10]
set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[11] -to do[11]
set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[12] -to do[12]
set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[13] -to do[13]
set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[14] -to do[14]
set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[15] -to do[15]
set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[16] -to do[16]
set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[17] -to do[17]
set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[18] -to do[18]
set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[19] -to do[19]
set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[20] -to do[20]
set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[21] -to do[21]
set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[22] -to do[22]
set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[23] -to do[23]
set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[24] -to do[24]
set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[25] -to do[25]
set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[26] -to do[26]
set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[27] -to do[27]
set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[28] -to do[28]
set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[29] -to do[29]
set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[30] -to do[30]
set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[31] -to do[31]
set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[32] -to do[32]
set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[33] -to do[33]

set_disable_timing IO33lib-max+ind/pt33b01 -from pad -to cin
set_disable_timing IO33lib-max+ind/pt33b02 -from pad -to cin
set_disable_timing IO33lib-max+ind/pt33b03 -from pad -to cin
set_disable_timing IO33lib-max+ind/pt33b04 -from pad -to cin
set_disable_timing IO33lib-max+ind/pt33b01u -from pad -to cin
set_disable_timing IO33lib-max+ind/pt33b02u -from pad -to cin
set_disable_timing IO33lib-max+ind/pt33b03u -from pad -to cin
set_disable_timing IO33lib-max+ind/pt33b04u -from pad -to cin