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Use Virtex CLKDLL for clock synchronisation
CONFIG_CLK_INFERRED
  Certain target technologies include clock generators to scale or
  phase-adjust the system and SDRAM clocks. This is currently supported
  for Xilinx, Altera and Proasic3 FPGAs. Depending on technology, you
  can select to use the Xilinx CKLDLL macro (Virtex, VirtexE, Spartan1/2),
  the Xilinx DCM (Virtex-2, Spartan3, Virtex-4), the Altera ALTDLL
  (Stratix, Cyclone), or the Proasic3 PLL. Choose the 'inferred' 
  option to skip a clock generator.

Clock multiplier
CONFIG_CLK_MUL
  When using the Xilinx DCM or Altera ALTPLL, the system clock can
  be multiplied with a factor of 2 - 32, and divided by a factor of
  1 - 32. This makes it possible to generate almost any desired 
  processor frequency. When using the Xilinx CLKDLL generator,
  the resulting frequency scale factor (mul/div) must be one of
  1/2, 1 or 2. On Proasic3, the factor can be 1 - 128.

  WARNING: The resulting clock must be within the limits specified
  by the target FPGA family.

Clock divider
CONFIG_CLK_DIV
  When using the Xilinx DCM or Altera ALTPLL, the system clock can
  be multiplied with a factor of 2 - 32, and divided by a factor of
  1 - 32. This makes it possible to generate almost any desired 
  processor frequency. When using the Xilinx CLKDLL generator,
  the resulting frequency scale factor (mul/div) must be one of
  1/2, 1 or 2. On Proasic3, the factor can be 1 - 128.

  WARNING: The resulting clock must be within the limits specified
  by the target FPGA family.

Output clock divider
CONFIG_OCLK_DIV
  When using the Proasic3 PLL, the system clock is generated by three
  parameters: input clock multiplication, input clock division and
  output clock division. Only certain values of these parameters
  are allowed, but unfortunately this is not documented by Actel.
  To find the correct values, run the Libero Smartgen tool and
  insert you desired input and output clock frequencies in the
  Static PLL configurator. The mul/div factors can then be read
  out from tool.

System clock multiplier
CONFIG_CLKDLL_1_2
  The Xilinx CLKDLL can scale the input clock with a factor of 0.5, 1.0, 
  or 2.0. Useful when the target board has an oscillator with a too high 
  (or low) frequency for your design. The divided clock will be used as the
  main clock for the whole processor (except PCI and ethernet clocks).

System clock multiplier
CONFIG_DCM_2_3
  The Xilinx DCM and Altera ALTDLL can scale the input clock with a large
  range of factors. Useful when the target board has an oscillator with a 
  too high (or low) frequency for your design. The divided clock will
  be used as the main clock for the whole processor (except PCI and 
  ethernet clocks). NOTE: the resulting frequency must be at least
  24 MHz or the DCM and ALTDLL might not work.

Enable CLKDLL for PCI clock
CONFIG_PCI_CLKDLL
  Say Y here to re-synchronize the PCI clock using a 
  Virtex BUFGDLL macro. Will improve PCI clock-to-output 
  delays on the expense of input-setup requirements.

Use PCI clock system clock
CONFIG_PCI_SYSCLK
  Say Y here to the PCI clock to generate the system clock.
  The PCI clock can be scaled using the DCM or CLKDLL to 
  generate a suitable processor clock.

External SDRAM clock feedback
CONFIG_CLK_NOFB
  Say Y here to disable the external clock feedback to synchronize the
  SDRAM clock. This option is necessary if your board or design does not
  have an external clock feedback that is connected to the pllref input
  of the clock generator.