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https://opencores.org/ocsvn/mips_enhanced/mips_enhanced/trunk
Subversion Repositories mips_enhanced
[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [lib/] [techmap/] [gencomp/] [clkgen.in] - Rev 2
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choice 'Clock generator ' \
"Inferred CONFIG_CLK_INFERRED \
Actel-HCLKBUF CONFIG_CLK_HCLKBUF \
Altera-ALTPLL CONFIG_CLK_ALTDLL \
Lattice-EXPLL CONFIG_CLK_LATDLL \
RH-LIB18T-PLL CONFIG_CLK_LIB18T \
Xilinx-CLKDLL CONFIG_CLK_CLKDLL \
Xilinx-DCM CONFIG_CLK_DCM" Inferred
if [ "$CONFIG_CLK_DCM" = "y" -o "$CONFIG_CLK_ALTDLL" = "y" \
-o "$CONFIG_CLK_LATDLL" = "y" \
-o "$CONFIG_CLK_CLKDLL" = "y" -o "$CONFIG_CLK_LIB18T" = "y"]; then
int 'Clock multiplication factor (2 - 32)' CONFIG_CLK_MUL 2
int 'Clock division factor (2 - 32)' CONFIG_CLK_DIV 2
fi
if [ "$CONFIG_CLK_CLKDLL" = "y" -o "$CONFIG_CLK_DCM" = "y" ]; then
bool 'Enable Xilinx CLKDLL for PCI clock' CONFIG_PCI_CLKDLL
fi
if [ "$CONFIG_CLK_DCM" = "y" ]; then
bool 'Disable external feedback for SDRAM clock' CONFIG_CLK_NOFB
fi
if [ "$CONFIG_PCI_ENABLE" != "y" ]; then
bool 'Use PCI clock as system clock' CONFIG_PCI_SYSCLK
fi