Subversion Repositories mjpeg-decoder

# BEGIN Project Options
SET flowvendor = Other
SET vhdlsim = True
SET verilogsim = False
SET workingdirectory = /home/smanz/coregen/coregen/tmp
SET speedgrade = -7
SET simulationfiles = Behavioral
SET asysymbol = False
SET addpads = False
SET device = xc2vp30
SET implementationfiletype = Edif
SET busformat = BusFormatAngleBracketNotRipped
SET foundationsym = False
SET package = ff896
SET createndf = False
SET designentry = VHDL
SET devicefamily = virtex2p
SET formalverification = False
SET removerpms = False
# END Project Options
# BEGIN Select
SELECT Multiplier family Xilinx,_Inc. 8.0
# END Select
# BEGIN Parameters
CSET pipelined=Minimum
CSET output_width=20
CSET asynchronous_clear=false
CSET synchronous_clear=false
CSET memory_type=Distributed_Memory
CSET clock_enable=false
CSET port_a_data=Signed
CSET load_done_output=false
CSET ce_overrides=SCLR_Overrides_CE
CSET nd=false
CSET register_input=false
CSET port_b_width=8
CSET port_b_data=Unsigned
CSET port_b_constant_value=10
CSET port_a_width=12
CSET component_name=jpeg_dequant_multiplier
CSET multiplier_construction=Use_Hybrid
CSET output_options=Non_Registered
CSET port_b_constant=false
CSET reload_options=Stop_During_Reload
CSET rfd=false
CSET reloadable=false
CSET rdy=false
# END Parameters
GENERATE