Subversion Repositories mjpeg-decoder

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-- The following code must appear in the VHDL architecture header:

------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
component jpeg_idct_core_12
        port (
        ND: IN std_logic;
        RDY: OUT std_logic;
        RFD: OUT std_logic;
        CLK: IN std_logic;
        RST: IN std_logic;
        DIN: IN std_logic_VECTOR(11 downto 0);
        DOUT: OUT std_logic_VECTOR(8 downto 0));
end component;

-- COMP_TAG_END ------ End COMPONENT Declaration ------------

-- The following code must appear in the VHDL architecture
-- body. Substitute your own instance name and net names.

------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
your_instance_name : jpeg_idct_core_12
                port map (
                        ND => ND,
                        RDY => RDY,
                        RFD => RFD,
                        CLK => CLK,
                        RST => RST,
                        DIN => DIN,
                        DOUT => DOUT);
-- INST_TAG_END ------ End INSTANTIATION Template ------------

-- You must compile the wrapper file jpeg_idct_core_12.vhd when simulating
-- the core, jpeg_idct_core_12. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".