Subversion Repositories mjpeg-decoder

# BEGIN Project Options
SET flowvendor = Other
SET vhdlsim = True
SET verilogsim = False
SET workingdirectory = /home/smanz/coregen/coregen/tmp
SET speedgrade = -7
SET simulationfiles = Behavioral
SET asysymbol = False
SET addpads = False
SET device = xc2vp30
SET implementationfiletype = Edif
SET busformat = BusFormatAngleBracketNotRipped
SET foundationsym = False
SET package = ff896
SET createndf = False
SET designentry = VHDL
SET devicefamily = virtex2p
SET formalverification = False
SET removerpms = False
# END Project Options
# BEGIN Select
SELECT 2-D_Discrete_Cosine_Transform family Xilinx,_Inc. 2.0
# END Select
# BEGIN Parameters
CSET internal_width=15
CSET has_reset=true
CSET precision_control=Round
CSET component_name=jpeg_idct_core_12
CSET enable_symmetry=false
CSET coefficient_width=15
CSET clock_cycles_per_input_sample=12
CSET operation=IEEE_1180_1990_IDCT
CSET transpose_memory=Block
CSET result_width=9
CSET input_data_type=Signed
CSET input_data_width=12
# END Parameters
GENERATE