Subversion Repositories mjpeg-decoder

# BEGIN Project Options
SET flowvendor = Other
SET vhdlsim = True
SET verilogsim = False
SET workingdirectory = /home/smanz/coregen/coregen/tmp
SET speedgrade = -7
SET simulationfiles = Behavioral
SET asysymbol = False
SET addpads = False
SET device = xc2vp30
SET implementationfiletype = Edif
SET busformat = BusFormatAngleBracketNotRipped
SET foundationsym = False
SET package = ff896
SET createndf = False
SET designentry = VHDL
SET devicefamily = virtex2p
SET formalverification = False
SET removerpms = False
# END Project Options
# BEGIN Select
SELECT RAM-based_Shift_Register family Xilinx,_Inc. 8.0
# END Select
# BEGIN Parameters
CSET aclr=false
CSET ce=true
CSET cepriority=Sync_Overrides_CE
CSET asyncinitval=0000000000000000
CSET depth=64
CSET meminitfile=no_coe_file_loaded
CSET shiftregtype=Fixed_Length
CSET component_name=jpeg_qt_sr
CSET syncinitval=0000000000000000
CSET defaultdata=00000000
CSET syncctrlpriority=Reset_Overrides_Set
CSET defaultdataradix=2
CSET sset=false
CSET asyncinitradix=2
CSET optgoal=Area
CSET ainit=false
CSET sclr=false
CSET width=8
CSET aset=false
CSET syncinitradix=2
CSET readmiffile=false
CSET sinit=false
CSET reglastbit=false
# END Parameters
GENERATE