Subversion Repositories mjpeg-decoder

(edif test (edifVersion 2 0 0) (edifLevel 0) (keywordMap (keywordLevel 0))
(status (written (timeStamp 2008 4 25 17 32 0)
   (author "Xilinx, Inc.")
   (program "Xilinx CORE Generator" (version "Xilinx CORE Generator 8.2.03i"))))
   (comment "                                                                                
      This file is owned and controlled by Xilinx and must be used              
      solely for design, simulation, implementation and creation of             
      design files limited to Xilinx devices or technologies. Use               
      with non-Xilinx devices or technologies is expressly prohibited           
      and immediately terminates your license.                                  
                                                                                
      XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION 'AS IS'             
      SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                   
      XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION           
      AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION               
      OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS                 
      IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                   
      AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE          
      FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY                  
      WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                   
      IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR            
      REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF           
      INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS           
      FOR A PARTICULAR PURPOSE.                                                 
                                                                                
      Xilinx products are not intended for use in life support                  
      appliances, devices, or systems. Use in such applications are             
      expressly prohibited.                                                     
                                                                                
      (c) Copyright 1995-2006 Xilinx, Inc.                                      
      All rights reserved.                                                      
                                                                                
   ")
   (comment "Core parameters: ")
       (comment "c_has_aset = 0 ")
       (comment "c_elaboration_dir = /home/smanz/coregen/coregen/tmp/_cg/ ")
       (comment "c_read_mif = 0 ")
       (comment "c_has_a = 0 ")
       (comment "c_sync_priority = 1 ")
       (comment "c_opt_goal = 0 ")
       (comment "c_has_sclr = 0 ")
       (comment "c_width = 8 ")
       (comment "c_enable_rlocs = 0 ")
       (comment "c_default_data_radix = 1 ")
       (comment "c_generate_mif = 0 ")
       (comment "c_ainit_val = 0000000000000000 ")
       (comment "c_has_ce = 1 ")
       (comment "c_family = virtex2p ")
       (comment "c_has_aclr = 0 ")
       (comment "InstanceName = jpeg_qt_sr ")
       (comment "c_mem_init_radix = 1 ")
       (comment "c_sync_enable = 0 ")
       (comment "c_depth = 64 ")
       (comment "c_has_ainit = 0 ")
       (comment "c_sinit_val = 0000000000000000 ")
       (comment "c_has_sset = 0 ")
       (comment "c_has_sinit = 0 ")
       (comment "c_mem_init_file = no_coe_file_loaded ")
       (comment "c_shift_type = 0 ")
       (comment "c_default_data = 00000000 ")
       (comment "c_reg_last_bit = 0 ")
       (comment "c_addr_width = 4 ")
   (external xilinxun (edifLevel 0)
      (technology (numberDefinition))
       (cell VCC (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port P (direction OUTPUT))
               )
           )
       )
       (cell GND (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port G (direction OUTPUT))
               )
           )
       )
   )
   (external jpeg_qt_sr_c_shift_ram_v8_0_xst_1_lib (edifLevel 0)
       (technology (numberDefinition))
       (cell jpeg_qt_sr_c_shift_ram_v8_0_xst_1 (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port ( array ( rename a "a<3:0>") 4 ) (direction INPUT))
                   (port ( array ( rename d "d<7:0>") 8 ) (direction INPUT))
                   (port clk (direction INPUT))
                   (port ce (direction INPUT))
                   (port aclr (direction INPUT))
                   (port aset (direction INPUT))
                   (port ainit (direction INPUT))
                   (port sclr (direction INPUT))
                   (port sset (direction INPUT))
                   (port sinit (direction INPUT))
                   (port ( array ( rename q "q<7:0>") 8 ) (direction OUTPUT))
               )
           )
       )
   )
(library test_lib (edifLevel 0) (technology (numberDefinition (scale 1 (E 1 -12) (unit Time))))
(cell jpeg_qt_sr
 (cellType GENERIC) (view view_1 (viewType NETLIST)
  (interface
   (port ( array ( rename d "d<7:0>") 8 ) (direction INPUT))
   (port ( rename clk "clk") (direction INPUT))
   (port ( rename ce "ce") (direction INPUT))
   (port ( array ( rename q "q<7:0>") 8 ) (direction OUTPUT))
   )
  (contents
   (instance VCC (viewRef view_1 (cellRef VCC  (libraryRef xilinxun))))
   (instance GND (viewRef view_1 (cellRef GND  (libraryRef xilinxun))))
   (instance BU2
      (viewRef view_1 (cellRef jpeg_qt_sr_c_shift_ram_v8_0_xst_1 (libraryRef jpeg_qt_sr_c_shift_ram_v8_0_xst_1_lib)))
   )
   (net (rename N6 "d<7>")
    (joined
      (portRef (member d 0))
      (portRef (member d 0) (instanceRef BU2))
    )
   )
   (net (rename N7 "d<6>")
    (joined
      (portRef (member d 1))
      (portRef (member d 1) (instanceRef BU2))
    )
   )
   (net (rename N8 "d<5>")
    (joined
      (portRef (member d 2))
      (portRef (member d 2) (instanceRef BU2))
    )
   )
   (net (rename N9 "d<4>")
    (joined
      (portRef (member d 3))
      (portRef (member d 3) (instanceRef BU2))
    )
   )
   (net (rename N10 "d<3>")
    (joined
      (portRef (member d 4))
      (portRef (member d 4) (instanceRef BU2))
    )
   )
   (net (rename N11 "d<2>")
    (joined
      (portRef (member d 5))
      (portRef (member d 5) (instanceRef BU2))
    )
   )
   (net (rename N12 "d<1>")
    (joined
      (portRef (member d 6))
      (portRef (member d 6) (instanceRef BU2))
    )
   )
   (net (rename N13 "d<0>")
    (joined
      (portRef (member d 7))
      (portRef (member d 7) (instanceRef BU2))
    )
   )
   (net (rename N14 "clk")
    (joined
      (portRef clk)
      (portRef clk (instanceRef BU2))
    )
   )
   (net (rename N15 "ce")
    (joined
      (portRef ce)
      (portRef ce (instanceRef BU2))
    )
   )
   (net (rename N22 "q<7>")
    (joined
      (portRef (member q 0))
      (portRef (member q 0) (instanceRef BU2))
    )
   )
   (net (rename N23 "q<6>")
    (joined
      (portRef (member q 1))
      (portRef (member q 1) (instanceRef BU2))
    )
   )
   (net (rename N24 "q<5>")
    (joined
      (portRef (member q 2))
      (portRef (member q 2) (instanceRef BU2))
    )
   )
   (net (rename N25 "q<4>")
    (joined
      (portRef (member q 3))
      (portRef (member q 3) (instanceRef BU2))
    )
   )
   (net (rename N26 "q<3>")
    (joined
      (portRef (member q 4))
      (portRef (member q 4) (instanceRef BU2))
    )
   )
   (net (rename N27 "q<2>")
    (joined
      (portRef (member q 5))
      (portRef (member q 5) (instanceRef BU2))
    )
   )
   (net (rename N28 "q<1>")
    (joined
      (portRef (member q 6))
      (portRef (member q 6) (instanceRef BU2))
    )
   )
   (net (rename N29 "q<0>")
    (joined
      (portRef (member q 7))
      (portRef (member q 7) (instanceRef BU2))
    )
   )
))))
(design jpeg_qt_sr (cellRef jpeg_qt_sr (libraryRef test_lib))
  (property X_CORE_INFO (string "c_shift_ram_v8_0, Coregen 8.2.03i"))
  (property PART (string "xc2vp30-ff896-7") (owner "Xilinx")))
)