Subversion Repositories mjpeg-decoder

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-- You must compile the wrapper file jpeg_idct_core_12.vhd when simulating
-- the core, jpeg_idct_core_12. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
 
-- The synopsys directives "translate_off/translate_on" specified
-- below are supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
 
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synopsys translate_off
Library XilinxCoreLib;
-- synopsys translate_on
ENTITY jpeg_idct_core_12 IS
	port (
	ND: IN std_logic;
	RDY: OUT std_logic;
	RFD: OUT std_logic;
	CLK: IN std_logic;
	RST: IN std_logic;
	DIN: IN std_logic_VECTOR(11 downto 0);
	DOUT: OUT std_logic_VECTOR(8 downto 0));
END jpeg_idct_core_12;
 
ARCHITECTURE jpeg_idct_core_12_a OF jpeg_idct_core_12 IS
-- synopsys translate_off
component wrapped_jpeg_idct_core_12
	port (
	ND: IN std_logic;
	RDY: OUT std_logic;
	RFD: OUT std_logic;
	CLK: IN std_logic;
	RST: IN std_logic;
	DIN: IN std_logic_VECTOR(11 downto 0);
	DOUT: OUT std_logic_VECTOR(8 downto 0));
end component;
 
-- Configuration specification 
	for all : wrapped_jpeg_idct_core_12 use entity XilinxCoreLib.C_DA_2D_DCT_V2_0(behavioral)
		generic map(
			c_clks_per_sample => 12,
			c_result_width => 9,
			c_internal_width => 15,
			c_data_type => 0,
			c_precision_control => 2,
			c_data_width => 12,
			c_operation => 2,
			c_enable_rlocs => 0,
			c_latency => 99,
			c_enable_symmetry => 0,
			c_coeff_width => 15,
			c_shape => 0,
			c_mem_type => 0,
			c_col_latency => 15,
			c_row_latency => 18,
			c_has_reset => 1);
-- synopsys translate_on
BEGIN
-- synopsys translate_off
U0 : wrapped_jpeg_idct_core_12
		port map (
			ND => ND,
			RDY => RDY,
			RFD => RFD,
			CLK => CLK,
			RST => RST,
			DIN => DIN,
			DOUT => DOUT);
-- synopsys translate_on
 
END jpeg_idct_core_12_a;