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[/] [mmcfpgaconfig/] [trunk/] [rtl/] [verilog/] [virtex_bitstream_const.v] - Rev 6
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// Copyright 2004-2005 Openchip // http://www.openchip.org // XAPP-151 `define VIRTEX_CFG_CMD_WCFG 4'b0001 `define VIRTEX_CFG_CMD_LFRM 4'b0011 `define VIRTEX_CFG_CMD_RCFG 4'b0100 `define VIRTEX_CFG_CMD_START 4'b0101 `define VIRTEX_CFG_CMD_RCAP 4'b0110 `define VIRTEX_CFG_CMD_RCRC 4'b0111 `define VIRTEX_CFG_CMD_AGHIGH 4'b1000 `define VIRTEX_CFG_CMD_SWITCH 4'b1001 // Virtex-II/Pro, S-3 `define VIRTEX_CFG_CMD_DESYNC 4'b1101 // XAPP 151 `define VIRTEX_CFG_REG_CRC 4'b0000 `define VIRTEX_CFG_REG_FAR 4'b0001 `define VIRTEX_CFG_REG_FDRI 4'b0010 `define VIRTEX_CFG_REG_FDRO 4'b0011 `define VIRTEX_CFG_REG_CMD 4'b0100 `define VIRTEX_CFG_REG_CTL 4'b0101 `define VIRTEX_CFG_REG_MASK 4'b0110 `define VIRTEX_CFG_REG_STAT 4'b0111 `define VIRTEX_CFG_REG_LOUT 4'b1000 `define VIRTEX_CFG_REG_COR 4'b1001 `define VIRTEX_CFG_REG_FLR 4'b1011 // Virtex-II `define VIRTEX_CFG_REG_RES_E 4'b1110 // XAPP 151 `define VIRTEX_CFG_OP_READ 2'b01 `define VIRTEX_CFG_OP_WRITE 2'b10